JP2614711B2 - Double tone generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic musical sound synthesis, and more particularly to a double tone generator that generates double tone in response to an activated key switch.

[Conventional technology]

Electronic keyboard instruments can be classified as either single-tone generators or fortune generators. Single-tone instruments are limited to producing only one sound at a time. Activating more than one key switch at the same time will cause only one note to be generated because all but one key switch is ignored. A polyphonic generator is a musical instrument that can generate multiple sounds in response to actuation of a corresponding key switch.

A digital tone generator having a stored waveform consisting of a set of data points defining one period of a tone waveform is implemented as a double music instrument by having independent memory means associated with each of the plurality of tone generators. be able to.
These tone generators are assigned corresponding to the activated key switches. This type of instrument is a "double tone synthesizer"
U.S. Pat. No. 4,085,644 (JP-A-52-276).
No. 21).

A single waveform memory can be shared by several tone generators, and systems utilizing a single waveform memory in a time-division or multiplexed manner are known as "methods for addressing memory at a selectively controlled rate." US Patent No. 3,74, entitled "
3,755. A calculator is used to continuously calculate a set of values, each defining a different interval between addresses in the waveform memory. The calculated values each increase periodically by their own value, the individual result of which identifies the address to the waveform memory. These numbers are then used to address the memory and obtain waveform sample points corresponding to each of the several tone generators.

[Problems to be solved by the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiple tone generator in which a large number of tone generators share waveform data stored in one tone register. This double tone generator is incorporated in a tone generator of the type that synthesizes a musical tone waveform by performing a discrete Fourier transform algorithm. A tone generation system of this type is described in detail in U.S. Pat. No. 4,085,644, entitled "Dual Tone Synthesizer." In the following description, all elements of the system described in the above patent are identified by two digit numbers, which correspond to the same numbered elements appearing in the above patent. The system element block identified by a three digit number may correspond to a system element added to the composite synthesizer, or a combination of several elements appearing in the above patents.

In a double tone synthesizer of the kind described in U.S. Pat.No. 4,085,644, the calculation cycle and the data transfer cycle are repeatedly and independently performed,
Data is provided that is converted to a musical instrument waveform. The sequence of calculation cycles is performed during each time a main data set is generated. At the end of each calculation cycle, the calculated main data set is stored in a main register.

Each transfer cycle is followed by a transfer cycle during which the stored main data set is transferred to the tone register. The data stored in the tone register is repeatedly read out at a constant speed. In particular, a comparator is used to assign data read from the tone register to each of a number of tone generators in response to the count state of the counter and the accumulated frequency number generated for each tone generator. .

[Means for solving the problem]

Accordingly, the configuration of the present invention is as described below. That is, in an electronic musical instrument for generating a musical tone from a plurality of data words corresponding to the amplitude of a point defining a musical sound waveform, a storage means for storing a data word corresponding to one cycle of the musical sound waveform; Tone tone detecting and assigning means for detecting each tone in response to the tone, and assigning a frequency number corresponding to the tone to each tone-generating channel, and a data word of the storage means for transferring the tone to each tone-generating channel. Reading means for repeatedly reading in accordance with the count state; addition-accumulator means for adding and accumulating frequency numbers assigned to the respective channels for each cycle of the counting of the reading means; and counting the clock signal. And generates a signal corresponding to the number of channels that generate musical tones. Selective transfer means for comparing the accumulated value of each channel of the accumulator means with each other and generating an equivalent signal when they are equal, and transferring the data word read from the storage means to the corresponding channel. It has a configuration as a double tone generating device.

Alternatively, the data word corresponding to one cycle stored in the storage means stores a point-symmetric component data word of a one-cycle waveform of a musical tone waveform, and the selective transfer means outputs the output of the addition-accumulator means. And a complement means for switching and outputting the read data word as it is or as a two's complement according to the numerical value of the addition-accumulator means.

Alternatively, the data word corresponding to one cycle stored in the storage means stores an axially symmetric component data word of a one-period waveform of a musical tone waveform, and the output of the addition-accumulator means of the selection means is provided. And a complement means for switching and outputting as it is or two's complement according to the numerical value of the addition-accumulator means.

〔Example〕

FIG. 1 illustrates one embodiment of the present invention described as a modification and addition to the system described in U.S. Pat. No. 4,085,644. As described in the above patent, this dual tone synthesizer includes a keyboard switch array. This array is contained in a system block labeled keyboard switch 12. When one or more keyboard switches change their state and are activated on the instrument keyboard (into the "on" position), the tone detection and assignment device 14 stores the corresponding tone information for the activated key switch. One tone generator of the set of tone generators 100 is assigned to each activated key switch. A suitable tone detection and assignment device subsystem is described in detail in U.S. Pat. No. 4,022,098 (JP-A-52-44626).

When one or more key switches on the keyboard are activated,
The execution control circuit 16 starts a series of calculation cycles. During each calculation cycle, a main data word of 64 data words is calculated in a manner described below and stored in a main register.
The 64 data words of the main data set are generated using 32 harmonic coefficients stored in harmonic coefficient memories 26 and 27. Selection of a particular combination of harmonic coefficients is controlled by setting tone switches 56 and 57. The tone switch is often called a stop or stop switch.

The 64 data words of the main data set correspond to the amplitudes of 64 equally spaced one-cycle audio waveform waveforms generated by the tone generator 100. As a general rule, the maximum number of harmonics in the audio tone spectrum is only half the number of data points of one complete waveform synchronization. Thus, a main data set containing 64 data words corresponds to up to 32 harmonics.

When each calculation cycle in the series of calculation cycles is completed, a transfer cycle is started, and the main data set in the main register 34 is transferred to the tone register 101 during the transfer cycle. The data words stored in the tone register 101 are sequentially and repeatedly read out in a manner to be described later and assigned to each of a number of tone generators. The data assigned to each tone generator is transferred to a DA converter, which converts the digital data words into analog waveforms. The DA converter is included in a system block labeled acoustic system 11. The tone waveform is converted to audible by an acoustic system consisting of a conventional amplifier and loudspeaker subsystem, also included in a system block labeled acoustic system 11. US Patent 4,085,64
While the actuated key remains depressed on the keyboard, as described in the specification, the generated main data set is continuously replayed during a series of calculation cycles. It would be desirable to be able to calculate, store and load this data into a tone register. This system function is achieved without interrupting the flow of data to the DA converter.

As described in U.S. Pat. No. 4,085,644, harmonic counter 20 is initialized at the beginning of each calculation cycle. Each time the word counter is incremented and returns to its initial state due to its modulo counting, a signal is provided to increment the count state of harmonic counter 20. The word (word) counter 19 is implemented to count modulo 64, this number being the number of data words (words) of the main data set generated and stored in the main register 34. Harmonic counter 20 is implemented to count Mogello 32. This number corresponds to the maximum number of harmonics consistent with the main data set containing 64 words.

At the beginning of each calculation cycle, an adder-accumulator
21 is initially set to zero. Each time the word counter 19 is reset to its initial or minimum count state, the accumulator is reset to zero. Each time the word counter 19 increments, the accumulator adds the current count state of the harmonic counter 20 at Mogello 64 to the sum already contained in the accumulator.

The contents of the accumulator of the adder-accumulator 21 are used by the memory address decoder 23 to address out the trigonometric sine wave function value from the sine wave function table 24. The sine wave function table 24 is implemented as a fixed memory that stores the value of the trigonometric function value sin (2πφ / 64) for 0 ≦ φ <64 at intervals of D. D is a table analysis constant.

Multiplier 28 responds to the address given by memory address decoder 25 to multiply the trigonometric function value read from sine wave function table 24 by the harmonic coefficient value read from harmonic coefficient memories 26 and 27. The memory address decoder 25 gives a memory address corresponding to the count state of the harmonic counter 20. Switches 56 and 57 are selectively activated to determine a set of harmonic coefficients provided to multiplier 28. The product value produced by the multiplier 28 is provided to the adder 33 as one input.

The contents of the main register 34 are initialized to zero values at the start of the calculation cycle. Every time the word counter 19 is incremented, the contents of the main register 34 at the address corresponding to the count state of the word counter 19 are read out, and an adder is used as one input.
Given to 33. The sum of the inputs to adder 33 is stored in main register 34 at a memory location equal to or corresponding to the count state of word counter 19. After the word counter 19 has cycled through 32 complete cycles of 64 counts per cycle, the main register 34 contains the main data set corresponding to the tone selected by the activation of the tone switches 56 and 57.

FIG. 2 shows a block diagram of a logic circuit in which data read from the tone register is assigned to each of a number of tone generators. The block configuration of the logic circuit surrounded by the broken line in FIG.

The tone detection / assignment device 14 detects the state of a key switch on an instrument keyboard. In response to a change in the switch state from an inactive switch state to an activated switch state,
The tone detection / assignment device addresses out the responding frequency number from the frequency number memory 116.

Frequency number memory 116 is an addressable fixed memory containing binary words having the value 2- ^{(MN) / 12} . .., M, where M is equal to the number of key switches on the instrument keyboard. The frequency number indicates the ratio of the fundamental frequencies of the equal-temperament scale.
A detailed description of the frequency numbers is provided here for reference. U.S. Pat. No. 4,114,496, entitled "Tone Frequency Generator for Dual Tone Synthesizer" (JP-A-53-10781)
No. 5).

The frequency number read from the frequency number memory 116 is transmitted to the key switch which has been activated by the tone / detection assignment device 14.
Is stored in the frequency number register 110 at the address corresponding to the musical tone generator assigned by.

Clock 105 provides a timing signal source used to increment the counter state of counter 103. The counter 103 is implemented to count modulo 64, which is equal to the number of words of the main data set transferred to the tone register 101.

The memory address decoder 102 addresses out the main data set word (word) from the tone register 101 in response to the count state of the counter 103. The data read from the tone register 101 is supplied to the gate 106 as an input data source.

The counter 104 is incremented by a reset signal generated by the counter 103 each time the counter 103 is incremented and returns to its minimum count state due to its mogello counting implementation. The counter 104 is implemented to count Mogello K. K is the number of tone generators included in the tone generator 100.

In response to the count state of the counter 104, the counter 104
The frequency number is set to the frequency number register 11 for the register related to the tone generator corresponding to the count state of
Read from 0. At the same time, the address number is read from the frequency register 108 at the address corresponding to the count state of the counter 104. The frequency numbers read from the frequency number register 110 are added by the adder 109 to create a new address number. This new address number is stored in frequency register 108 at the address location associated with the count state of counter 104. The address number is also called an accumulated frequency number.

The combination of the adder 109 and the frequency register 108 functions in the well-known manner of a conventional adder-accumulator used as one element of a fractional period given the generic name fractional fractional period.

Comparator 107 compares the count state of counter 103 with the 6 most significant bits of the current address number or accumulated frequency number read from frequency register 108. If comparator 107 finds an equal condition between the compared values, it generates an equal signal. This comparison is equivalent to examining the number difference between the count state of the counter 103 and the current address number and generating an equivalent signal if the difference is less than a preselected comparison number.

In response to the equivalent signal, the gate 106 transfers the current data value accessed from the tone register 101 to the data latch 111. Each time the counter 104 is incremented, the data value temporarily stored in the data latch 111 is
Is forwarded to The converted analog signal is provided to data selection circuit 113.

The purpose of the data latch 111 is to provide data to the DA converter at equal time intervals for each of the K tone generators. This is necessary because the time at which the comparator 10- generates an equivalent signal is not constant and varies as a function of the address number provided by the frequency register 108.

The data selection circuit 113 transfers the input signal to one of the K sound channels corresponding to the number obtained by subtracting 1 from the count state of the counter 104. The decrement of -1 is used because the data value contained in the data latch 111 corresponds to the sound channel for the count state immediately before the counter 104.

The required clock frequency f of the clock 105 is calculated from the following equation (1).

f = f ₀ HKL (1) where f ₀ = highest fundamental frequency H = maximum number of harmonics L = 2H.

In a typical case, f ₀ = 2093 Hz, K = 7, H = 32,
Therefore, the required clock frequency is f = 30 MHz.

By using the waveform symmetry described in U.S. Pat. No. 4,085,644, mentioned for reference, a reduction in calculation cycle time, transfer time cycle and clock frequency f can be obtained by a factor of two. . Element Z _j of the main data set; j = 1, 2 ......, when 64, for example, occurs at point _{symmetry, Z j = -Z 65-j} (2) Figure 3 is a point symmetry data in the main data set point FIG. 3 shows a configuration diagram of each logic circuit block shown in FIG. 2 in which the frequency of the clock 105 can be reduced to half by using points. Only one half of the main data set is calculated during the calculation period and stored in the main register 34. The main data set is transferred to the tone register 101 during the transfer cycle.

In FIG. 3, the counter 103 is implemented to count as 32 mogello, which is equal to half the number of data points for one complete cycle of the musical tone waveform corresponding to the calculated main data set.

When the decimal value equivalent to the 5 most significant bits of the address number m accessed out of the frequency register 108 is smaller than or equal to 32, the complement circuit 118 does not change the address number and the frequency number register remains unchanged. The data is transferred from 108 to the comparator 107. The address number accessed out from the frequency register 108 is 32
If greater, the complement circuit 118 changes the address number to a complemented address number or a complemented frequency number m-32. The complemented address number is transferred to the comparator 107, and a code signal is generated. Complement circuit 118 includes a comparator that determines whether a complemented address number has occurred.

In response to the sign signal, two's complement circuit 119 performs two's complement operation on the data transferred by gate 106 in response to the equivalent signal generated by comparator 107. U.S. Patent No.
Another alternative described in US Pat. No. 4,085,644 is to generate points in the main data set that have axial symmetry. Axisymmetric means Z _j = Z _65-j (3).

When the axisymmetric point is calculated, the two's complement circuit 119 shown in FIG. 3 is not used, and the data value transferred by the gate 106 remains unchanged.
Sent to

The individual music generators of the system shown in FIG. 2 include a register included in the frequency number register 110 and a sound channel. All tone generators are frequency number memory 116, adder 109, comparator 107, gate 106, data latch 11
1, The common elements of the DA converter 112 and the data selection circuit 113 are shared.

An alternative system of the present invention is shown in FIG.
The purpose of this alternative system is to reduce the frequency of clock 105.

Tone detection and allocation device in response to actuated key switch
14 reads out the frequency number stored in the frequency number memory 116. The accessed frequency number is stored in a set of frequency registers for a similar number of tone generators. Although only two frequency number registers 140 and 141 are explicitly shown in FIG. 4, they symbolically represent a number of similar frequency number registers, one for each horn tone generator. It should be understood that there is.

A main data set containing 32 data points is calculated axisymmetrically during the calculation cycle and stored in the main register.
These 32 data points correspond to one-half period of the selected musical sound waveform.

The counter 103 counts the clock signal generated by the clock 105. Counter 103 is implemented to count modulo 32. Each time the counter 103 is incremented and returns to its minimum count state, a reset signal is generated. In response to the reset signal, each of the set of adder-accumulators 138-139 adds the frequency number contained in its corresponding frequency number register to the sum contained in its accumulator. There is an adder-accumulator associated with each of the frequency number registers.

A set of complement circuits 128-129 will operate on the first 5 bits of the data word contained in the associated adder-accumulator in the manner described above for the system shown in FIG. 3 when the corresponding decimal value exceeds 32. Performs complement operation.

Each of the set of comparators 121-127 generates an equivalent signal when the first five bits output from its associated complement circuit are equal to the current address number provided by memory address decoder 102. In response to the equivalent signal, the OR gate 142 causes the gate 106 to transfer the current data value read from the tone register to the data selection circuit 130.

When any of comparators 121-127 generate an equivalent signal, the data input to data selection circuit 130 is transferred to one of a set of registers 131-133. The selection of one of these registers is determined to correspond to the comparator that generated the equivalent signal. It is noted that the system of the present invention can generate equivalent signals to two or more comparators simultaneously.

The counter 104 counts the clock signal generated by the clock 105. Counter 104 is implemented to count modulo K. Here, K is the number of tone generators. Counter 104 must reach the K count state at the same time required for counter 103 to reach the 32 count state. These count states are in the decimal sequence 1,
.. K, but in practice the counter counts binary sequence states 000 000 000 001,. The counter 104 can be implemented as a non-integer counter using an adder-accumulator that adds a constant K / 32 to itself for each clock timing pulse applied to the clock 105. The integer portion of the count state of counter 104 is used by data selection circuit 134 to direct the output from one of registers 131-133 toward the DA converter.

The selected portion of the count state of the counter 104 is used by the data selection circuit 136 to direct the output signal from the DA converter 135 to the corresponding sound channel of the set of sound channels.

 The frequency of the clock 105 is set to the following value.

f = f ₀ H ² (4) where f ₀ and H are defined in Equation 1. For a typical system value f ₀ = 2093 Hz, H = 32, f = 2.14 MHz. This value of f is well within the frequency limits of current state-of-the-art microelectronics.

Using a main data set calculated using point symmetry is a trivial extension of the system shown in FIG. Third
A variant similar to that shown is the gate 106 and data selector 1
Inserting two's complement circuit means between 30.

FIG. 5 shows the application of the present invention to a general type of tone generation system called a waveform in memory. Such a tone generation system is described in U.S. Pat. No. 3,515,792, incorporated herein by reference. The system blocks shown in FIG. 5 have corresponding block numbers shown in FIG. 1 of the patent mentioned for reference.
The number is increased by 400.

The waveform memory 7424 is used to store a set of data points that define one complete cycle of the selected tone.
The details of the memory access logic 170 are shown in FIG. 2 and its operation is as described above. The rest of the system is the same as that of the patent mentioned for reference.

〔The invention's effect〕

As described above, according to the present invention, the tone waveform can be read from the storage unit storing the tone waveform at a different frequency corresponding to the number of keys depressed without increasing the clock frequency of the system. Therefore, the storage capacity of musical tone waveforms can be reduced, and multiple tones can be generated from one stored musical tone waveform.

[Brief description of the drawings]

FIG. 1 is a block diagram of a double tone generator according to a first embodiment of the present invention. FIG. 2 is a block diagram of a logic circuit for allocating data read from a tone register to each of a number of tone generators. FIG. 3 is another block diagram of the logic circuit block of the tone generator using point symmetric data points. FIG. 4 is an alternative modification of the present invention. FIG. 5 is a variation of the present invention used for waveforms in a memory tone generator. 11: Sound system 12: Instrument keyboard switch 14: Tone detection / assignment device 16: Execution control circuit 19: Word counter 20: Harmonic counter 21, 138, 139: Adder-accumulator 22, 106: Gate 23, 25, 102 …… Memory address decoder 24 …… Sine wave function table 26,27 …… Harmonic coefficient memory 28 …… Multiplier 33,109 …… Adder 34… Main register 56,57… Switch 100… Sound generator 101… ... tone register 103, 104 ... counter 105 ... clock 107, 121, 127 ... comparator 108 ... frequency register 110, 140, 141 ... frequency number register 111 ... data latch 112, 135, 432 ... DA converter 113, 130, 134, 136 ... data selection circuit 114 ... sound Channel No. 1 115… Sound channel No. 2 116… Frequency number memory 118, 128, 129… Complement circuit 119… Two's complement circuit 131… Register No. 1 132… Register No. 2 133… Register No. Three 137 Sound channel No. 3 142 OR gate 170 Memory access circuit 412 Keyboard switch 424 Waveform memory 426 Attack and decay control circuit 428 Summation means

Continuation of the front page (56) References JP-A-57-188095 (JP, A) JP-A-58-65497 (JP, A)

Claims (3)

(57) [Claims] 1. An electronic musical instrument for generating a musical tone from a plurality of data words corresponding to the amplitude of a point defining a musical tone waveform, a storage means for storing a data word corresponding to one cycle of the musical tone waveform, and a plurality of keys. Tone detection allocating means for detecting the tone in response to the operation of the switch, and allocating a frequency number corresponding to the tone to each channel for generating a tone, and data words in the storage means for transferring to each channel for generating a tone. Reading means for repeatedly reading in accordance with the count state of the clock signal; addition-accumulator means for adding and accumulating the frequency numbers assigned to each of the channels for each cycle of the counting of the reading means; and To generate a signal corresponding to the number of channels that generate musical tones. Selective transfer means for comparing the accumulated value for each channel of the arithmetic-accumulator means, generating an equivalent signal when the values are equal, and transferring the data word read from the storage means to the corresponding channel. Characteristic double tone generator. 2. A data word corresponding to one cycle stored in said storage means stores a point-symmetric component data word of a one-period waveform of a musical tone waveform, and said selective transfer means includes said addition-accumulator means. 2. A double tone generating apparatus according to claim 1, further comprising: complement means for switching and outputting the output and read data word as it is or as a two's complement according to the numerical value of said addition-accumulator means. 3. A data word corresponding to one cycle stored in said storage means stores an axially symmetric component data word of a one-period waveform of a musical tone waveform, and said selective transfer means includes said addition-accumulator means. 2. A double tone generating apparatus according to claim 1, further comprising: complement means for switching and outputting the output as it is or as a two's complement according to the numerical value of said addition-accumulator means.