KR100624951B1 - method for forming fine pattern semiconductor device - Google Patents

method for forming fine pattern semiconductor device Download PDF

Info

Publication number
KR100624951B1
KR100624951B1 KR1020000079677A KR20000079677A KR100624951B1 KR 100624951 B1 KR100624951 B1 KR 100624951B1 KR 1020000079677 A KR1020000079677 A KR 1020000079677A KR 20000079677 A KR20000079677 A KR 20000079677A KR 100624951 B1 KR100624951 B1 KR 100624951B1
Authority
KR
South Korea
Prior art keywords
pattern
semiconductor device
forming
fine pattern
fine
Prior art date
Application number
KR1020000079677A
Other languages
Korean (ko)
Other versions
KR20020050519A (en
Inventor
이규성
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020000079677A priority Critical patent/KR100624951B1/en
Publication of KR20020050519A publication Critical patent/KR20020050519A/en
Application granted granted Critical
Publication of KR100624951B1 publication Critical patent/KR100624951B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

본 발명은 패턴의 가장 자리 영역에서 광 근접 효과에 의해 초래되어지는 가장 자리 패턴 열화 및 쓰러짐 현상을 방지하도록 한 반도체 소자의 미세 패턴 형성방법에 관한 것으로서, 노광 되어지는 밀집된 패턴 영역과 비 패턴 영역과의 광 근접 효과에 의한 빛의 세기 차이를 약화시키어 패턴의 사이즈 변화를 최소화하기 위한 반도체 소자의 미세 패턴 형성방법에 있어서, 일정한 간격을 갖고 형성되는 복수개의 메인 패턴의 바깥쪽에 하나의 태그 패턴을 형성하는 것을 특징으로 한다.The present invention relates to a method of forming a fine pattern of a semiconductor device to prevent edge pattern degradation and collapse caused by an optical proximity effect in an edge region of a pattern. In the method of forming a fine pattern of a semiconductor device for minimizing the change in the size of the pattern by weakening the difference in light intensity due to the optical proximity effect of the semiconductor device, one tag pattern is formed on the outside of the plurality of main patterns formed at regular intervals. Characterized in that.

미세 패턴, 태그 패턴Fine pattern, tag pattern

Description

반도체 소자의 미세 패턴 형성방법{method for forming fine pattern semiconductor device}Method for forming fine pattern semiconductor device

도 1은 종래의 반도체 소자의 미세 패턴 형성방법을 나타낸 모식도1 is a schematic diagram showing a method for forming a fine pattern of a conventional semiconductor device

도 2는 본 발명에 의한 반도체 소자의 미세 패턴 형성방법을 나타낸 모식도2 is a schematic diagram showing a method for forming a fine pattern of a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 메인 패턴 22 : 태그 패턴21: main pattern 22: tag pattern

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 패턴(pattern)의 열화 및 쓰러짐 현상을 방지하는데 적당한 반도체 소자의 미세 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a fine pattern of a semiconductor device suitable for preventing the deterioration and collapse of patterns.

최근 64M DRAM급 이상의 0.20㎛ 이하의 미세 패턴(pattern)을 구현하기 위한 노광 공정에서는 패턴의 가장 자리(edge) 영역에서 발생되는 광 회절 현상에 의한 에너지 세기(energy intensity)의 불균형(가장 자리에서의 패턴 영역과 비패턴 영역과 노광 에너지량 불균형)으로 인해서 CD 변화나, 패턴 현상공정에서 DI 린스(rinsing) 과정 중 근접 패턴간의 DI에 의한 표면 장력에 의해 그 현상들이 갈 수록 증폭된다.In the exposure process for realizing a fine pattern of 0.20 μm or less in 64 M DRAM or more, an unbalance of energy intensity due to light diffraction phenomenon occurring in the edge region of the pattern (at the edge) Due to the imbalance between the pattern region, the non-pattern region, and the exposure energy amount, the phenomena are amplified gradually by the CD change or the surface tension by DI between adjacent patterns during the DI rinsing process in the pattern development process.

따라서 지금까지는 미세 패턴의 가장 자리 영역에서의 광 근접 효과(Optical Proximity Effect)에 의한 에너지 세기 변화에 따른 패턴 변형(pattern deformation) 현상을 억제하기 위하여 메인(main) 패턴과 동일한 유형의 더미(dummy) 패턴을 추가 삽입하여 메인 패턴을 보호하는 기술로 사용하였다.Thus, to date, a dummy of the same type as the main pattern is used to suppress the pattern deformation caused by the change in energy intensity due to the optical proximity effect in the edge region of the fine pattern. Additional patterns were used to protect the main pattern.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 미세 패턴 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a fine pattern of a conventional semiconductor device with reference to the accompanying drawings as follows.

도 1은 종래의 반도체 소자의 미세 패턴 형성방법을 나타낸 모식도이다.1 is a schematic diagram showing a method for forming a fine pattern of a conventional semiconductor device.

도 1에서와 같이, 일정한 간격을 갖고 형성되는 복수개의 메인 패턴(11)과, 상기 메인(main) 패턴(11)과 동일한 유형의 더미(dummy) 패턴(12)을 3~4줄 추가 삽입하여 메인 패턴(11)을 광 근접 효과에 의한 에너지 세기 변화에 따른 패턴 변형을 방지하고 있다.As shown in FIG. 1, a plurality of main patterns 11 formed at regular intervals and a dummy pattern 12 of the same type as the main pattern 11 are additionally inserted into three to four lines. The main pattern 11 is prevented from pattern deformation due to the change in energy intensity due to the optical proximity effect.

즉, 종래는 노광 되어지는 밀집된 패턴 영역과 비 패턴 영역과의 광 근접 효과에 의한 빛의 세기 차이를 약화시키어 사이즈 변화를 최소화하기 위해 복수개의 메인 패턴(11)에 3~4줄의 더미 패턴(12)을 삽입하여 에너지 세기 변화에 따른 패턴의 변형을 방지하고 있다.That is, in the related art, in order to minimize the size change by minimizing the light intensity difference due to the light proximity effect between the dense pattern area and the non-pattern area to be exposed, a plurality of three to four dummy patterns (3 to 4 lines) are formed on the main patterns 11. 12) is inserted to prevent the deformation of the pattern due to the change in energy intensity.

그러나 상기와 같은 종래의 반도체 소자의 미세 패턴 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming a fine pattern of a semiconductor device has the following problems.

첫째, 광학 기술에서 점차 한계 해상력으로 접근해 갈수록 단순히 더미 패턴 삽입만으로는 그 개선효과에는 한계가 있으며 더구나 사이즈(size)가 작아질수록 이러한 현상은 더욱 심해지고 있다.First, as the optical technology gradually approaches the limit resolution, the improvement effect is merely limited by the insertion of a dummy pattern. Furthermore, as the size becomes smaller, the phenomenon becomes more severe.

둘째, 노광부와 비노광부의 감광액이 분리되어 패턴이 형성되는 현상 공정에서 DI 린스시 서로 근접하는 패턴간의 DI의 표면 장력 차이로 인하여 패턴 쓰러짐 현상이 나타날 수 있다.Second, in the development process in which the photoresist of the exposed portion and the non-exposed portion is separated to form a pattern, a pattern collapse phenomenon may occur due to the difference in the surface tension of the DI between patterns that are close to each other during DI rinse.

결국 더미 패턴조차 제 역할을 하지 못하고 변성되거나 붕괴되면 결국 반도체 소자 특성을 저해하는 심각한 결함으로 작용할 수 있다. As a result, even a dummy pattern may be deformed or collapsed and may act as a serious defect that eventually impairs semiconductor device characteristics.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 패턴의 가장 자리 영역에서 광 근접 효과에 의해 초래되어지는 가장 자리 패턴 열화 및 쓰러짐 현상을 방지하도록 한 반도체 소자의 미세 패턴 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming a fine pattern of a semiconductor device to prevent the edge pattern degradation and collapse phenomenon caused by the optical proximity effect in the edge region of the pattern to solve the conventional problems as described above. Its purpose is to.

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 미세 패턴 형성방법은 노광 되어지는 밀집된 패턴 영역과 비 패턴 영역과의 광 근접 효과에 의한 빛의 세기 차이를 약화시키어 패턴의 사이즈 변화를 최소화하기 위한 반도체 소자의 미세 패턴 형성방법에 있어서, 일정한 간격을 갖고 형성되는 복수개의 메인 패턴의 바깥쪽에 하나의 태그 패턴을 형성하는 것을 특징으로 한다.The method of forming a fine pattern of a semiconductor device according to the present invention for achieving the above object is to minimize the change in the size of the pattern by weakening the difference in light intensity due to the light proximity effect between the dense pattern area and the non-pattern area to be exposed In the method for forming a fine pattern of a semiconductor device, it is characterized in that one tag pattern is formed on the outside of the plurality of main patterns formed at regular intervals.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 미세 패턴 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 의한 반도체 소자의 미세 패턴 형성방법을 나타낸 모식도 이다.2 is a schematic diagram showing a method for forming a fine pattern of a semiconductor device according to the present invention.

도 2에서와 같이, 일정한 격을 갖고 형성되는 복수개의 메인 패턴( )과, 상기 복수개의 메인 패턴(21)의 바깥쪽 방향으로 일정 간격을 갖도록 태그(tag) 패턴(22)을 형성하고 있다.As shown in FIG. 2, a plurality of main patterns () formed at regular intervals and a tag pattern 22 are formed to have a predetermined interval in the outward direction of the plurality of main patterns 21.

여기서 상기 태그 패턴(22)은 일반적인 패턴 라인의 일측에 도근-본(dog-bone) 형태로 갖는 패턴 즉, 요철(凹凸) 형태의 패턴을 말한다.Here, the tag pattern 22 refers to a pattern having a dog-bone shape on one side of a general pattern line, that is, a pattern of irregularities.

따라서 본 발명은 노광 되어지는 밀집된 패턴 영역과 비 패턴 영역과의 광 근접 효과(OPE)에 의한 빛의 세기 차이를 약화시키어 사이즈 변화를 최소화하기 위해 복수개의 메인 패턴(21)의 바깥쪽에 하나의 태그 패턴(22)을 형성함으로서 패턴의 쓰러짐이나 변형을 방지할 수 있다.Accordingly, the present invention reduces the intensity of light due to the optical proximity effect (OPE) between the dense pattern region and the non-patterned region to be exposed, and thus, a single tag outside the main pattern 21 to minimize size change. By forming the pattern 22, the fall or deformation of the pattern can be prevented.

여기서 상기 광 근접 효과란 노광 공정시 서로 이웃하는 근접 패턴간에 입사광의 회절 현상에 의해 빛의 광량 분포가 달라지는 것으로, 주로 밀집된 패턴 영역과 비 패턴 영역과의 경계 지역에서 패턴 의존성을 갖는 빛 세기의 차이로 그 현상은 두드러져 패턴의 사이즈 변화 및 변성 등을 초래한다. Here, the optical proximity effect means that the light quantity distribution of the light is changed by the diffraction phenomenon of the incident light between adjacent adjacent patterns in the exposure process, and the difference in the light intensity having the pattern dependency in the boundary region between the dense pattern region and the non-pattern region is mainly. Log phenomena stand out, resulting in pattern size change and denaturation.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 미세 패턴 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a fine pattern of a semiconductor device according to the present invention has the following effects.

즉, 메인 패턴의 바깥쪽에 덧붙여진 태그 패턴에 의해 CD 감소를 보상하고 패턴 린스 공정에서 발생되는 쓰러짐 현상을 방지하며, 종래의 3~4줄의 더미 패턴을 한 줄로 줄임으로서 전체 칩 사이즈를 줄일 수 있다.In other words, the tag pattern attached to the outer side of the main pattern compensates for the CD reduction and prevents the collapse caused in the pattern rinse process, and reduces the overall chip size by reducing the conventional three to four dummy patterns in one line. .

Claims (1)

노광 되어지는 밀집된 패턴 영역과 비 패턴 영역과의 광 근접 효과에 의한 빛의 세기 차이를 약화시키어 패턴의 사이즈 변화를 최소화하기 위한 반도체 소자의 미세 패턴 형성방법에 있어서,In the method of forming a fine pattern of a semiconductor device to minimize the change in size of the pattern by reducing the light intensity difference due to the light proximity effect between the dense pattern region and the non-pattern region to be exposed, 일정한 간격을 갖고 형성되는 복수개의 메인 패턴의 바깥쪽에 하나의 태그 패턴을 형성하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성방법.The method of forming a fine pattern of a semiconductor device, characterized in that to form one tag pattern on the outside of the plurality of main patterns formed at regular intervals.
KR1020000079677A 2000-12-21 2000-12-21 method for forming fine pattern semiconductor device KR100624951B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000079677A KR100624951B1 (en) 2000-12-21 2000-12-21 method for forming fine pattern semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000079677A KR100624951B1 (en) 2000-12-21 2000-12-21 method for forming fine pattern semiconductor device

Publications (2)

Publication Number Publication Date
KR20020050519A KR20020050519A (en) 2002-06-27
KR100624951B1 true KR100624951B1 (en) 2006-09-14

Family

ID=27684194

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000079677A KR100624951B1 (en) 2000-12-21 2000-12-21 method for forming fine pattern semiconductor device

Country Status (1)

Country Link
KR (1) KR100624951B1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980050146A (en) * 1996-12-20 1998-09-15 김영환 Method of forming fine pattern of semiconductor device
KR0172561B1 (en) * 1995-06-23 1999-03-30 김주용 Method of suppressing the proximity effect of exposure mask
JPH11111951A (en) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JPH11186344A (en) * 1997-12-19 1999-07-09 Mitsui Mining & Smelting Co Ltd Improvement of dummy pattern in device holes
KR19990074690A (en) * 1998-03-13 1999-10-05 윤종용 Manufacturing Method of Liquid Crystal Display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0172561B1 (en) * 1995-06-23 1999-03-30 김주용 Method of suppressing the proximity effect of exposure mask
KR19980050146A (en) * 1996-12-20 1998-09-15 김영환 Method of forming fine pattern of semiconductor device
JPH11111951A (en) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JPH11186344A (en) * 1997-12-19 1999-07-09 Mitsui Mining & Smelting Co Ltd Improvement of dummy pattern in device holes
KR19990074690A (en) * 1998-03-13 1999-10-05 윤종용 Manufacturing Method of Liquid Crystal Display

Also Published As

Publication number Publication date
KR20020050519A (en) 2002-06-27

Similar Documents

Publication Publication Date Title
KR100309301B1 (en) Light exposure pattern mask and production method of the same
KR100624951B1 (en) method for forming fine pattern semiconductor device
US6977715B2 (en) Method for optimizing NILS of exposed lines
KR100495920B1 (en) Alignment mark for alignment of wafer of semiconductor device
KR0175679B1 (en) Mask having pattern for detecting unequal illuminance
US5366847A (en) Method and apparatus for optimizing semiconductor exposure process
US5675418A (en) Pattern alignment mark of semiconductor device
KR100480618B1 (en) Semiconductor memory device having improved redundancy scheme
KR100303799B1 (en) Mask pattern for semiconductor device
KR19980050146A (en) Method of forming fine pattern of semiconductor device
KR100424391B1 (en) Method for measuring align in a semiconductor fabrication process
JP3057767B2 (en) Method for manufacturing semiconductor integrated circuit device
KR20030085946A (en) Photo Mask having static electricity check module
KR100643483B1 (en) Semiconductor device fabricating method for use in minute pattern formation
KR101084632B1 (en) Semiconductor devices
KR100244453B1 (en) Sturcture of focus pattern of semiconductor wafer
US6797635B2 (en) Fabrication method for lines of semiconductor device
KR100760916B1 (en) Manufacturing method of reticle in semiconductor device
KR20000067353A (en) Mask layout for forming bank
KR100732757B1 (en) Mask for forming isolated pattern and method of forming the isolated pattern using the same
JPH10171095A (en) Mask for exposure, and production of semiconductor device
KR100687868B1 (en) Method for compensation boundary of the hole pattern array
US6717685B1 (en) In situ proximity gap monitor for lithography
KR19980082700A (en) Metal Film Etching Method of Semiconductor Device
KR20030047387A (en) Method for formming pattern of semiconductor device and semiconductor device thereby

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100825

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee