KR100624921B1 - Structure of memory cell array in nonvolatile memory device - Google Patents

Abstract

The present invention relates to a memory cell array structure of a nonvolatile memory device (NVM). The present invention relates to a drain contact portion for connecting a bit line including first and second lines and a drain region of a memory cell. The memory cell array structure is formed by protruding in a staggered direction, connecting any one of the first line and the drain contact part, and connecting any one of the second line and the drain contact part. Therefore, in the present invention, the drain disturbance characteristic generated by the bias voltage applied during the program and read operations of the memory cell can be reduced to 1/2.

Nonvolatile Memory, Split-Gate Flash Memory, Memory Cell Array, Drain Disturbance

Description

STRUCTURE OF MEMORY CELL ARRAY IN NONVOLATILE MEMORY DEVICE

1 is a plan view illustrating a memory cell array of a general split gate type flash memory device of the present invention.

FIG. 2 is an enlarged plan view of the memory cell illustrated in FIG. 1.

3 is a circuit diagram corresponding to the memory cell array shown in FIG. 1.

FIG. 4 illustrates a Vt shift of threshold voltages of adjacent memory cells sharing a bit line according to a stress time of a bias voltage during a program operation of a memory cell having the memory cell array structure illustrated in FIG. 1. One drain disturb characteristic.

5 is a plan view illustrating a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention.

FIG. 6 is an enlarged plan view of the memory cell illustrated in FIG. 5.

FIG. 7 is a plan view illustrating a memory cell array of an electrically erasable programmable read-only memory (EEPROM) device having a select transistor at a drain terminal according to another exemplary embodiment of the present invention.

FIG. 8 is an enlarged plan view of the memory cell illustrated in FIG. 7.

<Explanation of symbols for main parts of drawing>

MC, MC0 to MC3: memory cells

BL0 to BL3: bit line

WL0 to WL3: word line

MCS: Memory Common Source Line

11, 111a, 111b: drain contact portion

12, 112: active area

13, 113: floating gate

14, 114 source region

15, 115: drain region

16, 116: control gate

117: select transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell array structure of a nonvolatile memory device, and more particularly to a memory cell of a nonvolatile memory device capable of reducing drain disturbance characteristics during program and read operations of the memory cell. It relates to an array structure.

Recently, non-volatile memory devices (NVMs), such as flash, which can be electrically programmed and erased and do not require a refresh function to rewrite the data at regular intervals. The demand for a memory device (FLASH memory device) is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the term 'program' refers to an operation of writing data into a memory cell, and the term 'erase' refers to an operation of removing data written into the memory cell.

The programming and erasing operations of the flash memory device control the threshold voltage (Vt) of the memory cell by injecting electrons into the floating gate or emitting electrons injected into the floating gate through an electrical method. By doing so. However, high bias voltages are applied to the memory cells during program and erase operations. When a high bias voltage is applied to program the memory cell as described above, adjacent cells connected to the memory cell are affected by the bias voltage, thereby writing unnecessary memory cells (that is, cells that should not be programmed). The operation is made. This property is called disturbance property.

Hereinafter, the disturbance characteristic generated in the flash memory device will be described with reference to FIGS. 1 to 3. For convenience of description, a memory cell array of a typical split gate type flash memory device will be described as an example.

1 to 3, a memory cell array of a typical split gate type flash memory device includes a plurality of word lines WL0 to WL3 and bit lines BL0 to BL3, and word lines WLO to WL3 that cross each other. ) And the bit lines BL0 to BL3 are formed of memory cells MC formed at points where they cross each other. The word lines WL0 to WL3 are connected to the control gate 16 of the memory cell MC, and the bit lines BL0 to BL3 are each drain region of the memory cell MC through the contact part 11. It is connected with (15). Each source region 14 of the memory cell MC is electrically connected to a source region of an adjacent memory cell through a memory common source line (MCS).

In the memory cell array of the typical split gate type flash memory device, each control gate 15 of the plurality of memory cells MC shares one word line WL0 while each drain region 15 has one The bit line BL0 is shared. Accordingly, in the program operation, as shown in Table 1 below, the bit line is independent of the selected cell (hereinafter referred to as 'selected cell') and the unselected cell (hereinafter referred to as 'unselected cell'). Commonly applied to all the cells sharing the BL0 and the word line WL0.

Selected memory cell Unselected memory cells BL0 BL1 WL1 WL2 MCS BLO BL1 WL1 WL2 MCS 5 V 0 V -19V 0 V OV 5 V 0 V -9V 0 V 0 V

Therefore, not only the selected cells but also the threshold voltages of the unselected cells are caused to be changed. The characteristic of changing the threshold voltage of the non-selected cell in addition to the selected cell is called a disturbance characteristic. Among these, the disturbance characteristic generated in the unselected cell which shares the bit line BL0 with the selection cell in common is called a drain disturbance characteristic. The drain disturbance characteristic is a characteristic that appears during both the program operation and the read operation, and is largely generated when the bias voltage applied to the bit line BL0 is greater than or equal to a predetermined level during the program operation and the read operation.

As an example, a change in drain disturbance characteristics in a memory cell having a gate oxide thickness of 94 GPa is shown in FIG. 4. 4 is a graph illustrating a Vt shift of a memory cell with respect to a stress time. Here, the stress time is the time for applying the bias voltage. As shown in FIG. 4, when the bias voltage applied to the bit line BL0 is 7V or more, it can be seen that the threshold voltage of the memory cell is greatly changed as the stress time increases. In other words, it can be seen that the drain disturbance characteristic acts as much.

In addition to the drain disturbance characteristic, a disturbance characteristic may occur in the gate electrode sharing the word line WL1. It is known that the drain disturbance characteristic has a greater effect on the device characteristics than the gate disturbance characteristic. Meanwhile, '12', which is not described above, is an active region, and is a region in which the drain region 15 and the source region 14 are formed.

Accordingly, an object of the present invention is to provide a memory cell array structure of a nonvolatile memory device capable of reducing drain disturbance characteristics during a program and read operation of a memory cell.

According to an aspect of the present invention for achieving the above object, a plurality of word lines extending in parallel with each other, and the first and the first to cross in a direction perpendicular to the plurality of word lines, and to extend in parallel with each other And a plurality of bit lines formed of two lines, and a memory cell formed at a portion where the word line and the bit line cross each other, wherein the first and second lines are connected to a drain region of the memory cell, respectively, A memory cell array structure of a nonvolatile memory device having a structure in which adjacent ones formed in a line direction are connected to any one of a drain contact portion having a shape protruding in different directions is provided.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

FIG. 5 is a plan view illustrating a memory cell array structure of a nonvolatile memory device according to an exemplary embodiment of the present invention, and FIG. 6 is a plan view illustrating the memory cell of FIG. 5. For convenience of description, the memory cell array of the flash memory device is illustrated.

5 and 6, a memory cell array structure of a nonvolatile memory device according to an exemplary embodiment of the present invention includes a plurality of word lines WL0 to WL3 formed in parallel with each other, and a plurality of word lines WL0. To a plurality of bit lines BL0 to BL3 formed of two lines BL0a and BL0b, BL1a and BL1b, BL2a and BL2b, BL3a and BL3b, which cross each other in a direction perpendicular to the WL3 and extend in parallel with each other. do.

The bit lines BL0 to BL3, each of which consists of two electrically independent lines BL0a and BL0b, BL1a and BL1b, BL2a and BL2b, BL3a and BL3b. For example, the first and second lines BL0a and BLOb of the bit line BL0 extend in parallel with each other, and each of the two word lines WL1 and WL2 protrudes in different directions (ie It is electrically connected to the drain region 115 of the memory cell MC through the drain contact portions 111a and 111b having a zigzag shape. For example, as illustrated in FIG. 5, the first line BL0a is connected through the drain region 115 and the drain contact portion 111a of the memory cell MC2 selected by the word line WL2. The two lines BL0b are connected through the drain region 115 and the drain contact portion 111b of the memory cell MC1 selected by the word line WL1.

The program, erase and read operations of a memory cell of a flash memory device according to a preferred embodiment of the present invention having such a structure proceed in the same manner as the operation of the prior art.

For example, when a program operation is to be performed on the memory cell MC0 to which the word line WL0 and a control gate (not shown) are connected, −9 V is applied to the word line WL0 and the second line BL0b is applied. Apply 5V to. Then, 0V is applied to the memory common source line MCS. In this case, the memory cell MC1 connected to the second line BL0b may be supplied with a program bias voltage to generate drain disturbance characteristics, but is not electrically connected to the second line BL0b and may be electrically connected to the first line BL0a. The memory cells MC2 and MC3 connected to are not applied with the program bias voltage, so that the drain disturbance characteristic does not occur. That is, the generation of drain disturbance characteristics can be reduced to about 1/2 of the conventional structure.

The memory cell array structure of the nonvolatile memory device according to the preferred embodiment of the present invention having such a structure has almost no area increase compared to the memory cell array structure of the general flash memory device shown in FIG. 1. As shown in FIG. 5, the memory cell array structure of the nonvolatile memory device according to the preferred embodiment of the present invention is the active region 12 in which the drain contact portion 11 is formed in the memory cell array structure of a general flash memory device. This is because it is formed by moving in the right or left direction. That is, in the memory cell array structure of the general flash memory device, although the active region 12 of the portion where the drain contact portion 11 is formed is formed in a cross shape (“+”), a nonvolatile memory according to a preferred embodiment of the present invention. In the memory cell array structure of the device, the active region 112 is formed in a 'ㅏ' shape. Accordingly, when the left protrusion of the active area 12 having the cross shape is moved to the right side in the memory cell array structure of the general flash memory device, the memory cell array structure of the nonvolatile memory device according to the preferred embodiment of the present invention is obtained.

Meanwhile, the memory cell array structure of the nonvolatile memory device according to the preferred embodiment of the present invention is not limited to a split gate type flash memory device, but is applicable to all semiconductor devices in which drain disturbance characteristics are generated by a bias voltage. It is possible. For example, the present invention can also be applied to an EEPROM device having an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EEPROM Tunneling Oxide (ETOX) device, and a select transistor at a drain (or source).

As an example, a memory cell array structure of an EEPROM device having a select transistor at a drain end will be described with reference to FIGS. 7 and 8. The memory cell array structure of the EEPROM device has a structure substantially the same as that of the split gate type flash memory device shown in FIG. 5, except that a source region (or drain) connected to the memory common source line MCS is provided. The select transistor 117 extended in the direction parallel to the word line directions WL0 to WL3 is formed in the region). Other configurations than the select transistor 117 are the same as the memory cell array structure of the split gate type flash memory device.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. Particularly, in the preferred embodiment of the present invention, only the memory cell array structure of the nonvolatile memory device having the memory common source (MCS) structure has been described, but this is a memory having a self aligned source (SAS) structure as an example. It is also applicable to a cell array structure. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the drain contact portion for connecting the bit line consisting of the first and second lines and the drain region of the memory cell is formed to protrude in a direction crossing each other, and the first line and the drain A drain disturbance characteristic generated by a bias voltage applied during program and read operations of a memory cell by connecting one of the contact parts and connecting one of the second line and the drain contact part to form a memory cell array structure. Can be reduced to 1/2.

In addition, according to the present invention, by slightly changing the position where the drain contact portion and the metal line are formed, the drain due to the bias voltage applied during the program and read operations of the memory cell without modification of the conventional memory cell shape. The disturbing properties can be reduced.

In addition, according to the present invention, by simply adjusting the region where the drain contact portion is formed without increasing the area of the memory cell array of the conventional nonvolatile memory device, drain disturbance characteristics due to bias voltage applied during program and read operations of the memory cell are reduced. You can.

Claims (4)

A plurality of word lines extending in parallel with each other; A plurality of bit lines formed in a direction perpendicular to the plurality of word lines and extending in parallel with each other; And Including a plurality of memory cells formed at the intersection of the word line and the bit line, And each of the first and second lines is connected to drain regions of memory cells adjacent to each other and connected to respective drain contact portions disposed in different directions. The method of claim 1, And the drain contact unit is formed for every two word lines of the plurality of word lines. The method of claim 1, And a source region of the memory cell are connected to each other through a memory common source line or to each other in a self-aligned source structure. The method of claim 1, And the memory cell comprises a select transistor.

Images