KR100619162B1 - Low consumption power operating system of lcd module - Google Patents

Abstract

The present invention relates to a low power consumption driving apparatus of a liquid crystal display module for reducing power consumption by preventing a large current from flowing during gate-on of a thin film transistor for driving a liquid crystal display module.

According to a preferred embodiment of the present invention, in the driving device of a liquid crystal display module configured to drive a liquid crystal cell in pixel units by applying a gate voltage to a gate of a thin film transistor arranged in a matrix array form, gate on driving of the thin film transistor is performed. First and second switching elements complementary to each other so that a B voltage of 1-H period is commonly applied to each gate, and a first reference voltage generator for applying a first reference voltage to a source of the first switching element, And a second reference voltage generator for forming a clamping level for the potential of the connection node of the first and second switching elements, so as to generate the gate-source voltage of the thin film transistor in a step waveform.

Description

LOW CONSUMPTION POWER OPERATING SYSTEM OF LCD MODULE}

1 is a schematic diagram for explaining a driving method of a conventional liquid crystal display module;

2A to 2C are waveform diagrams for explaining a driving method of the conventional liquid crystal display module shown in FIG. 1;

3 is a view showing the configuration of a low power consumption driving device of a liquid crystal display module according to an embodiment of the present invention;

4A is a circuit diagram illustrating an example of a configuration of a first reference voltage generator shown in FIG. 3;

4B is a circuit diagram showing an example of the configuration of a second reference voltage generator shown in FIG. 3;

FIG. 5 is a waveform diagram illustrating an operation of a low power consumption driving device of a liquid crystal display module according to the present invention shown in FIG. 3.

6 is a waveform diagram illustrating another application example of the present invention.

<Description of the symbols for the main parts of the drawings>

10: thin film transistor (TFT), 20a, 20b: first and second switching elements,

22: the first reference voltage generator, 24: the second reference voltage generator,

224: inverting amplifier.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption driving device for a liquid crystal display module, and more particularly, to reduce power consumption when a large area and high resolution screen is reproduced by adopting a TFT-LCM. A low power consumption driving device of a liquid crystal display module for enabling this.

Currently, a liquid crystal display device, which is noted as a display device for screen reproduction, generally includes a liquid crystal panel in which a liquid crystal is injected between two upper glass substrates and a lower glass substrate, and a driver LSI for driving the liquid crystal panel. It consists of a drive unit having a PCB with integrated circuit elements and a chassis structure including a backlight.

Herein, a thin film transistor formed in the form of a matrix array used to drive a liquid crystal panel serves as a switching element for driving a liquid crystal cell in pixel units. The TFT includes a gate, a source, and a drain. It has a switching function for applying a signal voltage to the pixel electrode.

That is, in order to drive a TFT-LCD having an active matrix structure, a gate voltage must be applied to a TFT gate of a low line, and a data voltage must be applied to a source and a drain of the TFT, and a common electrode formed on the upper glass substrate. The data voltage is alternately applied to the (Com electrode) at a +/- level based on the Vcom voltage.

In order to apply the data voltage to the liquid crystal cell, a channel must be formed in the TFT, and the channel depends on the Vgs level formed between the gate electrode and the source electrode of the corresponding TFT.

In this case, as a high voltage is momentarily applied to the gate of the TFT, a large charging current flows between the gate and the source electrode under the influence of the parasitic capacitance Cgs, resulting in increased power consumption and distortion of the gate voltage. do.

That is, according to the driving method of the conventional liquid crystal display module illustrated in FIG. 1, when the Vgs level is applied to form a channel between the gate and the source of the TFT 10 to which the liquid crystal cell CE is connected to one side ( 2a), a large voltage is instantaneously applied to the gate, resulting in an influence of parasitic capacitance Cgs between the gate and the source, resulting in a large charge current (i = Cgs * dVgs / dt; see FIG. 2b). As it flows, power consumption increases (that is, P = V * i = Vgs * Cgs * dVgs / dt), while distortion in the gate voltage (see “A” in FIG. 2C) occurs. In addition, when the gate voltage is distorted, the charge rate is changed in the liquid crystal cell, and thus the likelihood of generating flicker is considerably increased.

Accordingly, the present invention has been made in view of the above-described state of the art, and forms a step in the voltage applied between the gate electrode and the source electrode of the thin film transistor for driving the liquid crystal display module to prevent rapid current flow. The purpose is to provide a low power consumption driving device of the liquid crystal display module to reduce the power consumption.

In order to achieve the above object, a driving apparatus of a liquid crystal display module according to the present invention includes applying a gate pulse to a gate of a thin film transistor in which a gate driver IC driven by a clock pulse vertical signal is arranged in a matrix array. A first switching element configured to be driven by a liquid crystal cell of the MOS FET, the switching voltage having a pulse waveform of 1-H period being applied to the gate while being synchronized with the clock pulse vertical signal; A second MOS FET having mutually complementary operation characteristics with the first switching element, connected in series with the first switching element, and having a switching voltage applied to the gate in common with the gate of the first switching element; Switching elements; A first reference voltage generator configured to apply a first reference voltage to the first switching element; And a second reference voltage generator configured to apply a second reference voltage to a connection node to which the first and second switching elements are connected in series to form a clamping level. The device performs a complementary operation, thereby generating an output voltage at which the level of the second reference voltage is clamped at the connection node and swinging the first reference voltage in that state, and the gate drive IC generates the clock pulse. The gate pulse may be provided as a step waveform in which the first reference voltage swings with the second reference voltage in synchronization with a vertical signal.
Here, the step waveform is determined and output as the gate pulse is synchronized with a section in which only the second reference voltage is applied to the output voltage at the rising time of the clock pulse vertical signal.
The gate pulse may be output after a step waveform is determined as a period in which only the second reference voltage is applied to the output voltage is synchronized at the time when the clock pulse vertical signal is polled.

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Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

3 shows a configuration of a low power consumption driving device of a liquid crystal display module according to a first embodiment of the present invention.

In the drawing, reference numerals 20a and 20b denote first and second switching elements composed of, for example, MOS FETs, which are complementary to each other, and reference numeral 22 denotes applying a first reference voltage V1 to the first switching element 20a. And a second reference voltage generator for applying a second reference voltage V2 for forming a clamping potential with respect to the voltage appearing at the connection node of the first and second switching elements 20a and 20b. Reference voltage generator.

More specifically, a switching voltage B is commonly applied to the gate of the first switching element 20a and the active low level gate of the second switching element 20b, and the source of the first switching element 20a is It is connected to the first reference voltage generator 22, and the drain of the second switching element 20b is connected to the ground potential.

The second reference voltage generator 24 is connected to the connection nodes of the first and second switching devices 20a and 20b via a capacitor 26 to obtain an output voltage Von.

Referring to FIG. 4A, the first reference voltage generator 22 receives an externally applied Vin1 voltage to the inverting terminal (−) through the resistor 220, and the non-inverting terminal (+) has a ground potential. And an inverting amplifier 224 connected between the inverting terminal (-) and the output terminal thereof, and configured to obtain the first reference voltage V1 at its output side.

In addition, referring to FIG. 4B, the second reference voltage generator 24 is applied to the non-inverting terminal (+) with the external Vin2 voltage divided by the resistors 230 and 232 to convert the second reference voltage. An amplifier 234 is configured to obtain.

The voltage Vin1 applied to the first reference voltage generator 22 is applied in the form of a pulse having a predetermined width T while having a period of 1-H, as shown in FIG. The switching voltage B applied to the gates of the first and second switching elements 20a and 20b is applied in the form shown in FIG.

Accordingly, when the Vin1 voltage is applied to the first reference voltage generator 22 (see FIG. 5A), the second switching device 20b is turned on by the switching voltage B, and the capacitor The output voltage having the level V1 corresponding to the second reference voltage V2 from the second reference voltage generator 24 is applied to both ends (ie, the connection node) of 26, while the switching voltage B is applied. When the first switching device 20a is turned on after the time T1, the level of the output voltage Von applied to both ends of the capacitor 26 (that is, the connection node) becomes V1 + V2 (see FIG. c)).

In this state, when the CPV signal (i.e., the clock pulse vertical signal) shown in Fig. 5D is applied to the gate driver IC (not shown) at time T0, the gate driver IC applies the TFT driving gate pulse Vgs. As shown in (e) of FIG. 5, when outputting in a step waveform and driving the gate electrode of the TFT by the waveform, large current flow is prevented and power consumption is reduced.

Meanwhile, referring to FIG. 6, another application example of the present invention will be described with reference to FIG. 6 (b) when a CPV signal is applied to a gate driver IC in a state where the output voltage Von shown in FIG. As shown in Fig. 6, when the falling edge is provided synchronously at the time T1, the gate driver IC outputs the TFT driving gate pulse Vgs as the step waveform of Fig. 6C, resulting in the line delay of the gate voltage. It is possible to reduce the occurrence of flicker.

As described above, according to the low power consumption driving apparatus and the driving method thereof of the liquid crystal display module according to the present invention, the step of applying the voltage applied to the gate of the TFT by step waveform is applied to prevent the rapid flow of current, thereby Power consumption can be reduced.

The preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, and such modifications and changes belong to the following claims Should be seen.

Claims (3)

In the driving apparatus of the liquid crystal display module in which a liquid crystal cell in pixel units is driven by applying a gate pulse to a gate of a thin film transistor in which a gate driver IC driven by a clock pulse vertical signal is arranged in a matrix array form. A first switching element configured of a MOS FET, to which a switching voltage having a pulse waveform of 1-H period is applied to the gate while being synchronized with the clock pulse vertical signal; A second MOS FET having mutually complementary operation characteristics with the first switching element, connected in series with the first switching element, and having a switching voltage applied to the gate in common with the gate of the first switching element; Switching elements; A first reference voltage generator configured to apply a first reference voltage to the first switching element; And And a second reference voltage generator configured to apply a second reference voltage to a connection node to which the first and second switching elements are connected in series to form a clamping level. The first and second switching elements perform a complementary operation by the switching voltage, and thus an output voltage at which the level of the second reference voltage is clamped at the connection node and the first reference voltage swings in the state. And the gate drive IC provides the gate pulse as a step waveform in which the first reference voltage swings at the second reference voltage in synchronization with the clock pulse vertical signal. Device. The liquid crystal display module of claim 1, wherein the gate pulse is output by determining a step waveform as a section in which only the second reference voltage is applied to the output voltage is synchronized at a rising time of the clock pulse vertical signal. Low power consumption drive. The liquid crystal display module of claim 1, wherein the gate pulse is outputted by determining a step waveform when a section in which only the second reference voltage is applied to the output voltage is synchronized at the time when the clock pulse vertical signal is polled. Low power consumption drive.

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