KR100614490B1 - 집적 회로, 컴퓨팅 시스템 및 재구성가능 컴퓨팅 방법 - Google Patents
집적 회로, 컴퓨팅 시스템 및 재구성가능 컴퓨팅 방법 Download PDFInfo
- Publication number
- KR100614490B1 KR100614490B1 KR1019997012385A KR19997012385A KR100614490B1 KR 100614490 B1 KR100614490 B1 KR 100614490B1 KR 1019997012385 A KR1019997012385 A KR 1019997012385A KR 19997012385 A KR19997012385 A KR 19997012385A KR 100614490 B1 KR100614490 B1 KR 100614490B1
- Authority
- KR
- South Korea
- Prior art keywords
- reconfigurable
- memory
- logic
- data
- data path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Microcomputers (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/884,380 | 1997-06-27 | ||
| US08/884,380 US5970254A (en) | 1997-06-27 | 1997-06-27 | Integrated processor and programmable data path chip for reconfigurable computing |
| US8/884,380 | 1997-06-27 | ||
| PCT/US1998/013565 WO1999000739A1 (en) | 1997-06-27 | 1998-06-29 | An integrated processor and programmable data path chip for reconfigurable computing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010020545A KR20010020545A (ko) | 2001-03-15 |
| KR100614490B1 true KR100614490B1 (ko) | 2006-08-22 |
Family
ID=25384495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019997012385A Expired - Fee Related KR100614490B1 (ko) | 1997-06-27 | 1998-06-29 | 집적 회로, 컴퓨팅 시스템 및 재구성가능 컴퓨팅 방법 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5970254A (enExample) |
| EP (1) | EP1015984A4 (enExample) |
| JP (1) | JP2002511173A (enExample) |
| KR (1) | KR100614490B1 (enExample) |
| AU (1) | AU8177598A (enExample) |
| CA (1) | CA2291789A1 (enExample) |
| WO (1) | WO1999000739A1 (enExample) |
Families Citing this family (226)
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1997
- 1997-06-27 US US08/884,380 patent/US5970254A/en not_active Expired - Lifetime
-
1998
- 1998-06-29 WO PCT/US1998/013565 patent/WO1999000739A1/en not_active Ceased
- 1998-06-29 EP EP98931733A patent/EP1015984A4/en not_active Withdrawn
- 1998-06-29 AU AU81775/98A patent/AU8177598A/en not_active Abandoned
- 1998-06-29 KR KR1019997012385A patent/KR100614490B1/ko not_active Expired - Fee Related
- 1998-06-29 JP JP50587899A patent/JP2002511173A/ja not_active Ceased
- 1998-06-29 CA CA002291789A patent/CA2291789A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP1015984A4 (en) | 2001-11-21 |
| AU8177598A (en) | 1999-01-19 |
| JP2002511173A (ja) | 2002-04-09 |
| CA2291789A1 (en) | 1999-01-07 |
| US5970254A (en) | 1999-10-19 |
| KR20010020545A (ko) | 2001-03-15 |
| EP1015984A1 (en) | 2000-07-05 |
| WO1999000739A1 (en) | 1999-01-07 |
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