KR100613297B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention improves the characteristics and performance of a semiconductor device, comprising: forming a gate insulating film and a gate electrode on a semiconductor substrate, forming a sidewall on the side of the gate insulating film and the gate electrode, and a semiconductor exposed by the gate electrode and the sidewall. Forming a source and a drain region by ion implanting a first conductivity type impurity into the substrate at a high concentration, forming an epitaxial layer on the source region, the drain region and the gate electrode, and removing the sidewalls at a predetermined angle on the semiconductor substrate. Implanting second conductivity type impurity ions to form a diffusion preventing region, and ion implanting the first conductivity type impurity ions at low concentration into a semiconductor substrate at a position corresponding to the region where the sidewalls are removed to form a low concentration doped region, Forming a spacer on a side of the gate insulating film and the gate electrode, and And depositing a silicide forming metal film on the semiconductor substrate and performing heat treatment to form a metal silicide by the reaction of the epi layer and the silicide forming metal film. As such, the epi layer is disposed on the semiconductor substrate and the gate electrode, and the epi layer is changed to the metal silicide, thereby minimizing the reduction of the source and drain regions of the semiconductor substrate by the metal silicide, thereby improving the performance and characteristics of the semiconductor device. It is possible to increase, and to reduce the contact resistance between the metal silicide and the underlying film in contact with each other.

Transistors, Silicides, Epitaxial

Description

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

1 is a diagram of a semiconductor device according to one embodiment of the present invention.

2 to 5 are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in manufacturing steps.

TECHNICAL FIELD This invention relates to the manufacturing method of a semiconductor element. Specifically, It is related with the manufacturing method of the semiconductor element which has a silicide.

In general, a semiconductor device includes a transistor including a gate, a source, and a drain in a device region defined by a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) device isolation method.

A method of manufacturing a transistor of such a semiconductor element will be described.

First, a gate insulating film is formed on a semiconductor substrate on which shallow trench isolation (STI) is formed, and a polysilicon layer is deposited thereon. Here, the STI prevents malfunction between the devices by electrically isolating the devices formed on the semiconductor substrate.

Subsequently, the gate insulating layer and the polysilicon layer are etched to form a gate electrode. At this time, the gate electrode is formed on the semiconductor substrate on which the STI is not formed.

Then, using the ion implantation device on the semiconductor substrate using the gate electrode as a mask, a high concentration of impurity ions are implanted, and annealing is performed to source and drain junctions to active regions of the semiconductor substrate exposed to both sides of the gate electrode. Form an area.

Next, a metal film is laminated on the entire surface of the upper structure of the semiconductor substrate, and then heat-treated at a predetermined temperature to form metal silicide.

Meanwhile, as the semiconductor device is highly integrated, a channel region formed in a region under the gate electrode and positioned between the source region and the drain region may be narrowed. Accordingly, the threshold voltage of the semiconductor device may be drastically reduced and performance may be degraded.

In addition, as the metal silicide reacts with the semiconductor substrate to make it thick, the source and drain junction regions may be reduced, resulting in deterioration of the characteristics of the semiconductor device.

Therefore, the technical problem of this invention is to improve the characteristic and performance of a semiconductor element.

The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of: forming a gate insulating film and a gate electrode on a semiconductor substrate, forming a sidewall on the side surface of the gate insulating film and the gate electrode; Forming a source and a drain region by ion implanting a first conductivity type impurity into the semiconductor substrate at a high concentration, forming an epitaxial layer on the source region, the drain region and the gate electrode, and removing the sidewall. Implanting the second conductivity type impurity ions at a predetermined angle onto the substrate to form a diffusion barrier region, and implanting the first conductivity type impurity ions at low concentration into the semiconductor substrate at a position corresponding to the region where the sidewalls are removed. Forming a doped region, said gate insulating film and said gay Forming a spacer on the electrode side, and a step of laminating metal film for a silicide is formed on the semiconductor substrate and heat-treated to form a metal silicide by said epitaxial layer and said silicide forming metal film for reaction.

The diffusion preventing region may extend to an edge region of the gate electrode and a region under the spacer.

The first conductivity type impurity ions and the second conductivity type impurity ions may have opposite polarities.

When the first conductivity type impurity ions for forming the source region and the drain region are n type impurity ions, ion implantation is performed at an energy of 10 to 100 keV, and in the case of P type impurity ions, ion implantation is performed at an energy of 5 to 50 KeV. have.

When the second conductivity type impurity ion for forming the diffusion barrier region is n type impurity ion, ion implantation may be performed at an energy of 10 to 60 keV, and when P type impurity ion is ion implanted at an energy of 5 to 50 KeV.

The epi layer may be formed to a thickness of 50 ~ 500Å.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a semiconductor device and a method of manufacturing the same will be described in detail with reference to FIGS. 1 to 5.

1 is a diagram of a semiconductor device according to one embodiment of the present invention, and FIGS. 2 to 5 are diagrams illustrating manufacturing steps of a semiconductor device according to one embodiment of the present invention.

First, the structure of a semiconductor device will be described in detail with reference to FIG. 1.

As shown in FIG. 1, the gate insulating film 3 and the gate electrode 4 are sequentially formed on the semiconductor substrate 1 on which the device isolation film 2 is formed, and the gate insulating film 3 and the gate electrode 4 are formed. The spacer 10 is formed at the side surface. Source and drain regions 6a and 6b are formed in the semiconductor substrate 1 exposed in such a structure, and metal silicides 11a and 11b are disposed on the source and drain regions 6a and 6b and the gate electrode 4. , 11c) is formed. The diffusion preventing regions 8a and 8b are formed in the semiconductor substrate 1 in the edge region of the gate electrode 4 and the region below the spacer 10. In addition, the lightly doped regions 9a and 9b are formed in portions of the metal silicides 11a and 11b extending to the lower region of the spacer 10. At this time, impurity ions of different conductivity types are implanted into the source region 6a and the drain region 6b and the diffusion preventing regions 8a and 8b. For example, when n-type impurity ions such as arsenic (As) impurity ions or phosphorus (P) impurity ions are implanted into the source region 6a and the drain region 6b, boron (B) may be used in the diffusion preventing regions 8a and 8b. P-type impurity ions such as impurity ions may be implanted. Also, when p-type impurity ions such as boron impurity ions are implanted into the source and drain regions 6a and 6b, n-type impurity ions such as arsenic impurity ions or phosphorus impurity ions are implanted into the diffusion preventing regions 8a and 8b. Can be.

Next, the manufacturing method of a semiconductor element is demonstrated in detail with reference to FIGS.

As shown in FIG. 2, the gate insulating film 3 and the gate electrode 4 are formed on the semiconductor substrate 1 in which the element isolation film 2 is formed. Subsequently, an oxide film is deposited on the entire upper surface of the semiconductor substrate 1 and etched to form sidewalls 5 formed of oxide films on side surfaces of the gate insulating film 3 and the gate electrode 4. In addition, the source region 6a and the drain region 6b are implanted by implanting impurity ions of the first conductivity type in a region except for the region covered by the gate electrode 4 and the sidewall 5 of the semiconductor substrate 1. Form.

At this time, impurity ions such as arsenic (As) are implanted into the source region 6a and the drain region 6b with an energy of 10 to 100 keV as impurity ions of the first conductivity type to form an n-channel metal oxide semiconductor (NMOS). Alternatively, impurity ions such as boron (B) are implanted into the source region 6a and the drain region 6b with energy of 5 to 50 keV to form a p-channel metal oxide semiconductor (PMOS). You may.

Next, as shown in FIG. 3, epitaxial layers 7a, 7b, and 7d are formed on the exposed semiconductor substrate 1 and the gate electrode 4.

The epitaxial layers 7a and 7b are formed by depositing gaseous semiconductor crystals to grow crystals along the crystal axis of the semiconductor substrate 1. The epitaxial layer 7c also deposits gaseous semiconductor crystals to form the gate electrode 4. It is formed by growing crystals along the crystal axis of. Here, the epi layers 7a, 7b, and 7d may be formed to a thickness of about 50 to 500 kPa.

Next, as shown in FIG. 4, the side wall 5 is completely removed by an etching process. Subsequently, a second conductive type impurity ions are implanted on the semiconductor substrate 1 at a predetermined angle using a photo mask (not shown) to form halo, that is, diffusion preventing regions 8a and 8b. At this time, the implantation angle of the second conductivity type impurity ion is preferably about 30 to 60 kPa. The diffusion preventing regions 8a and 8b by the second conductivity type impurity ion implantation are formed in the region where the sidewall 5 is located and the semiconductor substrate 1 under the gate electrode 4.

In this case, when the second conductivity type impurity is an impurity having a polarity opposite to that of the first conductivity type impurity, p-type impurity ions such as boron (B) are injected into the diffusion preventing regions 8a and 8b as the second conductivity type impurity. When the ion implantation energy is 5 to 50 keV, and the n-type impurity ions such as arsenic (As) are implanted into the diffusion barrier regions 8a and 8b as the second conductivity type impurities, the ion implantation energy is 10 to 60 keV. desirable.

Then, as shown in FIG. 5, low concentration doped regions 9a and 9b are formed by implanting impurity ions of the first conductivity type onto the semiconductor substrate 1 using a photomask at low concentration. At this time, when implanting n-type impurity ions such as arsenic (As) into the low concentration doped regions 9a and 9b as impurities of the first conductivity type, the ion implantation energy is 10 to 100 keV, and the low concentration doped regions 9a and 9b. In the case of implanting P-type impurity ions such as boron (B) as the first conductivity type impurity), the ion implantation energy is preferably 5 to 30 keV.

Meanwhile, as described above, impurity ions different from the source and drain regions 6a and 6b and the lightly doped regions 9a and 9b are implanted into the diffusion barrier regions 8a and 8b to the region under the gate electrode 4. The diffusion of impurity ions in the source and drain regions 6a and 6b and the lightly doped regions 9a and 9b can be prevented. As a result, the performance of the semiconductor device may be improved.

Next, as shown in FIG. 1, spacers 10 are formed on the side surfaces of the gate insulating film 3 and the gate electrode 4, and a silicide forming metal film is stacked on the entire upper structure of the semiconductor substrate 1, and then, The metal silicides 11a, 11b, and 11c are formed by heat treatment at a temperature of. Here, the metal film may be made of a low resistance metal such as titanium, cobalt, molybdenum, tungsten, or the like.

The metal silicides 11a, 11b, and 11c are silicon compounds, which are formed on the source region 6a and drain region 6b and on the gate electrode 4 by reacting with the epi layers 7a, 7b, and 7c by a heat treatment process. . In this case, the metal silicides 11a, 11b, and 11c do not react with the impurity ions or silicon in the source or drain regions 6a and 6b. Accordingly, it is possible to prevent the source or drain regions 6a and 6b from being damaged to increase the contact resistance between the metal silicides 11a, 11b and 11c and the source or drain regions 6a and 6b. In addition, since the thickness of the metal silicides 11a, 11b, and 11c can be formed thick, the resistance of the metal silicides 11a, 11b, and 11c can also be reduced.

According to the present invention, the epi layer is disposed on the semiconductor substrate and the gate electrode, and the epi layer is changed to the metal silicide, thereby minimizing the reduction of the source and drain regions of the semiconductor substrate by the metal silicide, thereby reducing the performance and characteristics of the semiconductor device. Can be increased.

In addition, the contact resistance between the metal silicide and the lower layer in contact with each other can be reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (6)

Forming a gate insulating film and a gate electrode on the semiconductor substrate, Forming sidewalls on the gate insulating layer and the side of the gate electrode; Forming a source and a drain region by ion implanting a first conductive impurity at a high concentration into the semiconductor substrate exposed by the gate electrode and the sidewall; Forming an epitaxial layer on the source region, the drain region and the gate electrode; Removing the sidewall and implanting second conductivity type impurity ions at a predetermined angle on the semiconductor substrate to form a diffusion barrier region; Forming a low concentration doped region by ion implanting the first conductivity type impurity ions at low concentration into a semiconductor substrate at a position corresponding to the region where the sidewalls are removed; Forming spacers on side surfaces of the gate insulating film and the gate electrode, and Stacking and heat treating a silicide forming metal film on the semiconductor substrate to form metal silicide by reaction of the epi layer and the silicide forming metal film Method for manufacturing a semiconductor device comprising a. In claim 1, The diffusion preventing region extends to an edge region of the gate electrode and a region under the spacer. The method of claim 1, And the first conductivity type impurity ion and the second conductivity type impurity ion have opposite polarities to each other. The method of claim 1, A semiconductor implanted with an energy of 10 to 100 keV when the first conductivity type impurity ions for forming the source region and the drain region is an n type impurity ion, and an ion implanted with an energy of 5 to 50 KeV when the P type impurity ion is used. Method of manufacturing the device. The method of claim 1, Fabrication of a semiconductor device in which the second conductivity type impurity ion for forming the diffusion barrier region is ion implanted at an energy of 10 to 60 keV and ion implanted at an energy of 5 to 50 KeV when the P type impurity ion Way. In claim 1, The epi layer is a semiconductor device manufacturing method to form a thickness of 50 ~ 500Å.

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