KR100613049B1 - A boosting circuit for wordline voltage - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line voltage boosting circuit, and in particular, a boosting means for boosting a word line voltage to stabilize the operation of the boosting circuit at a high power supply voltage and to reduce cell stress, and detecting a rise in the power supply voltage. And a clamp feedback means for sensing the boosted voltage by the boost means and outputting the result to the boost means, and a control means for outputting an operation signal of the boost means.

Wordline, Boost, Clamp

Description

A boosting circuit for wordline voltage             

1 is a circuit diagram of a conventional word line voltage boosting circuit.

2 is a characteristic diagram of FIG.

3 is a circuit diagram of a word line voltage boosting circuit according to the present invention;

4 is a characteristic diagram of FIG. 3.

Explanation of symbols on the main parts of the drawings

40: boost means 41: first precharge unit

42: 2nd precharge 43: 5th inverter chain

44: NOR gate 45: NAND gate

50: clamp feedback means 51: voltage distribution

60: output means 70: control means

71: 6th inverter chain 72: 7th inverter chain

The present invention relates to a flash memory, and more particularly, to a word line voltage boosting circuit that can stabilize the operation of the boosting circuit at high power supply voltage and reduce cell stress.

1 is a circuit diagram of a conventional boosting circuit.

Referring to FIG. 1, a conventional boosting circuit includes a boost means 10, a control means 30, and an output means 20, wherein the boost means 10 includes a first precharge part 11 and a second precharge. A branch 12 is included.

In the first precharge unit 11, a first PMOS transistor P1 and a first bipolar transistor Q1 are connected between the power supply voltage Vcc and the node boot1, and between the gate and the node boot1 of the first PMOS transistor P1. The second PMOS transistor P2 is connected to it. The first NMOS transistor N1 is connected between the gate and the ground of the first PMOS transistor P1, and the precharge signal PRECHAR described later is input to the gates of the first NMOS transistor and the second PMOS transistor P2.

Not only the first capacitor C1 and the first inverter chain 13 are sequentially connected to the node boot1, but also the second capacitor C2 and the second inverter chain 14 are connected to form a boost circuit.

A fifth PMOS transistor P5 is connected between the node boot1 and the node boot2, and a signal SWON described later is input to the gate of the fifth PMOS transistor P5. The third capacitor C3 is connected between the node boot2 and the node VBOOST, and the third NMOS transistor N3 is connected between the node boot2 and the ground. The output terminal of the inverter I1 is connected to the gate of the third NMOS transistor N3, and the output terminal of the NAND gate 15 is connected to the input terminal of the inverter I1. The signals SWON and DKICKb are input to the input terminal of the NAND gate 15.

The second precharge unit 12 is connected to the node VBOOST as follows.

In the second precharge unit 12, a third PMOS transistor P3 and a second bipolar transistor Q2 are connected between the power supply voltage Vcc and the node VBOOST, and between the gate and the node VBOOST of the third PMOS transistor P3. The fourth PMOS transistor P4 is connected to it. The second NMOS transistor N2 is connected between the gate and the ground of the third PMOS transistor P3, and the precharge signal PRECHAR is input to the gate of the second NMOS transistor and the fourth PMOS transistor P4.

The node VBOOST is connected with an output terminal consisting of a resistor R1 and fourth and fifth capacitors C4 and C5.

On the other hand, the control means 30 serves to distribute the signal SATDb by using an inverter, the inverter I2, the third inverter chain 31, the inverter I3 and the inverter I4 are connected in series, The fourth inverter chain 32 is connected between the three inverter chain 31 and the inverter I3. At this time, the output of the inverter I2 is the precharge signal PRECHAR, the output of the inverter I4 becomes the signal SWON, and the output of the fourth inverter chain 32 becomes the signal DKICKb.

Hereinafter, the operation of the above-described conventional boosting circuit will be described.

If the signal SATDb is initially a low signal, the precharge signal PRECHAR signal becomes a high signal by the inverter I2, and the signals SWON and DKICKb also become high signals.

First, the fifth PMOS transistor P5 is turned off by the high signal SWON.

When the precharge signal PRECHAR is a high signal, the first NMOS transistor N1 of the first precharge unit 11 is turned on while the second PMOS transistor P2 is turned off. When the first NMOS transistor N1 is turned on, ground is applied to the gate of the first PMOS transistor P1, and the first PMOS transistor P1 is turned on. Similarly, when the precharge signal PRECHAR is a high signal, the second NMOS transistor N2 of the second precharge unit 12 is turned on while the fourth PMOS transistor P4 is turned off. When the second NMOS transistor N2 is turned on, the ground is applied to the gate of the third PMOS transistor P3 and the third PMOS transistor P3 is turned on. Therefore, the node boot1 and the node VBOOST are charged to the power supply voltage Vcc level by the first precharge unit and the second precharge unit.

On the other hand, when the high signals SWON and DKICKb are input to the NAND gate, the NAND gate outputs a low signal, and the low signal is converted into a high signal through the inverter I1 and then input to the gate of the third NMOS transistor N3. Turn on the 3NMOS transistor N3. When the third NMOS transistor N3 is turned on, the node boot2 is at the ground level.

When the high signal SATDb is input to the control means, the precharge signal PRECHAR and the signals SWON and DKICKb output from the control means become low signals.

When the precharge signal PRECHAR becomes a low signal, the first NMOS transistor N1 of the first precharge unit 11 is turned off while the second PMOS transistor P2 is turned on. Accordingly, the first PMOS transistor P1 is turned off. Similarly, in the second precharge unit 12, when the precharge signal PRECHAR becomes a low signal, the second NMOS transistor N2 is turned off while the fourth PMOS transistor P4 is turned on. Accordingly, the third PMOS transistor P3 is turned off.

When the signal DKCKIb becomes a low signal, the output terminals of the first inverter chain 13 and the second inverter chain 14 go low. Accordingly, the first and second capacitors C1 and C2 are occupied so that the potential of the node boot1 becomes high. Will rise. At this time, while the fifth PMOS transistor P5 is turned on, the third NMOS transistor N3 is turned off to increase the potential of the node boot2. Accordingly, the potential of the node VBOOST rises and the boosting voltage is output to the word line through the output means 20 of the potential of the node VBOOST.

Referring to FIG. 2, as the power supply voltage increases, the voltage output to the word line also increases significantly. That is, in the conventional boosting circuit, when the power supply voltage Vcc is increased, the boosting voltage is also increased, and the variation of the voltage output to the word line is large.

Therefore, the present invention, the word line voltage including a clamping circuit to stabilize the operation of the boosting circuit at a high power supply voltage and to reduce the cell stress so that the boosting voltage supplied to the word line does not change significantly even if the power supply voltage changes It is an object to provide a boosting circuit.

In order to achieve the above object, the word line voltage boosting circuit according to the present invention includes a boost means for boosting a word line voltage and a boosted voltage sensed by the boost means to detect an increase in the power supply voltage. And a clamp feedback means for outputting the means and a control means for outputting an operation signal of the boost means.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

Referring to FIG. 3, the word line voltage boosting circuit according to the present invention includes a boosting means 40, a control means 70, a clamp feedback means 50, and an output means 60. Includes a first precharge unit 41 and a second precharge unit 42.

The first precharge unit 41 is as follows.

The sixth PMOS transistor P6 and the third bipolar transistor Q3 are connected between the power supply voltage Vcc and the first node node1, and the sixth PMOS transistor P6 is connected between the gate and the first node node1 of the sixth PMOS transistor P6. The 7 PMOS transistor P7 is connected. In addition, the fourth NMOS transistor N4 is connected between the gate and the ground of the sixth PMOS transistor P6 described above, and the gate of the fourth NMOS transistor N4 and the seventh PMOS transistor P7 is output by the control means 70 described later. The precharge signal PRECHAR is input.

The sixth capacitor C6 and the fifth inverter chain 43 are sequentially connected to the first node node1, and the signal DKICKb output from the control means 70 to be described later is connected to the input terminal of the fifth inverter chain 43. Is input. In addition, a seventh capacitor C7, an inverter I7, and an inverter I6 are connected to the first node node1, and an input terminal of the inverter I6 is connected to an output terminal of the NOR gate 44. At this time, the signal DKICKb output from the control means 70 and the signal SENSE which are the output signals of the clap feedback unit 50 are input to the input terminal of the NOR gate.

Meanwhile, a tenth PMOS transistor P10 is connected between the first node node1 and the second node node2, and a signal SWON output from the control means 70 to be described later is input to the gate of the tenth PMOS transistor P10. do. The eighth capacitor C8 is connected between the second node node2 and the third node node3, and the sixth NMOS transistor N6 is connected between the second node node2 and the ground. The output terminal of the inverter I5 is connected to the gate of the sixth NMOS transistor N6, and the input terminal of the inverter I5 is connected to the output terminal of the NAND gate 45. The signals SWON and DKICKb output from the control means 7 are input to the input terminal of the NAND gate 45.

The second precharge unit 42 is connected to the third node node3 as follows.

The eighth PMOS transistor P8 and the fourth bipolar transistor Q4 are connected between the power supply voltage Vcc and the third node node3, and the eighth PMOS transistor P8 is connected between the gate and the third node node3 of the eighth PMOS transistor P8. The 9 PMOS transistor P9 is connected. In addition, a fifth NMOS transistor N5 is connected between the gate and the ground of the ninth PMOS transistor P9, and the precharge signal output from the control means 70 is connected to the gate of the fifth NMOS transistor N5 and the ninth PMOS transistor P9. (PRECHAR) is entered.

The clamp feedback means 50 and the output means 60 are connected to the third node node3. The output means 60 includes a resistor R2 and ninth and tenth capacitors C9 and C10.

The above-described clamp feedback means 50 is as follows.

First, a voltage divider 51 made up of an eleventh PMOS transistor or a fifteenth PMOS transistor P11 to P15 is provided to the third node and the fourth node node4 so as to distribute the potential of the third node node3. Connected. A seventh NMOS transistor N7 and an eighth NMOS transistor N8 are connected between the fourth node and the ground, and the reset signal is reset to reset the potential of the fourth node according to the reset signal. A ninth NMOS transistor N9 input to the gate is connected between the fourth node node4 and ground. In addition, an inverter I11 and an inverter I12 are connected to the fourth node node4 so as to output a signal according to the potential state of the fourth node node4. At this time, the output signal of the inverter I12 becomes the signal SENSE, which is not only a gate of the eighth NMOS transistor N8 through the inverter I13 but also an input terminal of the NOR gate 44 of the boost means 40. Is entered.

On the other hand, the control means 70 serves to generate various signals by distributing and delaying the signal SATDb using an inverter, the inverter I8, the sixth inverter chain 71, the inverter I9 receiving the signal SATDb And an inverter I10 are connected in series, and a seventh inverter chain 72 is connected between the sixth inverter chain 71 and the inverter I9. At this time, the output of the inverter I8 is the precharge signal PRECHAR, the output of the inverter I10 becomes the signal SWON, and the output of the seventh inverter chain 72 becomes the signal DKICKb.

Hereinafter, the operation of the present invention according to the timing shown in FIG. 4 will be described.

Initially, the signal SATDb is a low signal and the reset signal is a high signal. If the signal SATDb is a low signal, the precharge signal PRECHAR signal becomes a high signal by the inverter I8, and the signals KICKb, SWON and DKICKb also become high signals.

The tenth PMOS transistor P10 is turned off by a high signal SWON. The fourth NMOS transistor N4 of the first precharge unit 41 is turned on by the precharge signal PRECHAR, which is a high signal, while the seventh PMOS transistor P7 is turned off. When the fourth NMOS transistor N4 is turned on, ground is applied to the gate of the sixth PMOS transistor P6, and the sixth PMOS transistor P6 is turned on. Similarly, the fifth NMOS transistor N5 of the second precharge unit 42 is turned on by the precharge signal PRECHAR which is a high signal while the ninth PMOS transistor P9 is turned off. When the fifth NMOS transistor N5 is turned on, the ground is applied to the gate of the eighth PMOS transistor P8, and the eighth PMOS transistor P8 is turned on. Therefore, the first node (node1) and the third node (node3) is charged to the power supply voltage (Vcc) level by the first precharge unit 41 and the second precharge unit 42.

On the other hand, when high signals SWON and DKICKb are input to the NAND gate 45, the NAND gate 45 outputs a low signal, and the low signal is converted into a high signal through the inverter I5, and then the sixth NMOS transistor N6. Is input to the gate of to turn on the sixth NMOS transistor N6. When the sixth NMOS transistor N6 is turned on, the second node node2 is at the ground level.

At this time, the reset signal is applied to the gate of the ninth NMOS transistor N9 to turn on the ninth NMOS transistor N9. When the ninth NMOS transistor N9 is turned on, the fourth node becomes the ground level, and the inverter I12 outputs a low signal SENSE.

When the low signal SENSE is input to the NOR gate 44, the signal DKICKb is also input to the NOR gate 44. Accordingly, the NOR gate 44 outputs a low signal, and the low signal output from the NOR gate 44 is applied to the seventh capacitor C7 through the inverter I6 and the inverter I7. In addition, when the high signal DKICKb is input to the fifth inverter chain 43, the fifth inverter chain 43 outputs a low signal, and the sixth capacitor C6 and the seventh capacitor C7 are potentials of the first node. Will boost

When the high signal SATDb is input to the control means 70, the precharge signal PRECHAR and the signals SWON and DKICKb output from the control means 70 become low signals.

When the precharge signal PRECHAR becomes a low signal, the fourth NMOS transistor N4 of the first precharge unit 41 is turned off while the seventh PMOS transistor P7 is turned on. Accordingly, the sixth PMOS transistor P6 is turned off. Similarly, in the second precharge unit 42, when the precharge signal PRECHAR becomes a low signal, the fifth NMOS transistor N5 is turned off while the ninth PMOS transistor P9 is turned on. Accordingly, the eighth PMOS transistor P8 is turned off.

As the signals DKICKb and SWON become low signals, the NAND gate 45 outputs a high signal, and the high signal is converted into a low signal through the inverter I5 to turn off the sixth NMOS transistor N6. On the other hand, the tenth PMOS transistor P10 is turned on by the low signal SWON to connect the first node node1 and the second node node2. At this time, the fifth inverter chain 43 receives the low signal DKICKb and outputs a high signal. Accordingly, the potentials of the first node node1 and the second node node2 are increased.

When the potentials of the first node node1 and the second node node20 rise, the potential of the third node node3 rises, and the potential of the third node node3 is output through the output means 60 (BOOT_OUT). do.

On the other hand, the clamp feedback means 50 senses the potential of the third node (node3), the potential of the third node (node3) is distributed by the voltage distribution unit 51. In this case, when the power supply voltage is about 2.3 volts or less, the potential appearing at the fourth node node4 is lower than or equal to the threshold voltage of the inverter I11 by the above-described voltage distribution, and the inverter I12 outputs a low signal SENSE. At this time, the low signal SENSE is converted into a high signal through the inverter I13 to turn off the eighth NMOS transistor N8.

The low signal SENSE is input to the input terminal of the NOR gate 44. The NOR gate 44 outputs a high signal by the low signals SENSE and DKICKb, and the high signal output from the NOR gate 44 is an inverter I6. And the seventh capacitor C7 through the inverter I7. Accordingly, the sixth capacitor C6 and the seventh capacitor C7 have a boosting function.

However, when the power supply voltage Vcc is increased, the boosting voltage is also increased, and the voltage of the third node node3 is also increased. When the power supply voltage Vcc is about 2.3 volts or more, the voltage of the fourth node node4 through the voltage distribution unit 51 exceeds the threshold voltage of the inverter I11, and the inverter I12 outputs a high signal SENSE. Accordingly, the eighth NMOS transistor N8 is turned off.

When the high signal SENSE is output from the inverter I12, the NOR gate 44 outputs a low signal. Finally, a low signal is applied to the seventh capacitor C7 to stop the boosting operation of the seventh capacitor C7. do. When the seventh capacitor C7 stops the boosting action, the potential of the third node node3 is lowered.

Referring to FIG. 4, even when the power supply voltage VCc increases, the boosting voltage does not increase very much. That is, when the power supply voltage Vcc rises above a certain voltage, the seventh capacitor C7 does not perform a boosting operation, thereby stabilizing the voltage of the BOOT_OUT finally output.

According to the present invention, even when the power supply voltage increases, the boosting voltage supplied to the word line is not greatly changed, thereby making it possible to stabilize the operation of the boosting circuit at a high power supply voltage and to reduce cell stress.

Claims (6)

Boost means for boosting the word line voltage; Clamp feedback means for sensing the boosted voltage by the boost means to detect the rise of the power supply voltage and outputs the result to the boost means; And a control means for outputting an operation signal of the boost means. The method of claim 1, The boost means includes a first precharge part connected to a first node, a boost part connected to the first node to boost the potential of the first node, and a connection between the first node and the second node. And a second precharge portion connected to the first switching element and the third node. The method of claim 2, The boost part includes an inverter chain having one end connected to the sixth capacitor C6 connected to the first node, an output end connected to the other end of the sixth capacitor C6, and one end connected to the first node. Word line voltage boosting, characterized in that it comprises a seventh capacitor (C7), the output terminal is connected to the other end of the seventh capacitor (C7), and the NOR gate output terminal is connected to the input terminal of the inverter Circuit. The method of claim 2, The clamp feedback means includes a voltage divider connected between a third node and a fourth node so as to distribute a potential of the third node to which a boosting voltage is output, and a seventh NMOS transistor connected between the fourth node and the ground. N7 and 8th NMOS transistors N8 and a ninth NMOS transistor connected between the fourth node and the ground so as to reset the potential of the fourth node according to a reset signal, and receiving the reset signal as a gate. N9) and a plurality of inverters connected to the fourth node to output a signal according to the potential state of the fourth node. The method of claim 4, wherein And the voltage divider is a plurality of PMOS transistors connected in series. The method of claim 4, wherein And an output terminal of the inverter connected to the fourth node is connected to an input terminal of a NOR gate of the boost unit.

Images