JPH10144080A - Boosting circuit and boosting control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the node potential at the time of a precharge operation to be held at a potential higher than the threshold value of a capacitor by providing a function precharging the capacitor in a non-boosting period. SOLUTION: A boosting circuit 10 has a charge clamping means 20, a driving means 30 and a MOS capacitor Q3. The MOS capacitor Q3 is connected in between a gate being the input end of the transistor for precharge Tr1 of a first stage and the drain being the output end of the transistor for precharge Trn of the final stage. The charge clamping means 20 has the transistors for precharge Tr1-Trn of plural stages connected in between a power source and a boosting node P and has a function precharging the potential of the MOS capacitor Q3 to a power source potential Vcc by activating all transistors for precharge Tr1, Tr2 in the non-boosting period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a booster circuit for boosting a potential of a node in a circuit network to a bootstrap potential higher than a power supply potential.

More specifically, the present invention relates to a boosting circuit for boosting the potential of a word line in a circuit network to a bootstrap potential which is several times the power supply potential when writing in an integrated circuit such as a memory element.

[0003]

2. Description of the Related Art Generally, a booster circuit is used in various circuits in a semiconductor integrated circuit to generate a boosted voltage exceeding a given power supply potential level.

For example, in a semiconductor memory such as a DRAM or an SRAM, it is used to boost a selected word line to a high level exceeding a power supply potential.

FIG. 4 is a circuit diagram for explaining a first conventional booster circuit.

As shown in FIG. 4, a booster circuit A of the first conventional example includes an NMOS transistor Q1 connected between a power supply potential Vcc and a booster node P, and a booster circuit connected to the booster node P for boosting. MOS capacitor 3.

In operation, the boosting node P is connected before boosting,
It is precharged to the potential of power supply potential Vcc-threshold voltage Vth1. Further, at the time of boosting, when the clock signal CK giving the boosting timing rises from the ground potential to the power supply potential Vcc, the potential of the boosting node P is boosted by capacitive coupling of the MOS capacitor (capacitance C0) 3.

Such a booster circuit A is often used to boost a word line or the like of a memory device such as a RAM or an EEPROM to a power supply potential or higher in order to speed up a semiconductor integrated circuit.

FIG. 5 is a circuit diagram for explaining a booster circuit according to a second conventional example.

A second prior art booster circuit is disclosed in Japanese Patent Application Laid-Open No. Hei 6-187788 (title: booster circuit,
(Filing date: December 17, 1992).

As shown in FIG. 5, in a booster circuit B, a back gate electrode of a PMOS transistor Q2 connected between a power supply potential Vcc and a booster node 2 has a PMOS transistor Q3 and a MOS capacitor (capacitance C0) 3. And was configured to be connected.

In such a boosting circuit B, the boosting node 2 is precharged to the power supply potential Vcc level in a period before boosting. Therefore, it is disclosed that the boosting condition by the MOS capacitor 3 is relaxed, and even if the level of the applied power supply potential Vcc is lowered, an effect is obtained that a normal boosting operation can be performed.

[0013]

However, in such a booster circuit A of the first conventional example, the potential of the booster node P at the time of the precharge operation is set to the MOS level in order to operate normally.
Although it is necessary to be higher than the threshold voltage Vth1 of the capacitor 3, the power supply potential Vcc tends to decrease in accordance with technical requirements for miniaturization of a circuit and reduction of power consumption.
Use at ~ 2.0V is also required.

Therefore, the booster circuit A has a technical problem that it is difficult to make the potential of the booster node P equal to or higher than the threshold voltage Vth1 of the MOS capacitor 3 during the precharge operation.

When the booster circuit A is used in an apparatus which performs battery driving, the guaranteed value of the power supply potential Vcc is 1.5 to
Since the power supply potential is as wide as 3.6 V, when the power supply potential Vcc is designed as a low voltage side, an over-boosted state may occur on the high voltage side of the power supply potential Vcc, and as a result, the device may be destroyed. There was also a technical problem that there was. It is.

In the boosting circuit B of the second conventional example, since the Pch transistor Q2 is used for the precharge operation, the potential of the boosting node 2 can be kept at the power supply potential Vcc during the precharge. At the time of boosting, the Pch transistor Q2 becomes non-conductive and the boosting node 2 is boosted. However, since the clamp circuit is not used, there is a possibility that excessive boosting may occur. There was a technical problem that could lead to destruction.

An object of the present invention is to solve such a conventional problem. In particular, a booster circuit for boosting the potential of a node in a circuit network to a bootstrap potential higher than a power supply potential is provided. And a plurality of stages of precharge transistors connected in series between the
During the boosting period, a predetermined potential is input to the precharge transistor, and the bootstrap potential determined by the sum of the threshold voltage of each precharge transistor and the power supply potential is connected to the last stage precharge transistor. And a charging clamp means configured to activate all the precharging transistors to precharge the capacitor potential to the power supply potential during the non-boosting period. Power supply potential can be supplied to the MOS capacitor during the precharge operation during the non-boosting period. As a result, sufficient boosting can be performed even at a low voltage, and excessive boosting can be performed even during a high voltage boosting period. To provide a booster circuit and a booster control method capable of preventing device destruction caused by the That.

[0018]

According to a first aspect of the present invention, there is provided a booster circuit for boosting the potential of a node P in a circuit network to a bootstrap potential higher than a power supply potential Vcc. The potential of the capacitor Q3 connected to the node P is precharged to the power supply potential Vcc of the power supply, and during the boosting period, the capacitor potential is boosted, and the capacitor potential is changed to the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2). ) +... + Vth (trn)], the capacitor potential is clamped, and the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2) +.
th (trn)], which is a booster circuit 10 having charge clamp means 20 for preventing excessive boosting.

According to the first aspect of the present invention, by providing such a precharge function, the power supply potential Vcc can be supplied to the capacitor Q3 during the precharge operation during the non-boosting period. As a result, there is an effect that the potential of the node P during the precharge operation can be held at the power supply potential Vcc.

The provision of such a clamping function has an effect that the device can be prevented from being destroyed due to excessive boosting even during the boosting period at a high voltage.

According to a second aspect of the present invention, in the booster circuit according to the first aspect, the charging clamp means includes:
A plurality of stages of precharge transistors Tr1,..., Trn connected in series between a power supply and the node P. A predetermined potential is input to the precharge transistors during the boosting period. Tr2, ...,
Trn is activated, and the precharge transistor Tr excluding the first-stage precharge transistor Tr1 is activated.
,..., Trn each have a threshold voltage Vth (Vth (tr2),
, Vth (trn)) and the power supply potential Vcc, the bootstrap potential [Vcc + Vth (tr1) + Vth].
(tr2) +... + Vth (trn)] so as to clamp the potential of the capacitor Q3 connected to the last-stage precharge transistor Trn.

According to the invention described in claim 2, according to claim 1,
In addition to the effects described in (1), by providing such a clamping function in the charging clamp means 20, it is possible to prevent the destruction of the device due to excessive boosting even during the high voltage boosting period. This has the effect.

As a result, the booster circuit 10 is used to target the lower voltage side of the power supply potential Vcc in an apparatus that performs a wide range of battery driving, for example, the guaranteed value of the power supply potential Vcc is 1.5 to 3.6 V. Even if you design as
This makes it possible to avoid the occurrence of an over-boosted state on the high voltage side of the power supply potential Vcc, thereby providing an effect of avoiding device destruction due to such an over-boosted state.

According to a third aspect of the present invention, in the booster circuit according to the second aspect, the charging clamp means includes:
, Trn are activated during the non-boosting period to precharge the potential of the capacitor Q3 to the power supply potential Vcc. is there.

According to the invention described in claim 3, according to claim 2
In addition to the effects described in the above, the provision of such a precharge function in the charging clamp means 20 makes it possible to supply the power supply potential Vcc to the capacitor Q3 during the precharge operation during the non-boosting period. , The potential of the node P during the precharge operation can be held at a potential higher than the threshold voltage Vth of the capacitor Q3 (that is, the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2) +... + Vth (trn)]). It has the effect of becoming

For example, in accordance with technical demands for circuit miniaturization and reduction of power consumption, even when a low power supply potential Vcc of about 1.5 to 2.0 V is used, a sufficient boosting operation can be performed. It has the effect of being able to do so.

According to a fourth aspect of the present invention, in the booster circuit of the third aspect, the precharging transistors Tr1,..., Trn are Pch transistors, and the charging clamp means 20 operates during the boosting period. , Trn, a predetermined potential is inputted to the precharging Pch transistors Tr1,.
, Vth (Vth (tr2),..., Vth
(trn)) and the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2) +... determined by the sum of the power supply potential Vcc.
+ Vth (trn)] so as to clamp the potential of the capacitor Q3 connected to the last-stage precharging Pch transistor Trn.

According to the invention described in claim 4, according to claim 3,
In addition to the effect described in (1), the Pch transistor T
The potential of the capacitor Q3 connected to rn is changed to the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2) +.
By providing the clamping function in n)]), there is an effect that the device can be prevented from being destroyed due to excessive boosting even during the boosting period at a high voltage.

According to a fifth aspect of the present invention, in the step-up circuit of the fourth aspect, the charging clamp means 20 comprises:
During the non-boosting period, all the precharging Pch transistors Tr1,.
The booster circuit 10 is configured to precharge the potential of No. 3 to the power supply potential Vcc.

According to the fifth aspect of the present invention, a third aspect is provided.
In addition to the effects described in
The transistors Tr1,.
Has the effect that the power supply potential Vcc can be supplied to the capacitor Q3 during the precharge operation during the non-boosting period.

For example, even when a low power supply potential Vcc of about 1.5 to 2.0 V is used in accordance with technical requirements for miniaturization of a circuit and reduction of power consumption, the power supply potential Vcc is not changed by a capacitor. There is an effect that a sufficient boosting operation can be performed by supplying the voltage to Q3.

According to a sixth aspect of the present invention, in the booster circuit 10 according to the fifth aspect, the charging clamp means 20 comprises:
During the boosting period, the precharge transistor Tr
A predetermined potential is input to 1,.
A predetermined potential is input to each gate of each of the channel transistors Tr1,..., Trn and activated, and the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2) +.
n)] is configured to clamp the potential of the capacitor Q3.

According to the invention described in claim 6, according to claim 5,
In addition to the effects described in
The transistors Tr1,.
, It is possible to avoid the occurrence of an over-boosted state on the high voltage side of the power supply potential Vcc, and it is possible to avoid device destruction caused by such an over-boosted state.

According to a seventh aspect of the present invention, in the booster circuit 10 according to the sixth aspect, the charging clamp means 20 comprises:
During the non-boosting period, a predetermined potential is input to the gates of all the precharging Pch transistors Tr1,..., Trn to activate them, and the potential of the capacitor Q3 is changed to the power supply potential Vcc.
The booster circuit 10 is configured so as to be precharged.

According to the invention described in claim 7, according to claim 6,
The same effect as the effect described in (1) is obtained.

The invention described in claim 8 is the invention according to claims 1 to 7
In the booster circuit 10 according to any one of the above, the final stage precharge transistor Trn and the ground potential GN
D-channel driving P-channel transistor Q
1 and a driving Nch transistor Q2, and a driving means 30 having a connection point between the driving Pch transistor Q1 and the driving Nch transistor Q2 connected to the gate of the final-stage precharging transistor Trn. The booster circuit 10 is characterized in that:

According to the invention of claim 8, according to claim 1,
In addition to the effects described in any one of (1) to (7), by providing such a driving means 30, a simple circuit configuration can be used.
It is possible to execute the control of the precharge operation and the clamp operation of the charging clamp means 20 and to realize the low-cost booster circuit 10 capable of reducing the circuit scale.

The invention according to claim 9 is the invention according to claims 1 to 8
In the booster circuit 10 according to any one of the above, the capacitor Q3 is a MOS capacitor Q3, and is connected between an input terminal of the first-stage precharge transistor Tr1 and an output terminal of the last-stage precharge transistor Trn. Connected to the booster circuit 10.

According to the ninth aspect of the present invention, there is provided the first aspect.
In addition to the effects described in any one of (1) to (8), by using the MOS capacitor Q3 suitable for the integrated circuit, the MOS capacitor Q3 can be used during the precharge operation in the non-boosting period by using the precharge function described above. To supply a power supply potential to the circuit can be realized with a simple and compact circuit scale.

According to a tenth aspect of the present invention, in the booster circuit according to any one of the first to ninth aspects, the driving N is controlled according to a boost control signal V (CKB) in a non-boost period.
By activating the channel transistor Q2 and inactivating the driving Pch transistor Q1, the first-stage precharge transistor Tr1 to the last-stage precharge transistor Trn in the charge clamp means 20 are activated. In addition, a boosting control method for the boosting circuit 10 is characterized in that the potential of the MOS capacitor Q3 is precharged to the power supply potential Vcc to generate a boosted output signal 13.

According to the tenth aspect of the present invention, the same effect as any one of the first to ninth aspects can be obtained.

According to an eleventh aspect of the present invention, in the boosting control method according to the tenth aspect, the driving Nch transistor Q2 is inactivated in response to a boosting control signal V (CKB) during a boosting period. After activating the driving Pch transistor Q1 to inactivate the first-stage precharge transistor Tr1, all the first-stage precharges except for the first-stage precharge transistor Tr1 using the capacitive coupling of the MOS capacitor Q3. The transistor Tr1 is activated to clamp the potential of the MOS capacitor Q3 to the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2) +... + Vth (trn)] to generate a boosted output signal 13. This is a step-up control method.

According to the eleventh aspect, the same effect as the tenth aspect can be obtained.

According to a twelfth aspect of the present invention, in the boost control method according to the eleventh aspect, the boost control signal is used as a clock signal corresponding to the non-write during a non-boost period corresponding to the non-write to the memory element. By using V (CKB) to activate the driving Nch transistor Q2 and deactivate the driving Pch transistor Q1 of the driving means 30, the first stage precharging Pch transistor Tr1 to the last stage Pch for precharge
Activating the transistor Trn and precharging the potential of the MOS capacitor Q3 to the power supply potential Vcc,
A boost control method is characterized in that the boost output signal 13 is generated and supplied to a word line of the memory element.

According to the twelfth aspect of the invention, the same effects as those of the eleventh aspect can be obtained.

According to a thirteenth aspect of the present invention, in the boosting control method according to the twelfth aspect, the boosting control signal V (CKB) is used as a clock signal corresponding to the writing during the boosting period according to the writing to the memory element. ), The driving Nch transistor Q2 is inactivated, the driving Pch transistor Q1 is activated, and all the first stage precharge transistors Tr1,. , Trn are activated, and the bootstrap potential [Vcc + Vth (tr1) +
Vth (tr2) +... + Vth (trn)]
3 is a boost control method, wherein the boosted output signal 13 is generated and supplied to the word line of the memory element.

According to the thirteenth aspect, the same effect as the twelfth aspect can be obtained.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

Each of the booster circuits 10 of the first and second embodiments disclosed below supplies a boosted voltage (unit: [V]) exceeding a given power supply potential level (that is, power supply potential Vcc). Since it occurs, it is used in a circuit network in a semiconductor integrated circuit such as an IC or an LSI.

For example, in a semiconductor memory device such as a DRAM (abbreviation of Dynamic RAM) or an SRAM (abbreviation of Static RAM), a voltage higher than a power supply potential may be required for an operation such as writing in the memory. For example, D
In a RAM or a high-speed SRAM, the level of the logic value H of the word line is set to a voltage higher than the power supply potential Vcc by at least twice the threshold voltage in order to prevent a voltage drop and a reduction in speed due to the threshold voltage of the transfer gate. It is necessary to boost (this is called bootstrap). In addition, EPRO
In M and EEPROM, a voltage higher than the power supply potential is required during a program operation.

Therefore, the booster circuit 10 sets the selected word line at a high voltage level exceeding the power supply potential Vcc (a voltage level several times the power supply potential Vcc, that is, the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2)). ]] Is a circuit means used to boost the voltage.

Next, a first embodiment will be described.

FIG. 1 is a circuit diagram for explaining a basic configuration of the first embodiment of the booster circuit 10.

As shown in FIG. 1, the booster circuit 10 includes a charging clamp means 20, a driving circuit 30, and a MOS capacitor Q
3 and has.

The MOS capacitor Q3 is a MOS capacitor, and is a first-stage precharge Pch transistor T
The gate which is the input terminal of r1 and Pc for the last stage precharge
It is connected between the output terminal of the h transistor Trn and the drain.

As described above, by using the MOS capacitor Q3 suitable for the integrated circuit, it is possible to supply the power supply potential to the MOS capacitor Q3 during the precharge operation in the non-boosting period by using the above-described precharge function. This has the effect of being able to be realized with a simple and compact circuit scale.

The charging clamp means 20 includes a plurality of stages of precharging Ps connected in series between the power supply and the boosting node P.
, Trn. Therefore, in the present embodiment, a case where the precharging Pch transistors Tr1 and Tr2 are connected in series between the power supply and the boosting node P will be described.

The charging clamp means 20 operates during the non-boosting period,
It has a function of precharging the potential of the MOS capacitor Q3 connected to the boost node P (specifically, a node connected to the word line) to the power supply potential Vcc of the power supply (hereinafter, abbreviated as precharge).

Specifically, the charging clamp means 20 has a function of activating all the precharging Pch transistors Tr1 and Tr2 to precharge the potential of the MOS capacitor Q3 to the power supply potential Vcc during the non-boosting period.

By providing such a precharge function in the charging clamp means 20, the power supply potential Vcc can be supplied to the MOS capacitor Q3 during the precharge operation in the non-boosting period. This has the effect that the potential of the boosting node P at the time can be held at Vcc.

For example, in accordance with technical requirements for circuit miniaturization and reduction in power consumption, even when a low power supply potential Vcc of about 1.5 to 2.0 V is used, a sufficient boosting operation can be performed. It has the effect of being able to do so.

The charge clamp means 20 operates during the step-up period.
While boosting the OS capacitor Q3, the voltage of the MOS capacitor Q3 changes to the bootstrap potential [Vcc + Vth (tr1) + V
th (tr2)], the MOS capacitor Q3 is clamped and the bootstrap potential [Vcc + Vth (tr1) + Vth (tr)
2)] to prevent over-boosting (hereinafter abbreviated as a clamp function).

More specifically, the charging clamp means 20 operates the first-stage precharging Pch connected to the power supply during the boosting period.
Has a function of inactivating the transistor Tr1,
Each of the precharging Pch transistors Tr2,..., Trn except the first-stage precharging Pch transistor Tr1 is activated, and the precharging Pch transistors Tr2,.
, Trn each threshold voltage Vth (Vth (tr2), ...,
Vth (trn)) and the power supply potential Vcc, and clamps the potential of the MOS capacitor Q3 connected to the pre-charging Pch transistor Trn at the final stage to the bootstrap potential [Vcc + Vth (tr1) + Vth (tr2)]. It has a function to do.

At this time, a boosting control signal V (CKB) for giving a boosting timing (that is, a clock signal CK which is a timing signal for writing to the memory element) is supplied to the boosting circuit 10.
, The MOS capacitor Q3
Due to the capacitive coupling of (capacitance C0), the potential of the boosting node P is boosted.

By providing such a clamping function in the charging clamp means 20, there is an effect that the device can be prevented from being destroyed due to excessive boosting even during the high voltage boosting period.

As a result, the booster circuit 10 is used to target the lower voltage side of the power supply potential Vcc in an apparatus which performs a wide range of battery driving, for example, the guaranteed value of the power supply potential Vcc is 1.5 to 3.6 V. Even if you design as
This makes it possible to avoid the occurrence of an over-boosted state on the high voltage side of the power supply potential Vcc, thereby providing an effect of avoiding device destruction due to such an over-boosted state.

As described above, by providing charging clamp means 20 having such a function, power supply potential Vcc can be supplied to MOS capacitor Q3 during the precharge operation during the non-boosting period. As a result, there is an effect that the potential of the boosting node P during the precharge operation can be held at a potential higher than the threshold voltage Vth of the MOS capacitor Q3.

By providing such a clamping function, there is an effect that the device can be prevented from being damaged due to excessive boosting even during the boosting period at a high voltage.

On the other hand, as shown in FIG. 1, the driving means 30 is provided with the last-stage precharge Pch transistor Tr.
drive Pc connected in series between n and ground potential GND
h transistor Q1 and a driving Nch transistor Q2, and a connection point between the driving Pch transistor Q1 and the driving Nch transistor Q2 is a final stage precharge Pc.
It is configured to be connected to the gate of the h transistor Trn.

By providing such a driving means 30, it is possible to control the precharging operation and the clamping operation of the charging clamp means 20 with a simple circuit configuration, and to reduce the circuit scale at a low cost. Booster circuit 1
0 is achieved.

The boost control method will be described.

FIG. 2 is a timing chart for explaining a boost control method used in boost circuit 10 of FIG.

This boosting control method activates the driving Nch transistor Q2 and inactivates the driving Pch transistor Q1 in response to the boosting control signal V (CKB) during the non-boosting period, thereby charging the battery. The first-stage precharge Pch transistor Tr1 to the last-stage precharge Pch transistor Trn in the clamp means 20 are activated, and the potential of the MOS capacitor Q3 is changed to the power supply potential Vcc.
To generate the boosted output signal 13 by pre-charging.

Further, in response to the boost control signal V (CKB) during the boost period, the driving Nch transistor Q2 is inactivated, the driving Pch transistor Q1 is activated, and the capacitive coupling of the MOS capacitor Q3 is used. , Trn are activated to activate the bootstrap potential [Vcc + Vth (tr1) +
[Vth (tr2)] to generate the boosted output signal 13 by clamping the potential of the MOS capacitor Q3.

The boost control method and the basic operation of the booster circuit 10 when this method is used will be described in more detail.

First, during the non-boosting period, as shown in FIG. 2, the boost control signal V (CKB) has a logical value H (= power supply potential Vcc), and the boost control signal V (CKB) using the logic element NOT32. ) Is a logical value L (ground potential GND) as shown in FIG.

In the charging clamp means 20, the voltage value V (3) of the node connected to the gate of the precharging Pch transistor Tr2 is changed to the driving Nch transistor Q2 as shown in FIG. Drive PC
When the h-transistor Q1 is inactivated, the logic value becomes L.

As a result, the gates of the first-stage precharging Pch transistor Tr1 and the last-stage precharging Pch transistor Tr2 become the ground potential GND as shown in FIG.
Of the voltage value V (0) becomes the power supply potential Vcc. This is the precharge state.

In the boosting period, as shown in FIG.
The boost control signal V (CKB) changes to the logical value L, and the inverted signal V (ck) of the boost control signal V (CKB) changes to the logical value H.

The gate of the first-stage precharging Pch transistor Tr1 of the charging clamp means 20 has a power supply potential Vcc.
Is input and deactivated.

At this time, the driving N
Since the channel transistor Q2 is inactivated and, at the same time, the driving Pch transistor Q1 is activated, the gate potential V (3) of the precharging Pch transistor Tr2 also becomes the power supply potential Vcc, as shown in FIG. The final-stage precharge Pch transistor Tr2 is inactivated.

However, this is an instantaneous state, and the boost control signal V (CKB) is applied to the MOS capacitor Q3 of the charging clamp means 20.
, The capacitive coupling occurs in the MOS capacitor Q3, and as shown in FIG. 2, the potential of the voltage value V (0) of the boosted output signal 13 rises, When the voltage becomes equal to or higher than the power supply potential Vcc + the threshold voltage Vth (tr2) of the last-stage precharge Pch transistor Tr2, the last-stage precharge Pch transistor Tr2 is activated. As a result, the last-stage precharge Pch transistor Tr2 is activated. The potential V (2) at the node connected to the source (or the node connected to the drain of the precharging Pch transistor Tr1) starts to rise.

At this time, V (2) at the node connected to the source of the final-stage precharging Pch transistor Tr2 of the charging clamp means 20 (or the node connected to the drain of the precharging Pch transistor Tr1).
Satisfies the relationship of V (2) = [voltage value V (0) of boosted output signal 13−threshold voltage Vth (tr2) of Pch transistor Tr2 for final stage precharge] (relational expression 1).

For this reason, V (2) at the node connected to the source of the final-stage precharging Pch transistor Tr2 of the charging clamp means 20 (or the node connected to the drain of the precharging Pch transistor Tr1).
As shown in FIG. 2, the step-up operation of V (2) ≦ power supply potential Vcc is performed by the Pch transistor Tr1 for initial stage precharging.
The operation stops at + the threshold voltage Vth (tr1) of the first-stage precharge Pch transistor Tr1 (relational expression 2).

Using the relational expressions 1 and 2, the voltage value V (0) of the boosted output signal 13 of the charging clamp means 20 is V
(0) ≦ power supply potential Vcc + threshold voltage Vth (tr1) of first-stage precharge Pch transistor Tr1 + threshold voltage Vth (tr) of last-stage precharge Pch transistor Tr2
The relationship 2) holds.

That is, as shown in FIG. 2, the voltage value V (0) of the boosted output signal 13 in the charging clamp means 20 is precharged to the power supply potential Vcc during the non-boosted period, and at most during the boosted period. It will rise only up to Vcc + Vth (tr1) + Vth (tr2).

For example, taking writing to a memory element as an example, during a non-boosting period corresponding to non-writing to a memory element, a boost control signal V (CKB) is used as a clock signal corresponding to non-writing, and a driving signal is used. By activating the Nch transistor Q2 and inactivating the driving Pch transistor Q1 of the driving means 30, the first stage precharging Pch transistor Tr1 through the last stage precharging Pch transistor
Activating the channel transistor Trn and precharging the potential of the MOS capacitor Q3 to the power supply potential Vcc,
The boosted output signal 13 can be generated and supplied to the word line of the memory element.

Further, during the boosting period according to the writing to the memory element, the boosting control signal V (CKB) is used as a clock signal according to the writing, the driving Nch transistor Q2 is inactivated, and the driving Pch transistor Activate Q1 to activate Pch transistor Tr for first stage precharge
After inactivating the first Pch transistor Tr1 using the capacitive coupling of the MOS capacitor Q3.
All first stage precharge Pch transistors T except
r1 is activated and the bootstrap potential [Vcc + Vth (tr
1) + Vth (tr2)], the potential of the MOS capacitor Q3 can be clamped to generate the boosted output signal 13 and supply it to the word line of the memory element.

Next, based on the drawing, the second
An embodiment will be described.

FIG. 3 is a circuit diagram for explaining a second embodiment of the booster circuit 10. An embodiment of the invention will be described.

The same reference numerals are given to the same portions as those already described in the booster circuit 10 of the first embodiment and the boosting control method used in the booster circuit 10, and duplicate description will be omitted.

The booster circuit 10 of the second embodiment has a circuit configuration similar to that of the first embodiment, and connects precharge Pch transistors Tr3, Tr4 and Tr5 in three stages between the power supply potential Vcc and the boost node. Circuit configuration.

Pch transistor Tr3 for precharging
Is provided between the power supply potential Vcc and the precharging Pch transistor Tr4, and its gate is connected to the logic element NO.
It is connected to the output terminal of T32.

Pch transistor Tr4 for precharging
, A switch circuit 301 for controlling activation / inactivation is connected to the gate.

The first switch circuit 301 is a logic circuit for controlling activation / inactivation of the precharging Pch transistor Tr4 according to the potential V (6) of the drain of the precharging Pch transistor Tr3. It is also provided between the gate of the precharging Pch transistor Tr4 and the MOS capacitor Q3.

Similarly, a switch circuit 302 for controlling activation / inactivation is connected to the gate of the precharging Pch transistor Tr5.

The second switch circuit 302 is a logic circuit for controlling activation / inactivation of the precharging Pch transistor Tr5 in accordance with the potential V (7) of the drain of the precharging Pch transistor Tr4. It is also provided between the gate of the precharging Pch transistor Tr5 and the MOS capacitor Q3.

The booster circuit 10 having such a configuration sequentially charges the MOS capacitor Q3 connected to the precharging Pch transistors Tr3, Tr4, Tr5 using a boost control signal V (CKB) as a clock signal. Finally, it has a function of obtaining a boosted output signal 13 which is substantially an integral multiple of the power supply potential Vcc.

Specifically, the output potential V of the first switch circuit 301 is increased during the boosting period by the above-described clip function.
(4) rises to V (4) = power supply potential Vcc + threshold voltage Vth (tr4) of the precharging Pch transistor Tr4, and the output potential V (5) of the second switch circuit 302 becomes V (5 )
= Power supply potential Vcc + Pch transistor T for precharge
r4 threshold voltage value Vth (tr4) + Pch for precharge
It rises only to the threshold voltage value Vth (tr5) of the transistor Tr5.

Therefore, the potential V (0) of the boosting node P is
V (0) = power supply potential Vcc + threshold voltage Vth (tr3) of precharging Pch transistor Tr3 + threshold voltage Vth of precharging Pch transistor Tr4
It is limited to the rise to (tr4) + the threshold voltage value Vth (tr5) of the precharging Pch transistor Tr5.

Thus, the precharging Pch transistors Tr1,..., Trn are connected to the power supply potential Vcc-boost node P
By connecting them in series, the clipping operation of the maximum value of the boosted potential can be performed.

[0102]

According to the first aspect of the present invention, by providing such a precharge function, the power supply potential can be supplied to the capacitor during the precharge operation during the non-boosting period. As a result, there is an effect that the potential of the node during the precharge operation can be held at a potential higher than the threshold voltage of the capacitor.

By providing such a clamping function, there is an effect that the device can be prevented from being destroyed due to excessive boosting even during the high voltage boosting period.

According to the invention described in claim 2, according to claim 1
In addition to the effects described in (1), by providing such a clamping function in the charging clamp means, it is possible to prevent the destruction of the device due to excessive boosting even during the high voltage boosting period. It works.

As a result, for example, a booster circuit is used in a device in which the guaranteed value of the power supply potential is as wide as 1.5 to 3.6 V to perform battery driving, and the low power supply potential is designed as a target. Even in such a case, it is possible to avoid the occurrence of an over-boosted state on the high voltage side of the power supply potential, and it is possible to avoid a device breakdown due to such an over-boosted state.

According to the invention described in claim 3, according to claim 2
In addition to the effects described in (1), by providing such a precharge function in the charging clamp means, it becomes possible to supply the power supply potential to the capacitor during the precharge operation during the non-boosting period. This has the effect that the potential of the node during operation can be held at the power supply potential.

For example, a sufficient boosting operation can be performed even when a low power supply potential of about 1.5 to 2.0 V is used in accordance with technical requirements for miniaturization of a circuit and reduction of power consumption. It has the effect of becoming

According to the invention described in claim 4, according to claim 3,
In addition to the effects described in (1), using such a Pch transistor, the potential of the capacitor connected to the final-stage precharging Pch transistor is changed to the bootstrap potential.
By providing a function of clamping, the device can be prevented from being damaged due to excessive boosting even during the boosting period at a high voltage.

According to the invention described in claim 5, according to claim 3,
In addition to the effects described in
By providing a transistor in the charging clamp means,
There is an effect that the power supply potential can be supplied to the capacitor during the precharge operation in the non-boosting period.

For example, even when a low power supply potential of about 1.5 to 2.0 V is used, the power supply potential is supplied to the capacitor in accordance with technical requirements for circuit miniaturization and reduction in power consumption. As a result, a sufficient boosting operation can be performed.

According to the invention set forth in claim 5, according to claim 5,
In addition to the effects described in
By providing a transistor in the charging clamp means,
It is possible to avoid the occurrence of an over-boosted state on the high voltage side of the power supply potential, and to avoid the device destruction caused by such an over-boosted state.

According to the invention described in claim 7, according to claim 6,
The same effect as the effect described in (1) is obtained.

According to the invention of claim 8, according to claim 1,
In addition to the effects described in any one of (1) to (7), by providing such a driving unit, it becomes possible to execute a precharge operation and a clamp operation control of the charging clamp unit with a simple circuit configuration. In addition, there is an effect that a low-cost booster circuit capable of reducing the circuit scale can be realized.

According to the ninth aspect of the present invention, a first aspect is provided.
In addition to the effects described in any one of (1) to (8), by using a MOS capacitor suitable for an integrated circuit, the above-described precharge function is used to supply power to the MOS capacitor during a precharge operation in a non-boost period. There is an effect that the supply of the potential can be realized with a simple and compact circuit scale.

According to the tenth aspect of the present invention, the same effect as that of the first aspect is obtained.

According to the eleventh aspect, the same effect as the tenth aspect can be obtained.

According to the twelfth aspect, the same effect as the eleventh aspect can be obtained.

According to the thirteenth aspect, the same effect as the twelfth aspect can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining a first embodiment of a booster circuit of the present invention.

FIG. 2 is a timing chart for explaining a basic operation and a boost control method of the booster circuit of FIG. 1;

FIG. 3 is a circuit diagram illustrating a booster circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a booster circuit according to a first conventional example.

FIG. 5 is a circuit diagram for explaining a booster circuit of a second conventional example.

[Explanation of symbols]

Reference Signs List 10 booster circuit 13 booster output signal 20 charge clamp means 30 drive means GND ground potential P node (boost node) Q1 drive Pch transistor Q2 drive Nch transistor Q3 capacitor (MOS capacitor) Tr1, Tr2, Tr3, Tr4, Tr5,. , Trn Precharge transistor Tr1 First stage precharge transistor Tr2, Tr8, Trn Last stage precharge transistor V (0) Node potential (boost node) V (2) Drain side potential of first stage precharge transistor V (3 ) Gate potential of the final stage precharge transistor (drain potential of Q1) Vcc power supply potential Vth, Vth (tr1), Vth (tr2) Threshold voltage Vcc + Vth (tr1) + Vth (tr2) Bootstrap potential V (CK) Boost Inversion signal of control signal (clock signal) V (CKB) Boost control signal (clock signal )

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H02M 3/07 H01L 27/04 G

Claims (13)

[Claims] In a booster circuit for boosting a potential of a node in a circuit network to a bootstrap potential higher than a power supply potential, a potential of a capacitor connected to the node is precharged to a power supply potential during a non-boosting period. Along with the boost period,
Charge boosting means for boosting the capacitor potential and clamping the capacitor potential when the capacitor potential reaches the bootstrap potential to maintain the bootstrap potential and prevent over-boosting. And a booster circuit. 2. The charge clamping means has a plurality of stages of precharge transistors connected in series between a power supply and the node, and inputs a predetermined potential to the precharge transistors during the boosting period. The bootstrap potential determined by the sum of the threshold voltage of each of the precharging transistors and the power supply potential is clamped to the potential of the capacitor connected to the last-stage precharging transistor. The booster circuit according to claim 1, wherein 3. The charge clamping unit is configured to activate all precharge transistors and precharge the potential of the capacitor to a power supply potential during the non-boosting period. The booster circuit according to claim 2. 4. The precharging transistor is Pc
h charging transistor, wherein the charging clamp unit inputs a predetermined potential to the precharging transistor during the boosting period, and determines the sum by the threshold voltage of each precharging Pch transistor and the power supply potential. 4. The booster circuit according to claim 3, wherein the booster circuit is configured to clamp a potential of the capacitor connected to a pre-charging Pch transistor in a final stage to the bootstrap potential. 5. The charge clamping unit is configured to activate all the precharging Pch transistors to precharge the potential of the capacitor to a power supply potential during the non-boosting period. The booster circuit according to claim 4, wherein 6. The charging clamp means inputs a predetermined potential to the precharging transistor and inputs a predetermined potential to each gate of the precharging Pch transistor during the boosting period, and activates the precharging transistor. The booster circuit according to claim 5, wherein the booster circuit is configured to clamp a potential of the capacitor to the bootstrap potential. 7. The charge clamping unit according to claim 1, wherein during the non-boosting period, a predetermined potential is input to the gates of all precharging Pch transistors and activated to precharge the potential of the capacitor to a power supply potential. The booster circuit according to claim 6, wherein the booster circuit is configured. 8. A driving Pch transistor and a driving Nch transistor connected in series between the final stage precharge transistor and a ground potential, and a connection between the driving Pch transistor and the driving Nch transistor. The boosting circuit according to claim 1, further comprising a driving unit having a point connected to a gate of the last-stage precharge transistor. 9. The capacitor according to claim 1, wherein the capacitor is a MOS capacitor, and is connected between an input terminal of the first-stage precharge transistor and an output terminal of the last-stage precharge transistor. Item 9. The booster circuit according to any one of Items 1 to 8. 10. A boost control signal in a non-boost period,
By activating the driving Nch transistor and inactivating the driving Pch transistor, the first-stage precharge transistor to the last-stage precharge transistor in the charging clamp unit are activated, The boost control method for a boost circuit according to claim 1, wherein a boost output signal is generated by precharging a potential of the MOS capacitor to a power supply potential. 11. After inactivating the driving Nch transistor and activating the driving Pch transistor to inactivate the first stage precharging transistor in response to a boosting control signal during a boosting period, Activating all the first-stage precharge transistors except the first-stage precharge transistor using the capacitive coupling of the MOS capacitor, and clamping the potential of the MOS capacitor to the bootstrap potential to generate a boosted output signal; The boost control method according to claim 10, wherein: 12. During a non-boosting period corresponding to non-writing to a memory element, the boosting control signal is used as a clock signal corresponding to the non-writing to activate the driving Nch transistor and to activate the driving means. Driving Pch
By inactivating the transistors, the first-stage precharge Pch transistor to the last-stage precharge Pch transistor are activated, and
The boost control method according to claim 11, wherein the potential of the OS capacitor is precharged to a power supply potential, the boosted output signal is generated and supplied to a word line of the memory element. 13. A boosting period according to writing to a memory element, the boosting control signal is used as a clock signal corresponding to the writing, the driving Nch transistor is inactivated, and the driving Pch transistor is turned on. Activating the precharging transistor by using the capacitive coupling of the MOS capacitor, clamping the potential of the MOS capacitor to the bootstrap potential, generating the boosted output signal, and applying the boosted output signal to the word line of the memory element. The boosting control method according to claim 12, wherein the voltage is supplied.