KR100612940B1 - Memory device for adjusting data output timing - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device capable of adjusting data output timing by using a fuse in a DDR memory device. The present invention relates to a fuse block including a plurality of fuses, and an enable timing of an output enable signal according to whether a fuse is cut. And strobe clock generating means.

Fuse, DLL, OE, DDR, Strobe

Description

Memory device for adjusting data output timing             

1 is a block diagram illustrating a memory device according to the present invention;

FIG. 2 is a timing diagram showing the operation of the memory device shown in FIG. 1 when the DLL is turned on. FIG.

3A is a timing diagram illustrating an operation of a memory device illustrated in FIG. 1 in a state in which a fuse is not blown when a DLL is turned off.

FIG. 3B is a timing diagram illustrating an operation of the memory device shown in FIG. 1 in a fuse blown state when the DLL is turned off. FIG.

* Explanation of symbols for the main parts of the drawings

1: fuse block

2 strobe clock generator

3: output driver

RD: read commend

CL: CAS Latency

BL: Burst Length

OE: Output Enable

The present invention relates to a double data rate (DDR) memory device, and more particularly, to a memory device capable of adjusting data output timing by using a fuse in a DDR memory device.

In DDR (Double Data Rate) memory devices, the DQ and DQS are synchronized with a clock signal using a delay locked loop (DLL). In other words, in the DDR memory device, DLL on / off can be programmed through EMRS. When the DLL is on, data is output in synchronization with the clock signal without access time (tAC = 0ns) by the DLL clock signal. When the DLL is turned off, a clock signal that strobes data is strobe through the clock buffer, rather than using a DLL clock signal that is prepared in advance, and outputs a slower access time (tAC) than the clock signal.

In this case, when the DLL is turned off, data is output after the CL (CAS Latency) after the read command is input, but there is a problem that cannot be used in a specific system that strobes data one clock before the CL.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a memory device capable of widening a system application by adjusting data output timing according to whether a fuse is cut.

The memory device of the present invention for achieving the above technical problem,
A memory device for outputting data in synchronization with a clock buffer or a clock output from a clock synchronization device in accordance with the clock synchronization device on / off,
A fuse block including a plurality of fuses;
Strobe clock generation means for generating a data output strobe signal by adjusting the enable timing of the output enable signal input from the outside by the output signal of the fuse block according to whether the fuse is cut;
When the clock synchronous device is not used, the strobe clock generating means enables the output enable signal one clock faster than the CL (CAS Latency) when the fuse is cut, and from the clock buffer in the enable period. The data output strobe signal synchronized with the output clock is generated, and when the fuse is not cut, the output enable signal is enabled according to the CL (CAS Latency) and is output from the clock buffer in the enable period. And generating the data output strobe signal synchronized with a clock.
In addition, when the clock synchronization device is used, the strobe clock generating means enables the output enable signal according to the CL (CAS Latency) regardless of whether the fuse is cut or not and the clock in the enable period. And generating the data output strobe signal synchronized with the clock output from the synchronization device.

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Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily implement the present invention.

1 is a block diagram illustrating a memory device according to the present invention.

The memory device includes a fuse block 1, a strobe clock generator 2, and an output driver 3.

The fuse block 1 generates different logic values (highi or low) depending on whether the internal fuse is cut. In this case, the fuse may be made of poly or metal, or an electrical fuse may be used.

The strobe clock generator 2 varies an enable period (for example, a logic 'H' period) of the output enable signal OE according to the output of the fuse block 1 (i.e., whether the fuse is cut or not), As a result, the timings of the strobe signals RCLKDO and FCLKDO are differently provided to the output driver 3.
That is, the strobe clock generator 2 has a signal indicating DLL on / off information (DLL OFF), RCLK / FCLK signal provided from a clock buffer (not shown), and RCLKDLL / provided from a DLL (not shown) as in the related art. The FCLKDLL signal, the signal CL of the cascade latency information, the signal BL of the burst length information, and the output enable signal OE are received.
And, unlike the prior art, the fuse block 1 is provided with information on whether the fuse is cut.
As will be described in detail later with reference to the timing diagrams of FIGS. 2, 3A, and 3B, the strobe clock generator 2 of the present invention enables the output enable signal OE according to whether a fuse is cut when the DLL is not used. By varying the interval, the timings of the strobe signals RCLKDO and FCLKDO are differently provided to the output driver 3.
That is, the strobe clock generator 2 of the present invention adds a function for defining an enable period of the output enable signal OE to a conventional stove clock generator, and includes a DLLOFF signal (DLL on / off information) and a fuse. The enable section of the OE signal is set differently according to the output signal (information according to whether or not fuse cutting) of the block 1.

The output driver 3 outputs data to the output terminal DQ in synchronization with the strobe signals RCLKDO and FCLKDO.

As is well known, in a DDR memory device, DLL on / off can be programmed through EMRS. RCLK and FCLK are clock signals output from a clock buffer and used for DLL off. RCLKDLL and FCLKDLL are clock signals output from the DLL and are used when the DLL is turned on.

The OE is an output enable signal and is enabled after the read command RD is input. As described above, the strobe clock generator 2 is configured to adjust the enable interval of the input output enable signal OE. do. That is, when the DLL is turned on, the enable timing of the output enable signal OE is adjusted according to CL regardless of whether the fuse is cut, and when the DLL is turned off, the output enable signal OE is enabled according to whether the fuse is cut. Adjust the timing.
In particular, when the DLL is turned off, the output enable signal OE is enabled one clock faster than CL when the fuse is cut, and the data output strobe signal RCLK_DO / FCLK_DO is generated in synchronization with the signal RCLK / FCLK in the enable period. When the fuse is not cut, the output enable signal OE is enabled according to CL and the strobe signal RCLK_DO / FCLK_DO is generated in synchronization with the signal RCLKDLL / FCLKDLL in the enable period.

RCLKDO and FCLKDO are strobe signals of the output driver 3, and are well known to those skilled in the art (as in the prior art) in a section in which the output enable signal OE is enabled (for example, a section in which logic 'H' is enabled). Created by selecting either the RCLKDLL / FCLKDLL signal or the RCLK / FCLKDLL signal.

BL denotes a burst length, and DLLOFF may be set to a logic 'high' level when the DLLRS is off when the state is determined at EMRS.

FIG. 2 is a timing diagram illustrating an operation of the memory device illustrated in FIG. 1 when a DLL is turned on. When CL = 2 and BL = 4, that is, four data are continuously output two clocks after the read command RD is input.
Since the DLL is on, the output enable signal OE is enabled according to CL regardless of whether the fuse is cut (i.e., enabled two clocks after the input of the read command), and the output enable signal OE is In the enabled period, strobe signals RCLKDO and FCLKDO are generated in synchronization with clock signals RCLKDLL and FCLKDLL output from the DLL.

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Here, the strobe signals RCLKDO and FCLKDO are generated by RCLKDLL / FCLKDLL, which are DLL clocks, so that the output data is output in synchronization with the clock signal CLK. That is, there is no access time tAC at all.

FIG. 3A is a timing diagram illustrating an operation of the memory device shown in FIG. 1 in a state where a fuse is not blown when a DLL is turned off.

When the DLL is off and the fuse is not blown, the output enable signal OE is enabled according to CL (i.e., enabled two clocks after the read command is input).
Since the DLL is not used, the strobe signals RCLKDO and FCLKDO are generated in synchronization with the clock signals RCLK and FCLK output from the clock buffer in a section where the output enable signal OE is enabled and becomes a high level. Let's do it.

Here, since the strobe signals RCLKDO and FCLKDO are generated by the clock signals RCLK / FCLK output from the clock buffer, the output data is output after a predetermined time delay from the rising edge of the clock signal CLK. That is, there is an access time tAC.

FIG. 3B is a timing diagram illustrating an operation of the memory device shown in FIG. 1 when a fuse is blown when the DLL is turned off.

When the DLL is turned off, the output enable signal OE is enabled one clock before the CL when the fuse is blown. Since the DLL is not used, the strobe signals RCLKDO and FCLKDO are synchronized with the clock signals RCLK and FCLK output from the clock buffer in the interval of the output enable signal OE enabled one clock before CL. Generate.

Similarly, since the strobe signals RCLKDO and FCLKDO are generated by the clock signals RCLK / FCLK output from the clock buffer, the output data is output after a predetermined time delay from the rising edge of the clock signal CLK. That is, there is an access time tAC.
Because of the call, data is output after a predetermined time delay from the rising edge of the clock signal CLK. That is, there is an access time tAC.

According to the present invention described above, data timing can be set differently by adjusting timing of an internal signal using a fuse, and thus, the present invention can flexibly cope with system application.

Claims (5)

delete A memory device for outputting data in synchronization with a clock buffer or a clock output from a clock synchronization device in accordance with the clock synchronization device on / off, A fuse block including a plurality of fuses; Strobe clock generation means for generating a data output strobe signal by adjusting the enable timing of the output enable signal input from the outside by the output signal of the fuse block according to whether the fuse is cut; When the clock synchronization device is not used, the output enable signal is enabled one clock faster than the CL (CAS Latency) when the fuse is cut, and the clock synchronized with the clock output from the clock buffer in the enable period. And a data output strobe signal. The method of claim 2, When the clock synchronizing device is used, the strobe clock generating means enables the output enable signal according to CL (CAS Latency) regardless of whether the fuse is cut or not and outputs from the clock synchronizing device in the enable period. And generating the data output strobe signal synchronized with the clock. The method of claim 2, When the clock synchronous device is not used, the strobe clock generating means enables the output enable signal according to CL (CAS Latency) when the fuse is not cut, and is output from the clock buffer in the enable period. And generate the data output strobe signal synchronized with a clock. delete

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