KR100951669B1 - Circuit and method for generating output enable signal in semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: An output enable signal generation circuit and a method thereof are provided to vary the enable timing of an output enable signal by generating the output enable signal in response to a DLL(Delay Locked Loop) clock and CAS(Column Address Strobe) latency signal. CONSTITUTION: A source signal generator(10) generates a first source signal in response to a burst command, a read command, and an internal clock. An internal clock synchronization part(20) generates a clock synchronization signal by synchronizing the first source signal with the internal clock. An output enable timing control unit(30) selectively outputs the first source signal or the clock synchronization signal as the second source signal in response to the selection signal. An output enable signal generator receives the first source signal and the second source signal. The output enable signal generator(40) generates the output enable signal in response to a DLL clock and a CAS latency signal.

Description

Circuit and Method for Generating Output Enable Signal in Semiconductor Memory Apparatus

The present invention relates to a semiconductor memory device, and more particularly, to an output enable signal generation circuit and method of a semiconductor memory device.

In general, a semiconductor memory device outputs data in accordance with clock cycles according to CAS latency (Column Address Strobe Latency) based on a clock transmitted from a delay locked loop (DLL) circuit when outputting data. At this time, in order to buffer the output data, a process of setting a buffering section of the output data is required. In order to set the buffering section of the output data as described above, the semiconductor memory device includes an output enable signal generation circuit. The output enable signal generation circuit generates an output enable signal under the control of the CAS latency information and the DLL clock when a read command is input. The output enable signal generation circuit of a semiconductor memory device such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) uses a rising clock and a falling clock output from a DLL circuit, respectively, to enable a rising output enable signal and a falling output enable signal. The signal is generated and used for data output operation.

In general, a semiconductor memory device performs an operation of generating the DLL clock by using a DLL circuit, but under a special condition, a DLL off mode may be used. For example, the DLL off mode is used when the equipment for testing the semiconductor memory device operates at a relatively low frequency or when the power consumption of the semiconductor memory device needs to be drastically reduced.

In this manner, the semiconductor memory device enables the output enable signal after a predetermined delay time considering the CAS latency and the data access time tAC from the input timing of the read command, and outputs data in synchronization with this. However, semiconductor memory devices implementing the DLL off mode need to output data at different timings according to their external conditions. That is, at the request of the device receiving data from the semiconductor memory device, the data is output after the CAS latency and the delay time as much as the data access time based on the input timing of the read command, and 1 is the length of the CAS latency. There is a case where data is output after a delay time plus a data access time after subtraction.

As such, in order for the semiconductor memory device to adjust the output timing of the data, the enable timing of the output enable signal must be adjusted. However, the conventional semiconductor memory device cannot vary the enable timing of the output enable signal, and is designed to fix the enable timing of the output enable signal. Therefore, the output enable signal generation circuits have to be designed differently according to external conditions, and accordingly, there is a problem in that time and cost increase in producing a semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and there is a technical problem to provide an output enable signal generation circuit and method of a semiconductor memory device capable of varying an enable timing of an output enable signal.

In addition, another object of the present invention is to provide an output enable signal generation circuit and method for a semiconductor memory device which reduces production time and cost due to an increase in adaptability to external conditions.

The output enable signal generation circuit of a semiconductor memory device according to an embodiment of the present invention for achieving the above-described technical problem, the source signal generator for generating a first source signal in response to a burst command, a read command and an internal clock; ; An internal clock synchronizer configured to generate a clock synchronizing signal by synchronizing the first source signal with the internal clock; An output enable timing adjusting unit for selectively outputting the first source signal or the clock synchronizing signal as a second source signal in response to a selection signal; And an output enable signal generator configured to receive the first source signal and the second source signal and generate an output enable signal in response to a DLL clock and a CAS latency signal.

Also, a method of generating an output enable signal of a semiconductor memory device according to another embodiment of the present invention may include: a) generating a first source signal in response to a burst command, a read command, and an internal clock; b) delaying the first source signal in synchronization with the internal clock to generate a clock synchronization signal; c) when the first operation mode is set, delaying the clock synchronizing signal in synchronization with a DLL clock to generate an output enable signal; And d) generating the output enable signal by delaying the first output enable signal in synchronization with the DLL clock when a second operation mode is set.

The output enable signal generation circuit and method of the semiconductor memory device of the present invention create the effect that the enable timing of the output enable signal can be varied in accordance with the requirements of an external device.

In addition, the output enable signal generation circuit and method of the semiconductor memory device of the present invention create the effect of reducing the production time and cost due to the increase in adaptability to external conditions.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a configuration of an output enable signal generation circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

As illustrated, the output enable signal generation circuit of the semiconductor memory device generates a source signal that generates a first source signal src1 in response to a burst command blcmd, a read command rdcmd, and an internal clock clk_int. Generation unit 10; An internal clock synchronizer 20 generating a clock synchronizing signal syn by synchronizing the first source signal src1 with the internal clock clk_int; An output enable timing adjuster 30 for selectively outputting the first source signal src1 or the clock synchronizing signal syn as a second source signal src2 in response to a selection signal sel; And a rising output enable signal routing in response to the rising clock rclk, the falling clock fclk, and the CAS latency signal caslt in response to the first source signal src1 and the second source signal src2. And an output enable signal generator 40 for generating a polling output enable signal (fouten).

When the read command rdcmd is input, the source signal generator 10 generates the first source signal src1 enabled in synchronization with the internal clock clk_int. At this time, the enable period of the first source signal src1 is maintained as indicated by the burst command blcmd. Here, it is assumed that the enable period has two cycles of the internal clock clk_int. Shall be.

The internal clock synchronizer 20 delays the first source signal src1 in synchronization with the internal clock clk_int to generate the clock synchronizing signal syn. In this case, the clock synchronizing signal syn is implemented as a form delayed by one period of the internal clock clk_int than the first source signal src1.

The output enable timing adjustment unit 30 may output the clock synchronizing signal syn to the second source signal src2 when the selection signal sel is at a first level (eg, at a high level). ) And outputs the first source signal src1 as the second source signal src2 when the selection signal sel is at a second level (for example, a low level). . Here, the selection signal sel is a delay in which the rising output enable signal and the polling output enable signal fouten add a data access time to the length of CAS latency after the input of the read command rdcmd. Has a potential of the first level in a first operating mode that is enabled after a time, and the rising output enable signal and the polling output enable signal fouten after the input of the read command rdcmd It has a potential of the second level in the second mode of operation, which is enabled after a delay time subtracting one by the length of the CAS latency plus the data access time. The selection signal sel may be easily implemented using a test mode or a fuse option, or may be implemented using a mode register set.

The rising clock rclk and the falling clock fclk are clocks transmitted from a DLL circuit, which may be collectively referred to as a DLL clock. The CAS latency signal caslt is a signal indicating the length of a CAS latency preset in the semiconductor memory device.

The output enable signal generator 40 receives the first source signal src1 and the second source signal src2. In this case, when the semiconductor memory device performs a low speed operation by a low frequency clock, the output enable signal generator 40 uses the first source signal src1 to route the rising output enable signal. And the polling output enable signal (fouten), and when the semiconductor memory device performs a high speed operation by a high frequency clock, the output enable signal generator 40 may generate the second source signal src2. Generate the rising output enable signal (routen) and the polling output enable signal (fouten) using. Whether the semiconductor memory device performs a high speed operation or a low speed operation is determined by CAS latency information transmitted by the CAS latency signal caslt. That is, the output enable signal generator 40 determines that the high speed operation is performed when the CAS latency is greater than or equal to a predetermined length, and performs the operation according to the low speed operation when it is less than the predetermined length.

The output enable signal generator 40 alternately synchronizes and delays the first source signal src1 or the second source signal src2 with the falling clock fclk and the rising clock rclk. Do this. The output enable signal generator 40 performs the above-described delay operation by the length of CAS latency, and then extracts the rising output enable signal and the polling output enable signal from the delayed signals. To print.

As such, the output enable signal generation circuit of the semiconductor memory device according to the embodiment generates the clock synchronization signal syn by synchronizing the first source signal src1 with the internal clock clk_int. . The clock synchronizing signal syn is implemented as a form delayed by one period of the internal clock clk_int than the first source signal src1. Thereafter, since the first source signal src1 or the clock synchronizing signal syn is selectively utilized as the second source signal src2 by controlling the selection signal sel, the second source signal src2 ) Enables the enable timing to vary by one period of the internal clock clk_int according to the state of the selection signal sel. As described above, since the enable timing of the second source signal src2 is variable, the enable timing of the rising output enable signal and the polling output enable signal can also be changed. Thus, by adjusting the output timing of the data according to the environment of the semiconductor memory device, it is possible to improve the adaptability to external conditions.

FIG. 2 is a detailed configuration diagram of the source signal generator shown in FIG. 1.

As illustrated, the source signal generation unit 10 may generate a section setting signal itvset in response to the burst command blcmd, the read command rdcmd, and the internal clock clk_int. 110; And a latch unit 120 for latching a potential generated by the interval setting signal itvset and the read command rdcmd to output the first source signal src1.

Here, the section setting unit 110, the first inverter (IV1) for receiving the burst command (blcmd); A second inverter IV2 receiving the read command rdcmd; And a NAND gate ND configured to receive the output signal of the first inverter IV1, the output signal of the second inverter IV2, and the internal clock clk_int, and output the interval setting signal itvset. do.

In addition, the latch unit 120 includes a first transistor in which the interval setting signal itvset is input to a gate terminal, an external supply power supply VDD is applied to a source terminal, and a drain terminal thereof is connected to a first node N1. (TR1); A second transistor TR2 having a read command (rdcmd) input to a gate terminal, a drain terminal connected to the first node N1, and a source terminal grounded; A third inverter IV3 receiving the potential of the first node N1 and outputting the first source signal src1; And a fourth inverter IV4 forming a latch structure with the third inverter IV3.

In the source signal generator 10 configured as described above, when the read command rdcmd is enabled in the form of a high pulse, the potential of the first node N1 of the latch unit 120 is low. Since the level becomes high, the first source signal src1 is enabled to a high level. The interval setting signal itvset has a low level when the potential of the burst command blcmd and the read command rdcmd is low and the potential of the internal clock clk_int is high. When the potential of the interval setting signal itvset becomes low, the first transistor TR1 of the latch unit 120 is turned on, so that the first node N1 has a high level potential. Hence, the first source signal src1 is disabled.

That is, the first source signal src1 is enabled in response to the input of the read command rdcmd, and is combined with the burst command blcmd, the read command rdcmd, and the internal clock clk_int. It is disabled by the interval setting signal itvset generated. The first source signal src1 has an enable period corresponding to a burst length transmitted by the burst command blcmd, and as mentioned above, here, the internal clock clk_int It is set to have two enable periods.

FIG. 3 is a detailed configuration diagram of the internal clock synchronization unit shown in FIG. 1.

As shown, the internal clock synchronization unit 20 includes: a fifth inverter IV5 receiving the internal clock clk_int; A first pass gate PG1 transferring the first source signal src1 to a second node N2 in response to an output signal of the fifth inverter IV5 and the internal clock clk_int; A sixth inverter IV6 receiving the potential of the second node N2; A seventh inverter IV7 forming a latch structure with the sixth inverter IV6; An eighth inverter IV8 that receives an output signal of the sixth inverter IV6; A second pass gate PG2 transferring an output signal of the eighth inverter IV8 to a third node N3 in response to an output signal of the fifth inverter IV5 and the internal clock clk_int; A ninth inverter IV9 receiving a potential of the third node N3; A tenth inverter IV10 forming a latch structure with the ninth inverter IV9; And an eleventh inverter IV11 that receives the output signal of the ninth inverter IV9 and outputs the clock synchronizing signal syn.

In this configuration, the clock synchronizing signal syn is implemented as a signal having a delay of one cycle of the internal clock clk_int by synchronizing the first source signal src1 with the internal clock clk_int. .

4 is a detailed configuration diagram of the output enable timing adjusting unit illustrated in FIG. 1.

As shown, the output enable timing adjuster 30 includes: a fourth node N4 for outputting the second source signal src2; A twelfth inverter IV12 receiving the selection signal sel; A third pass gate PG3 passing through the first source signal src1 to the fourth node N4 in response to the selection signal sel and an output signal of the twelfth inverter IV12; And a fourth pass gate PG4 passing through the clock synchronizing signal syn to the fourth node N4 in response to the selection signal sel and the output signal of the twelfth inverter IV12. Include.

By the configuration of the output enable timing adjusting unit 30 as described above, the clock synchronizing signal syn is the second source signal in the first operation mode, that is, when the potential of the selection signal sel is at a high level. The first source signal src1 is output as the second source signal src2 in the second operation mode, that is, when the potential of the selection signal sel is at the low level.

5A and 5B are timing diagrams for describing an operation of an output enable signal generation circuit of the semiconductor memory device shown in FIG. 1. FIG. 5A shows timings of signals in the first operation mode, and FIG. 5B. Denotes the timing of each signal in the second operation mode. It is assumed here that CAS latency is six.

Referring to FIG. 5A, after the read command rdcmd is input, the first source signal src1 is enabled in synchronization with the internal clock clk_int. The clock synchronizing signal syn is implemented as a form delayed by one period of the internal clock clk_int compared to the first source signal src1.

In general, when the CAS latency is 6 in a semiconductor memory device, it is determined that a high speed operation using a high frequency clock is performed. In addition, since the selection signal sel has a high level potential in the first operation mode, the clock synchronizing signal syn is utilized as the second source signal src2. Accordingly, the output enable signal generator 40 alternately delays the second source signal src2 in synchronization with the falling clock fclk and the rising clock rclk, and performs the above operation six times. Outputs the signal obtained by the signal as the rising output enable signal (routen) and delays the rising output enable signal (routen) once more in synchronization with the polling clock (fclk). Output as a foul.

Referring to FIG. 5B, since the potential of the selection signal sel is at a low level in the second operation mode, the first source signal src1 is used as the second source signal src2. The output enable signal generation unit 40 alternately delays the second source signal src2 having this type of timing in synchronization with the falling clock fclk and the rising clock rclk. Outputs the signal obtained by six times as the rising output enable signal (routen) and delays the rising output enable signal (routen) once more in synchronization with the polling clock (fclk). Output as a polling output enable signal (fouten).

As described above, the output enable signal generation circuit of the semiconductor memory device of the present invention controls the potential of the selection signal in accordance with an operation mode set according to a request of an external condition, and uses the enable signal of the second source signal. By adjusting the timing, the enable timing of the output enable signal can be varied. As described above, the present invention makes it possible to vary the enable timing of the output enable signal in accordance with the requirements of an external device, and as a result, the semiconductor memory device can effectively adapt to external conditions without a separate design change. It is possible to reduce the loss of time and money in the production of.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram showing a configuration of an output enable signal generation circuit of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a detailed configuration diagram of the source signal generator shown in FIG. 1;

3 is a detailed configuration diagram of an internal clock synchronizer illustrated in FIG. 1;

4 is a detailed configuration diagram of an output enable timing adjustment unit illustrated in FIG. 1;

5A and 5B are timing diagrams for describing an operation of an output enable signal generation circuit of the semiconductor memory device shown in FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: source signal generation unit 20: internal clock synchronization unit

30: output enable timing adjusting unit 40: output enable signal generating unit

Claims (13)

A source signal generator configured to generate a first source signal in response to a burst command, a read command, and an internal clock; An internal clock synchronizer configured to generate a clock synchronizing signal by synchronizing the first source signal with the internal clock; An output enable timing adjusting unit for selectively outputting the first source signal or the clock synchronizing signal as a second source signal in response to a selection signal; And An output enable signal generator configured to receive the first source signal and the second source signal and generate an output enable signal in response to a DLL clock and a CAS latency signal; Output enable signal generation circuit of a semiconductor memory device comprising a. The method of claim 1, The source signal generator is configured to enable the first source signal in synchronization with the internal clock when the read command is input, and to maintain the enable period of the first source signal as indicated by the burst command. An output enable signal generation circuit of a semiconductor memory device. The method according to claim 1 or 2, The source signal generator, An interval setting unit configured to generate an interval setting signal in response to the burst command, the read command, and the internal clock; And A latch unit for latching a potential generated by the interval setting signal and the read command to output the first source signal; And an output enable signal generation circuit of the semiconductor memory device. The method of claim 1, And the internal clock synchronizing unit is configured to delay the first source signal by one period of the internal clock to generate the clock synchronizing signal. The method of claim 1, And the selection signal is a signal implemented by using a test mode or a fuse option or a mode register set. The method of claim 5, The output enable timing adjustment unit outputs the clock synchronization signal as the second source signal when the selection signal is at the first level, and outputs the first source signal when the selection signal is at the second level. And an output enable signal generation circuit of the semiconductor memory device, configured to output as a source signal. The method of claim 1, The output enable signal generator determines whether a high speed operation or a low speed operation is performed by using the CAS latency signal, generates the output enable signal by using the first source signal during a low speed operation, and generates the first enable signal when the high speed operation is performed. And outputting the output enable signal using two source signals. The method of claim 7, wherein Wherein the output enable signal generator is configured to delay the first source signal or the second source signal by a length of a CAS latency in synchronization with the DLL clock to generate the output enable signal. Output enable signal generation circuit. a) generating a first source signal in response to a burst command, a read command and an internal clock; b) delaying the first source signal in synchronization with the internal clock to generate a clock synchronization signal; c) when the first operation mode is set, delaying the clock synchronizing signal in synchronization with a DLL clock to generate an output enable signal; And d) if the second mode of operation is set, delaying the first output enable signal in synchronization with the DLL clock to generate the output enable signal; An output enable signal generation method of a semiconductor memory device comprising a. The method of claim 9, In the step a), when the read command is input, the first source signal is enabled in synchronization with the internal clock, and the enable period of the first source signal is maintained as indicated by the burst command. A method of generating an output enable signal of a semiconductor memory device. The method of claim 9, And b) generating the clock synchronizing signal by delaying the first source signal by one period of the internal clock. The method of claim 9, The first operation mode and the second operation mode are set by output timing of data according to a request of an external device, and in accordance with a potential level of a selection signal generated by using a test mode or a fuse option or a mode register set. And determining an output enable signal of the semiconductor memory device. The method of claim 9, The step c) and the step d) is a step of generating the output enable signal by delaying the clock synchronizing signal or the first source signal by a length of CAS latency in synchronization with the DLL clock. A method of generating an output enable signal of a memory device.

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