KR100612653B1 - Apparatus and method of dual-clock selecting for wireless communication system - Google Patents

Abstract

The present invention discloses an apparatus and method for selecting a redundant clock in a wireless communication system.

The present invention compares a first clock with a reference clock provided by the wireless communication system to determine whether there is an abnormality, and if an abnormality is determined in the first clock, a first clock monitor unit for outputting an interrupt signal and a second clock; A second clock monitor unit which determines whether there is an error is compared with a reference clock provided by the wireless communication system and outputs an interrupt signal when an abnormality is determined in the second clock, and the first clock and the second clock are the main clocks. And a preliminary clock to provide a main clock to the wireless communication system. The main clock and the preliminary clock are switched by an interrupt signal output from the first clock monitor unit or the second clock monitor unit. By configuring the clock control unit to perform initialization, it maintains stable board operation by fast switching on the input of the redundant clock, and maintains the main clock. If the condition can be improved if the secondary clock all over again, and to transfer, to the redundancy of the two clocks, take appropriate measures for error conditions.

Redundant Clock, Interrupt, Clock Alternate

Description

Apparatus and method of dual-clock selecting for wireless communication system

1 is a block diagram illustrating a configuration of clock duplication of a control station of a wireless communication system according to an exemplary embodiment of the present invention.

Fig. 2 is a block diagram showing the structure of a line interface card in a control station having a clock duplication apparatus for a wireless communication system.

3 is a block diagram illustrating a structure of a redundant clock selection device of a wireless communication system according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating a structure of a clock monitor unit of FIG. 3 according to an exemplary embodiment of the present invention.

5 is a waveform diagram illustrating a clock monitor of FIG. 4 according to an exemplary embodiment of the present invention.

6 is a waveform diagram of an operation of a redundant clock selection device of a wireless communication system according to an exemplary embodiment of the present invention.

The present invention relates to an apparatus and method for selecting a redundant clock of a wireless communication system. Particularly, a redundant clock of a wireless communication system for fast switching to a redundant clock input and a stable operation of the wireless communication system through a simple circuit configuration is provided. A selection device and method are disclosed.

A device for providing a clock interface of a redundancy unit in a conventional system is disclosed in the Republic of Korea Patent Publication (10-2002-00673130 clock interface device of the redundancy unit in a synchronous transmission system) and switching of the clock generation unit in a synchronous transmission and multiplexing system The clock interface of the redundancy unit is proposed to prevent frame loss and bit error during hermetic operation.

However, the above-described technique has a problem in that it is impossible to effectively prepare for an error because there is no reporting function of an error to be generated at the time of switching or switching by configuring a clock redundant switching through hardware using a PLL (phase locked loop).

In order to solve the above problem, the present invention maintains stable board operation by fast switching to the input of the redundant clock, and when the state of the main clock improves, switches back to the auxiliary clock, and the abnormality of both the redundant clocks It is an object of the present invention to provide an apparatus and method for selecting a redundant clock of a wireless communication system that can properly take action for an error situation.

An apparatus for selecting a redundant clock in a wireless communication system according to a feature of the present invention,

A redundant clock selection device for selecting a redundant clock provided to a wireless communication system, the abnormality of the upper level and lower level of the first clock is determined based on the reference clock, and outputs the result of the determination as an interrupt signal. A first clock monitor; A second clock monitor unit which determines whether an upper level and a lower level of the second clock are abnormal based on a reference clock, and outputs a result of the determination as an interrupt signal; And defining a first clock and a second clock as a main clock and a preliminary clock to provide a main clock to the wireless communication system, and the main clock by an interrupt signal output from the first clock monitor or the second clock monitor. And a clock control unit which alternates the preliminary clock, performs initialization to a clock in which an abnormality occurs, and generates a specific interrupt when both the main clock and the preliminary clock occur.
The redundant clock selection method of the wireless communication system according to an aspect of the present invention,

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A redundant clock selection method for selecting a redundant clock provided in a wireless communication system, the method comprising: (a) setting a first clock, which is a dual inputted main clock, and a second clock, which is a preliminary clock; Providing to a communication system; (b) determining whether there is an abnormality between upper and lower levels of the first and second clocks based on a reference clock, and when an abnormality of the first clock is detected and the second clock is normal according to the determination, Switching a second clock to a main clock and waiting for a first clock initialization signal from the wireless communication system; And (c) restoring the first clock to a main clock and setting the second clock to a preliminary signal by a first clock initialization signal received from the wireless communication system.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the accompanying drawings, parts irrelevant to the description of the present invention are omitted in order to clearly describe the present invention, and the same or similar parts are denoted by the same reference numerals.

The clock duplication of the control station of the general wireless communication system is configured as follows.

1 is a block diagram illustrating a configuration of clock duplication of a control station of a wireless communication system according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a redundant clock board 100 of a control station of a general ATM (Asynchronous Transfer Mode) based wireless communication system includes a remote access server-terminal (RAS-T) 110 and an ATM switch unit (ASU) ( 120), RAS-N (Remote Access Server-Network) 130, RAS-Node B (RAS-B) 140, RAS-CN (RAS-Core Network) 150, and Clock Generation System (CGS) ( 160).

The control station transmits and receives a cell through an interface between a run time system (RTS) 170 and a core network (CN) 180.

In this case, the RAS-T 110 includes a plurality of traffic handing units (THUs) 111 and a first ATM switch interface unit (AIU) 112, and the RAS-N 130 includes a second AIU 121. ), An ATM switch processor (ASP) 132, and an ATM switch control processor unit (ACP) 133.

The RAS-B 140 also includes a Line Interface Unit-Node B (LIU-B) 141 and a third AIU 142, and the RAS-CN 150 includes a fourth AIU 151 and a LIU-N. (Line Interface Unite-Core Network) 152.

The CGS 160 includes a CDU-A (Clock Data Unit-Node A) 161, a CDU-B (Node B) 162, a CGU-A (Clock Generation Unit-Node A) 163, and a CGU- Node B (164).

The THU 111 of the RAS-T 110 coordinates the cells of the traffic ATM, and the first AIU 112, the second AIU 131, the third AIU 142 and the fourth AIU 151 It serves as the interface between each board and the ATM switch.

In addition, the ASP 132 and the ACP 133 are parts for controlling the entire redundant clock board 100 of the control station, and the LIU-B 141 and the LIU-N 152 are respectively the RTS 170 and the RTS 170. Serves as a line interface with the CN 180.

The CGU-A 163 and the CGU-B 164 generate a clock for providing a synchronous clock of each board, and the CGU-A 163 uses a clock supplied from the CN 180 as a main clock. The CGU-B 164 switches to the sub-clock of the CGU-1 163 and performs a clock supply when there is an error in the main clock.

The clocks generated by CGU-A 163 and CGU-B 164 are provided to each board by CDU-A 161 and CDU-B 162, respectively.

In the wireless communication system having the above structure, both the control station and the base station operate in a reception-dependent method of restoring a clock from an upper network. And the clock supply of each functional board in the control station is received by the CGUs 163 and 164.

At this time, the clock supplied to each board is duplexed and composed of the CGU-A 163 and the CGU-B 164, and the CGU-A 163 as the main clock and the sub-clock CGU-B 164 are set.

If the state of the main clock goes bad, it is necessary to quickly switch to the sub-clock to maintain stable board operation. When the state of the main clock improves, the sub-clock should be prepared by converting the state from the sub-clock to the main clock again.

The line interface board LIU-B or LIU-N of the control station to which the clock duplexing device having the above structure is applied is as follows.

Fig. 2 is a block diagram showing the structure of an interface card which is a line in a control station having a clock duplication apparatus of a wireless communication system.

Referring to FIG. 2, the line interface card 200 includes a function block 210, a CPU 220, a field-programmable gate array (FPGA) 230, and an oscillator (OSC) 240.

The function block 210 is a block for performing an external interface function, which is a function unique to the line interface card 200, and the FPGA 230 uses a programmable device as a device for selecting a redundant clock. The level can be easily changed by program.

The OSC 240 is an oscillator for a clock provided by the line interface card 200 itself, and the CPU 220 manages and controls the entire line interface card 200.

The FPGA 230 of the line interface card according to the embodiment of the present invention configured as shown in FIG. 2 receives two clocks (clock A and clock B) input from the outside and a clock generated by the OSC 240 as an input. While interfacing with the CPU 220 is configured to receive a control on the situation that the abnormality occurs in the redundant clock.

The FPGA 230 will be described in more detail as follows.

3 is a block diagram illustrating a structure of a redundant clock selection device of a wireless communication system according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the redundant clock selecting apparatus 300 includes a clock monitor unit A 310, a clock monitor unit B 320, and a clock controller 330.

 The clock monitor A 310 compares the clock A input from the outside with the reference clock input from the board to determine whether the clock A is normal, and the clock monitor B 320 is the same as the clock monitor A 310. It is configured and determines whether clock B is normal.

The clock controller 330 selects one of the clock A and the clock B as the main clock or transfers the preliminary clock to the main clock according to the clock state signals input from the clock monitor A 310 and the clock monitor B 3020. In charge of the function.

The clock monitor unit A 310 and the clock monitor unit B 320 have the same structure as described above, and the detailed structure is as follows.

4 is a block diagram illustrating a structure of a clock monitor unit of FIG. 3 according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the clock monitor 400 may include an inverter 410, a first counter 420, a second counter 430, and a first comparator corresponding to an abnormality determining unit for determining an abnormality of a clock. 440, a second comparator 450, an OR gate 460, and a D-flip flip (DFF) 470 for outputting an interrupt signal according to whether there is an error.

The inverter 410 reversely outputs a comparison clock (clock A or clock B) to be compared to the first counter 420, and the comparison clock is input to the second counter 430 as it is. That is, the first counter 420 and the second counter 430 respectively receive opposite reference clocks.

The first counter 420 and the second counter 430 operate by the reference clock, operate by the reference clock, and operate only when the counter maintains the upper level of the input comparison clock and is initialized according to the initialization signal.

In addition, the first counter 420 may be initialized when the comparison clock is at the upper level (= 1), and the second counter 430 may be initialized when the comparison clock is at the lower level (= 0).

The first comparator 440 compares the counter value output from the first counter 420 with the reference counter value, and the second comparator 460 compares the counter value output from the second counter 430 and the reference counter value. Compare.

The OR gate 460 takes an OR value with respect to the output values of the first comparator 440 and the second comparator 460, and inputs the same to the DFF 470.

The DFF 470 is an interrupt signal output unit that outputs an interrupt signal for notifying a clock error according to an input signal.

The clock monitor having the above structure will be described in more detail as follows.

The first comparator 440 compares the reference counter value with the output value of the first counter 420 to output '1' if the first counter value is greater than the reference counter value.

That is, if the reference clock is 1Mhz and the comparison clock is lower than 10 Khz, the reference clock oscillates 10 times during one period of the comparison clock, and the reference counter can be defined as 10 or less. If an error occurs at an upper level of the input comparison clock, the upper level is increased so that a value greater than the reference counter value is generated in the first counter 420, so that the output value of the first comparator 440 becomes '1'.

In addition, when an error occurs at a lower level of the comparison clock, the output value is divided by '1' by the second counter 430 and the second comparator 460.

Therefore, the OR gate 450 ORing the values of the first comparator 440 and the second comparator 460 indicate all errors at the upper or lower level of the comparison clock, thereby causing an abnormality through the DFF 470. The alert may output an interrupt signal.

5 is a waveform diagram of a clock monitor of FIG. 4 according to an embodiment of the present invention, and FIG. 6 is a waveform diagram of an operation of a redundant clock selection device of a wireless communication system according to an embodiment of the present invention.

Referring to FIG. 5, when the error occurs due to the disappearance of the upper portion of the input clock in the 'ga' portion of the waveform diagram, it can be seen that the value generated by the first counter 420 becomes larger than the set reference counter value. If you enter a value, an output interrupt occurs.

When the initialization signal is input in the error state, all the states are initialized.

In response to the error, the clock control unit 330 of FIG. 3 observes the main clock of the input clock and selects the other one as a preliminary clock to output only the main clock.

That is, when the main clock is the clock A and the preliminary clock is the clock B in the dual clocks of the original clock A and the clock B, the clock controller 330 outputs the clock A in a normal state.

However, when the clock monitor A 310 outputs an interrupt signal, the clock controller 330 alternates the main clock and the preliminary clock to output the clock B with the clock B as the main clock and the clock A as the preliminary clock, and the CPU Wait for an initialization signal from 220.

When the initialization signal is received from the CPU 220, the clock A is set as the main clock and the clock B is set as the preliminary clock to output the clock A.

Referring to FIG. 6, when an initial main clock becomes a clock A and a preliminary clock becomes a clock B, when an error of the main clock is reported, the clock B is replaced with the main clock so that there is no clock error input to the system. When clock A is initialized by the CPU, clock A is activated again as the main clock.

In addition, when the clock A and the clock B fail simultaneously, each clock can be initialized by initialization of a CPU.

Although a preferred embodiment of the present invention has been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

As described above, in the redundant clock selection apparatus and method of the wireless communication system according to the present invention, the redundant clock of the wireless communication system can be switched to a preliminary clock due to an abnormality of the main clock with a simple hardware configuration. Programmable levels provide flexibility in the implementation and operation of redundant clocks, enabling fast board switching for redundant clock inputs to maintain stable board operation. In case there is an error in both of the redundant clocks, there is an effect to properly take action on the error situation.

Claims (8)

A redundant clock selection device for selecting a redundant clock provided to a wireless communication system, A first clock monitor configured to determine whether an upper level and a lower level of the first clock are abnormal based on a reference clock, and output a result of the determination as an interrupt signal; A second clock monitor unit which determines whether an upper level and a lower level of the second clock are abnormal based on a reference clock, and outputs a result of the determination as an interrupt signal; And The first clock and the second clock are defined as a main clock and a preliminary clock to provide a main clock to the wireless communication system, and the main clock and the second clock are interrupted by an interrupt signal output by the first clock monitor or the second clock monitor. A clock control unit which transfers a spare clock, initializes a clock in which an error occurs, and generates a specific interrupt when both the main clock and the spare clock occur. Redundant clock selection device of a wireless communication system comprising a. The method of claim 1, The first clock monitor unit, A first counter for counting a higher level of the first clock input by a reference clock provided by the wireless communication system and outputting a result; A first comparator for comparing an output value of the first counter with a reference counter value when the first clock is normal and outputting a result; A second counter for counting a lower level of the input first clock by a reference clock provided by the wireless communication system and outputting a result; A second comparator comparing the output value of the second counter with a reference counter value when the first clock is normal and outputting a result; An OR gate that ORs the output values of the first comparator and the second comparator and outputs the result; And An interrupt signal output unit which receives the result of the abnormality determination unit and outputs the interrupt signal as an interrupt signal. Redundant clock selection device of a wireless communication system comprising a. delete The method of claim 1, The second clock monitor unit, A first counter for counting a higher level of an input second clock by a reference clock provided by the wireless communication system and outputting a result; A first comparator for comparing an output value of the first counter with a reference counter value when the second clock is normal and outputting a result; A second counter for counting a lower level of the input second clock by a reference clock provided by the wireless communication system and outputting a result; A second comparator for comparing the output value of the second counter with a reference counter value when the second clock is normal and outputting a result; An OR gate that ORs the output values of the first comparator and the second comparator and outputs the result; And An interrupt signal output unit which receives the result of the abnormality determination unit and outputs the interrupt signal as an interrupt signal. Redundant clock selection device of a wireless communication system comprising a. delete The method of claim 1, And the first clock monitor unit and the second clock monitor unit are initialized by an initialization signal of the wireless communication system. A redundant clock selection method for selecting a redundant clock provided to a wireless communication system, (a) setting a first clock which is a dual input main clock and a second clock which is a preliminary clock, and providing a first clock to the wireless communication system; (b) determining whether there is an abnormality between upper and lower levels of the first and second clocks based on a reference clock, and when an abnormality of the first clock is detected and the second clock is normal according to the determination, Switching a second clock to a main clock and waiting for a first clock initialization signal from the wireless communication system; And (c) restoring the first clock to a main clock and setting the second clock to a preliminary signal by a first clock initialization signal received from the wireless communication system; Redundant clock selection method of a wireless communication system comprising a. The method of claim 7, wherein In step (b), And if an abnormality of both the first clock and the second clock is detected, waiting for an initialization signal from the wireless communication system to initialize the first clock and the second clock.

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