KR100611249B1 - Graphic processing unit capable of reducing transaction into system bus - Google Patents

Abstract

The graphics processing unit is disclosed. The graphics processing unit according to the present invention is a graphics processing unit that processes bitmap graphics on a bit-by-bit basis, and includes a destination read block controller for reading a destination read bitmap image from a system memory through a system bus, and a destination read. GPU cores for performing logical operations on the destination read bitmap image read by the block controller, a buffer for storing data of the destination address until processing of one band by the GPU cores, and a GPU core. The destination write block controller writes data of the destination address stored in the buffer to the system memory through the system bus when the processing of one band is completed.

GPU, Bitmap, Destination Bitmap, System Bus, Transaction

Description

Graphic processing unit capable of reducing transaction into system bus}

1 is a block diagram schematically showing a graphics processing unit according to the prior art;

2 is a block diagram schematically showing a graphics processing unit according to the invention, and

3 is a flowchart illustrating a graphic processing method by the graphic processing unit of FIG. 2.

Explanation of symbols on the main parts of the drawings

10, 120: graphics processing unit 11, 123: GPU core

13: source block controller 14: source memory interface

15: pattern block controller 16: pattern memory interface

17a, 126: Destination Write Block Controller

18a, 127: destination write memory interface

17b, 121: Destination Read Block Controller

18b: Destination Read Memory Interface

19: Other Block Controller 19a: Other Memory Interface

20: CPU 30: VPU

40: memory controller 45: system memory

The present invention relates to a graphics processing unit of a printer, and more particularly, to a graphics processing unit of a printer that can improve the overall performance by reducing transactions to the system bus.

In general, the GPU (Graphic Processing Unit) block of a printing SoC system is a graphics processor that performs bitmap operations, and handles bitmap graphics bit by bit only by performing bitwise operations, which are weak points of general-purpose processors. . Such graphics processors use a unique instruction called a symbolic command, which stores bitmaps in bits in memory for printing.

The resources for bitmap operations include source bitmap, pattern bitmap, and destination bitmap. Using these three bitmaps, 256 Boolean logic operations ( Boolean operation). Such operations are commonly referred to as 'Bit Block Transfer' and may also be called 'bitBLT'.

1 is a block diagram schematically showing a graphic processing unit according to the prior art. Referring to the drawings, the graphic processing unit 10 is connected to the CPU 20, the video processing unit (VPU) 30, and the memory controller 40 through a system bus.

In this case, the graphic processing unit 10 provides the requested data in response to the GPU core 11, the source bitmap image, the destination bitmap image, and the pattern bitmap image data request from the GPU core 11. Each controller 13, 15, 17a, 17b and a memory interface 14, 16, 18a, 18b corresponding to each controller 13, 15, 17a, 17b are provided. The destination block has controllers 17a and 17b and memory interfaces 18a and 18b for write and read operations, respectively. In addition, the graphic processing unit 10 includes various other logics 19 and 19a, but the description thereof is omitted since it is not related to the present invention.

The GPU core 11 stores the source bitmap image, the destination read bitmap image, and the pattern bitmap image data through the controllers 13, 15, and 17b and the memory interfaces 14, 16, and 18b, respectively. 45), then process the data. The processed result is written back to the system memory 45 through the destination write controller 17a and the destination write memory interface 18a.

The basic operation of the GPU block is based on reading these bitmap images, performing operations by logical operation on these data, and modifying them to record the result at the destination address. do. As a result, reading and writing multiple bitmap image data requires a lot of memory access, resulting in many transactions on the system bus. In particular, since the graphic processing unit 10 according to the prior art has to continuously read the source bitmap image, the pattern bitmap image, the destination read bitmap image in order to perform the logical operation, a large number of reads are made on the system bus. It will request a / write transaction. This may cause the performance of the system bus of the SoC system to degrade.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a graphic processing unit that can improve the performance of the SoC system as a whole by reducing the number of transactions occurring in the SoC system.

In order to achieve the above object, the graphics processing unit according to the present invention, in the graphics processing unit for processing bitmap graphics bit by bit, destination for reading a destination read bitmap image from the system memory through a system bus A read block controller, a GPU core for performing logical operations on the destination read bitmap image read by the destination read block controller, and data of a destination address until processing of one band by the GPU core is completed. And a destination write block controller that writes data of the destination address stored in the buffer to the system memory through the system bus when processing of one band by the GPU core is completed. It features.

Advantageously, said graphics processing unit further comprises a first register for storing a destination address of said destination read bitmap image read by said destination read block controller.

Preferably, the graphic processing unit stores a value of "1" when the type of emulator used is PCL6, and further adds a second register which stores a value of "0" when another type of emulator is used. Include.

In this case, when the execution of a new logic operation starts, the GPU core may set the buffer to "1" or clear to "0" according to a value indicating the type of emulator stored in the second register. In addition, the buffer is preferably implemented as SRAM (Static RAM).

As a result, the graphic processing unit according to the present invention stores the destination bitmap image data repeatedly used until the processing of one band is completed in the SRAM in the GPU, thereby reducing the read / write transaction to the system bus. SoC system performance can be improved.

Hereinafter, a graphic processing unit according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a graphics processing unit according to the present invention. Referring to the drawings, the graphics processing unit 120 includes a destination read block controller 121, a GPU core 123, a buffer 125, a destination write block controller 126, a destination write memory interface 127, And a first register (SFR0: Special Function Register 0) 128a, and a second register (SFR1) 128b. 2 illustrates a destination read block controller 121, a GPU core 123, a buffer 125, a destination write block controller 126, a destination write memory interface 127, and a first block in the graphic processing unit 120. Although only the register (SFR0: Special Function Register 0) 128a and the second register (SFR1) 128b are shown, the graphic processing unit 120 according to the present invention also includes the source block controller 13, the source shown in FIG. The memory interface 14, the pattern block controller 15, the pattern memory interface 16, the other block controller 19, and the other memory interface 19a are provided. However, since their configuration and function are the same as the conventional ones, these are omitted in order to simplify the drawings.

The destination read block controller 121 reads the destination read bitmap image from the system memory 45 through the system bus. At this time, the memory controller 40 disposed between the system bus and the system memory 45 controls data transmission and reception between the system memory 45 and the system bus.

The GPU core 123 performs a logical operation on the destination read bitmap image read by the destination read block controller 121.

When sending data from a host (not shown) such as a personal computer (PC) to a printer, the printer is exported in a form that can be interpreted by a printer such as PCL (Printer Command Language), Postscript, GDI, etc. ), Resolution, and pixel depth of the pixel are transmitted. The printer receives this information and converts it to data for printing in bitmap format.

Here, the bitmap form is a method of expressing the value of each pixel in black or white (that is, '0' or '1'). Converts the transmitted data to a mono image in gray format (the method of expressing the brightness value of each pixel as a 8-bit data, for example, in the level of 0 to 255). In order to print it out, you need to convert the gray format to bitmap format. Therefore, there must be a halftoning process that converts 256 levels of values from 0 to 255 to 0 or 1.

On the other hand, in order to print a user-created document to a printer, a printer and a printer driver must be provided. An important point is that the printer and the printer driver must have the same emulation. For example, a driver must be provided that can generate the same commands based on printer emulation, such as PCL6, PCL5e, Postscript, GDI, and so on. In other words, a PostScript printer driver must be provided for printers with PostScript emulation.

The buffer 125 stores the data of the destination address until the processing of one band by the GPU core 123 is completed. That is, when reprocessing of data of the destination address is required in one band, the conventional technology stores the data in the system memory 45, so that many transactions are required on the system bus whenever reprocessing is required. By storing data in the buffer 125 inside the graphics processing unit 120 instead of 45, transactions to the system bus can be reduced. Here, the buffer 125 is preferably implemented with SRAM (Static RAM) used as a flip-flop memory device. The size of the SRAM is about 79360 bytes (assuming that one band is 4960 x 128 lines) that can store all one band bitmap data. However, the size of the SRAM is not limited thereto and may be extended to a desired size later.

The destination write block controller 126 transfers the data of the destination address stored in the buffer 125 through the destination write memory interface 127 and the system bus when the processing of one band is completed by the GPU core 123. Write to system memory 45.

The first register 128a stores the destination address of the destination read bitmap image read by the destination read block controller 121. The second register 128b stores a value of "1" when the type of emulator used is PCL6, and a value of "0" when another type of emulator is used. Here, the first register and the second register is preferably implemented in a size of 32 bits.

3 is a flowchart illustrating a graphic processing method by the graphic processing unit of FIG. 2. Referring to the drawing, when the graphic processing for one band is completed, the GPU 123 sets bit 0 stored in the first register 128a (S101) and idles until a new band starts. It becomes

When a new band is started (S103), the GPU 123 clears or sets the SRAM 125. To this end, when a new band is started (S103), the GPU 123 checks the second register 128b to determine the type of emulator. At this time, when the type of emulator determined by the GPU 123 is PCL6 (S105), the GPU 123 sets the SRAM 125 to "1" (S107), and the type of the emulator determined is other than PCL6. If so, the GPU 123 clears the SRAM 125 to "0" (S109).

After clearing or setting the SRAM 125 is complete, the SRAM 125 can be read to the destination read block controller 121 and the destination write block controller 126 until the GPU 123 processes all the bands. In response, data of the destination address is stored (S111). In other words, data is not transferred to the system bus until processing of one band by the GPU 123 is completed.

When the processing of one band is completed by the GPU 123 (S113), the GPU 123 transmits a signal to the SRAM 125 that the processing of one band is completed, and the SRAM 125 transmits the signal by the transmitted signal. The data stored up to that point is written back, i.e., stored in the area of the system memory 45 corresponding to its size starting from the destination address stored in the first register 128a (S115).

After all writeback to the system memory 45 by the SRAM 125 is complete, the GPU 123 sets the bits in the first register to zero and is idle again until a new band begins.

According to the present invention, the graphics processing unit stores the destination bitmap image data, which is repeatedly reused until the graphics processing for one band is completed, in the SRAM in the GPU, and until the graphics processing for one band is completed. By not generating transactions on the bus, the overall system bus transaction can be reduced, resulting in improved performance of the SoC system.                     

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the present invention is not limited to the specific embodiments of the present invention without departing from the spirit of the present invention as claimed in the claims. Anyone skilled in the art can make various modifications, as well as such modifications are within the scope of the claims.

Claims (5)

A graphic processing unit for processing bitmap graphics in units of bits, A destination read block controller for reading a destination read bitmap image from system memory via a system bus; A GPU core configured to perform a logical operation on the destination read bitmap image read by the destination read block controller; A buffer for storing data of a destination address until the processing of one band by the GPU core is completed; And And a destination write block controller which writes data of the destination address stored in the buffer to the system memory through the system bus when the processing of one band is completed by the GPU core. . The method of claim 1, And a first register for storing a destination address of the destination read bitmap image read by the destination read block controller. The method of claim 2, And a second register storing a value of "1" when the type of emulator used is PCL6, and a value of "0" when another type of emulator is used. . The method of claim 3, wherein The GPU core sets the buffer to "1" or clears it to "0" according to a value indicating the type of emulator stored in the second register when a new logic operation is started. unit. The method of claim 1, And the buffer is implemented as static RAM (SRAM).

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