KR100609978B1 - Method for monitoring the critical dimension of contact hole of semiconductor device - Google Patents

Method for monitoring the critical dimension of contact hole of semiconductor device Download PDF

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KR100609978B1
KR100609978B1 KR1020040116531A KR20040116531A KR100609978B1 KR 100609978 B1 KR100609978 B1 KR 100609978B1 KR 1020040116531 A KR1020040116531 A KR 1020040116531A KR 20040116531 A KR20040116531 A KR 20040116531A KR 100609978 B1 KR100609978 B1 KR 100609978B1
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line width
contact hole
monitoring
semiconductor device
contact
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KR20060077623A (en
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김형석
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Automation & Control Theory (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 반도체 소자의 콘택 홀 선폭 모니터링 방법에 관한 것으로, 보다 자세하게는 콘택 모트 선폭 키에 STI(Shallow Trench Isolation)를 삽입하여 실제 셀(Cell) 지역과 동일한 조건 아래 평면에서 콘택 홀 선폭(Critical Dimension)을 측정하는 것을 특징으로 하는 콘택 홀 선폭 모니터링(Monitoring) 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for monitoring contact hole line width of a semiconductor device. More specifically, the contact hole line width (Critical Dimension) in a plane under the same conditions as a real cell region by inserting a shallow trench isolation (STI) into the contact mote line width key ) Is a contact hole line width monitoring method.

따라서, 본 발명의 반도체 소자의 콘택 홀 선폭 모니터링 방법은 콘택 모트(Contact Moat) 선폭 키(Key)에 STI 층을 삽입하여 선폭을 실제 셀(Cell) 지역과 동일한 조건에서 측정함으로써, 포토(Photo) 및 식각(Etch) 장비 변화 및 문제점을 양산시 조기에 발견할 수 있는 효과가 있다.Accordingly, the method for monitoring the contact hole line width of the semiconductor device of the present invention inserts an STI layer into the contact moat line width key and measures the line width under the same conditions as the actual cell region, thereby providing a photo. And etching (Etch) has the effect of early detection of changes and problems in mass production.

선폭, 모트, STI, 모니터링Linewidth, Mort, STI, Monitoring

Description

반도체 소자의 콘택 홀 선폭 모니터링 방법{Method for monitoring the critical dimension of contact hole of semiconductor device} Method for monitoring the critical dimension of contact hole of semiconductor device             

도 1은 종래기술에 의한 반도체 소자의 콘택 홀 제조 방법을 나타낸 단면도.1 is a cross-sectional view showing a contact hole manufacturing method of a semiconductor device according to the prior art.

도 2a는 본 발명에 의한 반도체 소자의 콘택 홀 선폭 모니터링 방법을 나타낸 단면도.Figure 2a is a cross-sectional view showing a contact hole line width monitoring method of a semiconductor device according to the present invention.

도 2b는 본 발명에 의한 콘택 홀 스파이킹 현상을 검출한 사진.Figure 2b is a photograph of detecting the contact hole spiking phenomenon according to the present invention.

본 발명은 반도체 소자의 콘택 홀 선폭 모니터링 방법에 관한 것으로, 보다 자세하게는 콘택 모트(Contact Moat) 선폭(Critical Dimension) 키(Key)에 트렌치 소자 분리(Shallow Trench Isolation, 이하 STI)를 삽입하여 실제 셀(Cell) 지역과 동일한 조건 아래 평면에서 콘택 홀 선폭(Critical Dimension)을 측정하는 것을 특징으로 하는 콘택 홀 선폭 모니터링(Monitoring) 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for monitoring the contact hole line width of a semiconductor device, and more particularly, to insert a trench trench isolation (STI) into a contact moat critical dimension key. The contact hole line width monitoring method comprising measuring the contact hole line width in the plane under the same condition as the (Cell) area.

일반적으로 반도체 소자를 분리하는 방법으로는 선택적 산화법으로 질화막을 이용하는 실리콘의 국부적 산화(Local Oxidation Of Silicon, 이하 LOCOS) 소자 분리 방법이 이용되어 왔다. LOCOS 소자 분리 방법은 질화막을 마스크(Mask)로 해서 실리콘 웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 이점이 있다. 그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 소자의 미세화에 한계가 있을 뿐만 아니라 버즈 비크(Bird's Beak)가 발생하게 된다.In general, as a method of separating semiconductor devices, a method of separating a local oxide of silicon (LOCOS) device using a nitride film as a selective oxidation method has been used. Since the LOCOS device isolation method uses a nitride film as a mask to thermally oxidize the silicon wafer itself, there is an advantage that the process is simple, the device stress problem of the oxide film is small, and the resulting oxide film is good. However, when the LOCOS device isolation method is used, the device isolation region occupies a large area, thereby limiting the miniaturization of the device and generating a bird's beak.

이러한 단점을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 STI가 있다. STI에서는 실리콘웨이퍼에 트렌치를 만들어 산화막을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 소자의 미세화에 유리하다.To overcome this drawback, STI is an alternative to LOCOS device isolation. In STI, since trenches are made in silicon wafers to insert oxide films, the area of device isolation regions is small, which is advantageous for miniaturization of devices.

종래의 콘택홀 선폭 측정 방법은 모트와 폴리(Poly) 상에 형성된 콘택 홀을 을 동시에 측정한다. The conventional contact hole line width measuring method simultaneously measures the contact holes formed on the mort and the poly.

그러나, 와이드 모트(Wide Moat)와 와이드 폴리(Wide Poly) 상에서 선폭을 동시에 측정하는 기존의 방법으로는 콘택홀 패턴(Pattern)시 발생한 배열 오류(Mis-align)을 확인하는 건 불가능하다. However, it is impossible to identify misalignment occurring in the contact hole pattern by the conventional method of simultaneously measuring the line width on the wide moat and the wide poly.

도 1은 종래기술에 의한 반도체 소자의 콘택 홀 제조 방법을 나타낸 단면도이다. 도 1에서 보는 바와 같이 기존의 측정 포인트(Point)의 구조와 배열 오류가 발생하여 누설 결손(Leakage Fail)이 발생하였다. 이와 같이, 포토(Photo) 및 식각(Etch) 장비의 문제나 오버레이(Overlay) 또는 잡-파일(Job-File) 문제로 선폭 이동(CD Shift)이 발생하였을 경우 기존의 방법은 상기 문제점을 조기에 발견 하는데 한계가 있었다. 1 is a cross-sectional view illustrating a method for manufacturing a contact hole in a semiconductor device according to the prior art. As shown in FIG. 1, the structure and arrangement error of the existing measurement point occurred, resulting in leakage defects. As described above, when a CD shift occurs due to a problem of photo and etching equipment or an overlay or job-file problem, the conventional method preemptively solves the problem. There was a limit to discovery.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 콘택 모트 선폭 키에 STI 층을 삽입하여 선폭을 실제 셀(Cell) 지역과 동일한 조건에서 측정함으로써, 포토 및 식각 장비 변화 및 문제점을 양산시 조기에 발견할 수 있는 반도체 소자의 콘택 홀 선폭 모니터링 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by inserting the STI layer in the contact mote line width key to measure the line width in the same conditions as the actual cell area, photo and etching equipment changes and problems It is an object of the present invention to provide a method for monitoring the contact hole line width of a semiconductor device that can be found early in mass production.

본 발명의 상기 목적은 본 발명은 반도체 소자의 콘택 홀 선폭 모니터링 방법에 관한 것으로, 보다 자세하게는 콘택 모트 선폭 키에 트렌치 소자 분리 층을 삽입하여 실제 셀 지역과 동일한 조건 아래 평면에서 콘택 홀 선폭을 측정하는 것을 특징으로 하는 콘택 홀 선폭 모니터링 방법에 의해 달성된다.The present invention relates to a method for monitoring the contact hole line width of a semiconductor device. More specifically, the contact hole line width is measured in a plane under the same conditions as a real cell region by inserting a trench isolation layer in a contact moat line width key. It is achieved by a contact hole line width monitoring method characterized in that.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

먼저, 도 2a는 본 발명에 의한 반도체 소자의 콘택 홀 선폭 모니터링 방법을 나타낸 단면도이다. 도 2a에서 보는 바와 같이 모트 측정 포인트의 구조를 와이드 모트 구조에서 STI가 존재하는 구조로 변경하여 콘택 모트 선폭 키에 트렌치 소자 분리 층을 삽입하여 포토 및 식각 공정에서 발생하는 문제를 조기에 해결한다. First, FIG. 2A is a cross-sectional view illustrating a contact hole line width monitoring method of a semiconductor device according to the present invention. As shown in FIG. 2A, the structure of the mote measurement point is changed from the wide mote structure to the structure in which the STI exists so that a trench element isolation layer is inserted into the contact moat line width key to solve the problems occurring in the photo and etching process early.

도 2b는 본 발명에 의한 콘택 홀 스파이킹 현상을 검출한 사진으로서, 컨택 홀 식각시에도 식각 종료층(Stopping Layer)인 질화막(Nitride)과의 선택비가 떨어지면 STI영역에 형성된 산화막에 스파이킹(Spiking) 현상이 발생하게 되므로 콘택 선폭 변화 점검시 추가로 검사할 수 있다. FIG. 2B is a photograph of detecting contact hole spiking according to the present invention. Even when the contact hole is etched, when the selectivity with respect to the nitride layer, which is the etch stop layer, falls, the spikes are formed on the oxide film formed in the STI region. ) Phenomenon occurs, so it can be additionally checked when checking the contact line width change.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above-described embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 콘택 홀 선폭 모니터링 방법은 콘택 모트 선폭 키에 STI 층을 삽입하여 선폭을 실제 셀 지역과 동일한 조건에서 측정함으로써, 포토 및 식각 장비 변화 및 문제점을 양산시 조기에 발견할 수 있는 효과가 있다.Therefore, the contact hole line width monitoring method of the present invention has an effect of early detection of photo and etching equipment changes and problems by inserting an STI layer into the contact moat line width key and measuring the line width under the same conditions as the actual cell area. have.

Claims (2)

콘택 홀 선폭 모니터링 방법에 있어서,In the contact hole line width monitoring method, 콘택 모트 선폭 키에 STI(Shallow Trench Isolation) 층을 삽입하여 실제 셀(Cell) 지역과 동일한 조건 아래 평면에서 콘택 홀 선폭을 측정하는 것을 특징으로 하는 콘택 홀 선폭 모니터링 방법.A method for monitoring contact hole linewidth, comprising inserting a shallow trench isolation (STI) layer into a contact moat linewidth key in the plane under the same conditions as the actual cell area. 삭제delete
KR1020040116531A 2004-12-30 2004-12-30 Method for monitoring the critical dimension of contact hole of semiconductor device KR100609978B1 (en)

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KR100869746B1 (en) * 2007-07-13 2008-11-21 주식회사 동부하이텍 Test element group for monitoring leakage current in a semiconductor device and method of manufacturing the same
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Publication number Priority date Publication date Assignee Title
JPH11340193A (en) 1998-05-19 1999-12-10 United Microelectronics Corp Monitor pattern for critical dimension controller and method for using the same
US6350994B1 (en) 2000-11-14 2002-02-26 United Microelectronics Corp. Structure of critical dimension bar

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340193A (en) 1998-05-19 1999-12-10 United Microelectronics Corp Monitor pattern for critical dimension controller and method for using the same
US6350994B1 (en) 2000-11-14 2002-02-26 United Microelectronics Corp. Structure of critical dimension bar

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