KR100609569B1 - Method of forming a BPSG film in a semiconductor device - Google Patents

Method of forming a BPSG film in a semiconductor device Download PDF

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KR100609569B1
KR100609569B1 KR1019990065143A KR19990065143A KR100609569B1 KR 100609569 B1 KR100609569 B1 KR 100609569B1 KR 1019990065143 A KR1019990065143 A KR 1019990065143A KR 19990065143 A KR19990065143 A KR 19990065143A KR 100609569 B1 KR100609569 B1 KR 100609569B1
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bpsg film
forming
semiconductor device
mask
reflow
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KR20010065271A (en
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서윤석
손기근
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

본 발명은 반도체 소자의 BPSG막 형성 방법에 관한 것으로, BPSG막을 증착한 후 750∼900℃에서 10∼40분간 리플로우를 실시한 후 냉각 속도를 15∼50℃/min 정도로 빠르게 함으로써 BPSG막의 표면에 압축 응력을 형성하여 표면에서의 수분 흡수를 억제한다. 따라서, BPSG막과 마스크와의 고착력을 증대시켜 마스크 계면에서의 식각 속도를 다른 부위와 균일하게 하므로써 과도 식각으로 인한 움푹 패인 형상을 방지한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a BPSG film of a semiconductor device. After depositing a BPSG film, reflow is performed at 750 to 900 ° C. for 10 to 40 minutes, and the cooling rate is increased to about 15 to 50 ° C./min. Form stresses to inhibit water absorption on the surface. Therefore, by increasing the adhesion between the BPSG film and the mask to make the etching speed at the mask interface uniform with other parts, the recessed shape due to the excessive etching is prevented.

BPSG막, 리플로우, 램프 다운BPSG film, reflow, ramp down

Description

반도체 소자의 비피에스지막 형성 방법{Method of forming a BPSG film in a semiconductor device} Method of forming a BPSG film in a semiconductor device             

도 1은 종래의 BPSG막의 리플로우 방법을 설명하기 위한 레시피도.1 is a recipe diagram for explaining a conventional reflow method of a BPSG film.

도 2는 종래 방법에 의해 형성된 BPSG막을 습식 식각한 후 마스크와의 계면 사진.2 is a photograph of an interface with a mask after wet etching a BPSG film formed by a conventional method.

도 3은 본 발명에 따른 BPSG막의 리플로우 방법을 설명하기 위한 레시피도.Figure 3 is a recipe for explaining a reflow method of the BPSG film according to the present invention.

도 4는 본 발명에 의해 형성된 BPSG막을 습식 식각한 후 마스크와의 계면 사진.Figure 4 is a photograph of the interface with the mask after wet etching the BPSG film formed by the present invention.

본 발명은 반도체 소자의 비피에스지(BPSG)막 형성 방법에 관한 것으로, 특히 BPSG막을 증착한 후 750∼900℃에서 10∼40분간 리플로우를 실시한 후 냉각 속도를 15∼50℃/min 정도로 빠르게 함으로써 BPSG막과 마스크와의 고착력을 증대시 켜 마스크 계면에서의 식각 속도를 다른 부위와 균일하게 하여 과도 식각으로 인한 움푹 패인 형상을 방지할 수 있는 반도체 소자의 BPSG막 형성 방법에 관한 것이다.The present invention relates to a method for forming a BPSG film of a semiconductor device, and in particular, by depositing a BPSG film and then reflowing at 750 to 900 ° C for 10 to 40 minutes, thereby increasing the cooling rate to about 15 to 50 ° C / min. The present invention relates to a method for forming a BPSG film of a semiconductor device capable of increasing the adhesion between the BPSG film and the mask to make the etch rate at the mask interface uniform with other portions, thereby preventing the dent from the excessive etching.

다층 배선을 형성하는 반도체 소자의 제조 공정에서 하부 구조와 상부 구조를 절연시키기 위해 형성하는 BPSG막은 셀 지역과 주변 회로 지역의 단차를 최대한으로 완화시키기 위해 최대한 고농도로 소정 두께 증착한 후 고온에서 열처리를 실시하여 리플로우시킨다. 또한, 이후 공정으로 주변 회로 지역에 형성하는 식각 마스크에 의한 셀 지역만의 선택적 습식 식각으로 셀 지역과 주변 회로 지역간의 단차를 더욱 완화시킨다. 여기서, BPSG막의 열처리는 도 1과 같은 레시피에 의해 실시된다. 즉, 600℃의 온도를 유지하는 챔버에 워이퍼를 로딩한 후 3℃/min의 속도로 850℃까지 램프업시킨다. 850℃에서 약 20분동안 리플로우를 실시한 후 3℃/min의 속도로 600℃까지 램프 다운하고 웨이퍼를 언로딩한다.The BPSG film formed to insulate the lower structure from the upper structure in the manufacturing process of a semiconductor device forming a multi-layer wiring is deposited with a predetermined thickness at the highest concentration to minimize the step difference between the cell region and the peripheral circuit region, and then subjected to heat treatment at a high temperature. To reflow. In addition, the selective wet etching of only the cell region by the etching mask formed in the peripheral circuit region by the subsequent process further alleviates the step between the cell region and the peripheral circuit region. Here, the heat treatment of the BPSG film is performed by the recipe as shown in FIG. That is, the wafer is loaded in the chamber maintaining the temperature of 600 ℃ and ramped up to 850 ℃ at a rate of 3 ℃ / min. After about 20 minutes of reflow at 850 ° C., ramp down to 600 ° C. at 3 ° C./min and unload the wafer.

고농도의 BPSG막은 표면의 붕소와 인이 수분과 반응하여 표면에 수분기를 함유하게 되므로 주변 회로 지역에 형성된 식각 방지 마스크의 경계면에서 식각 방지 마스크와의 고착력을 약화시킨다. 이에 의해 마스크와 BPSG막과의 계면에서는 습식 식각 용액의 빠른 침투(모세관 현상)에 의해서 과도 식각이 일어나게 되므로 계면을 중심으로 도 2의 사진에서 볼 수 있는 바와 같이 BPSG막이 움푹 패이게 된다. 이와 같은 현상은 후속 제 1 금속 배선을 형성하기 위한 노광 및 식각 공정에 불리하게 작용할 뿐만 아니라 제 2 금속 배선을 형성하기 위한 제 1 금속 배선과의 콘택 형성시 콘택 깊이가 깊어지게 되어 제 2 금속 배선의 콘택 매립을 어렵게 하므 로 소자 불량의 주원인이 된다.Since the high concentration of BPSG film reacts with moisture in the surface of boron and phosphorus, the surface contains moisture groups, thereby weakening the adhesion to the etch mask at the interface of the etch mask formed in the peripheral circuit area. As a result, excessive etching occurs at the interface between the mask and the BPSG film due to the rapid penetration of the wet etching solution (capillary phenomenon), so that the BPSG film is pitted as shown in the photograph of FIG. 2 around the interface. This phenomenon not only adversely affects the exposure and etching process for forming the subsequent first metal wiring, but also deepens the contact depth when forming a contact with the first metal wiring for forming the second metal wiring so that the second metal wiring is formed. This makes it difficult to fill the contacts, which is the main cause of device defects.

따라서, 본 발명은 BPSG막의 표면에 압축 응력을 형성하여 표면에서의 수분 흡수를 억제하므로써 BPSG막과 마스크와의 고착력을 증대시켜 마스크 계면에서의 식각 속도를 다른 부위와 균일하게 하므로써 과도 식각으로 인한 움푹 패인 형상을 방지할 수 있는 반도체 소자의 BPSG막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention increases the adhesion between the BPSG film and the mask by forming a compressive stress on the surface of the BPSG film to suppress water absorption on the surface, thereby making the etching rate at the mask interface uniform with other parts, resulting in excessive etching. It is an object of the present invention to provide a method for forming a BPSG film of a semiconductor device capable of preventing a recessed shape.

상술한 목적을 달성하기 위한 본 발명은 반도체 소자의 BPSG막 형성 방법에 있어서, 소정의 공정을 통해 하부 구조가 형성된 웨이퍼에 BPSG막을 증착하는 단계와, 상기 BPSG막이 증착된 웨이퍼를 반응로에 로딩시키는 단계와, 상기 반응로를 램프업시켜 750 내지 900℃의 온도에서 10 내지 40분간 열처리를 실시하여 BPSG막을 리플로우하는 단계와, 상기 반응로의 온도를 200 내지 700℃로 램프 다운시켜 언로딩하는 단계와, 상기 BPSG막의 소정 부분만을 식각하는 단계를 포함하여 이루어진 것을 특징으로 한다.
According to an aspect of the present invention, there is provided a method for forming a BPSG film of a semiconductor device, the method comprising: depositing a BPSG film on a wafer on which a lower structure is formed through a predetermined process, and loading the wafer on which the BPSG film is deposited into a reactor; And ramping up the reactor to heat treatment at a temperature of 750 to 900 ° C. for 10 to 40 minutes to reflow the BPSG film, and ramping down and unloading the temperature of the reactor to 200 to 700 ° C. And etching only a predetermined portion of the BPSG film.

본 발명에서는 BPSG막을 증착한 후 750∼900℃에서 10∼40분간 리플로우를 실시한 후 냉각 속도를 15∼50℃/min 정도로 빠르게 함으로써 BPSG막의 표면에 압축 응력을 형성하여 표면에서의 수분 흡수를 억제한다. 따라서, BPSG막과 마스크와의 고착력을 증대시켜 마스크 계면에서의 식각 속도를 다른 부위와 균일하게 하므 로써 과도 식각으로 인한 움푹 패인 형상을 방지하게 한다.In the present invention, after the BPSG film is deposited, reflow is performed at 750 to 900 ° C. for 10 to 40 minutes, and then the cooling rate is increased to about 15 to 50 ° C./min to form compressive stress on the surface of the BPSG film to suppress water absorption on the surface. do. Therefore, the adhesion between the BPSG film and the mask is increased to make the etching speed at the mask interface uniform with other parts, thereby preventing the recessed shape due to the excessive etching.

본 발명에 따른 반도체 소자의 BPSG막 형성 방법을 설명하면 다음과 같다.A method of forming a BPSG film of a semiconductor device according to the present invention is as follows.

반도체 소자의 제조 공정에서 하부 구조, 즉 캐패시터 또는 하부 금속 배선을 형성한 후 셀 지역과 주변 회로 지역의 고단차를 완화시키기 위해 상압화학기상증착 방법에 의해 BPSG막을 7000∼15000Å의 두께로 형성한다. 이때, BPSG막은 리플로우가 크게 일어날 수 있도록 붕소의 농도는 3.5∼5.0wt%, 인의 농도는 2.5∼4.5wt% 정도로 한다. 그리고 BPSG막이 형성된 웨이퍼를 리플로우시키기 위한 열처리 공정을 실시한다. 열처리 공정은 도 3에 도시된 바와 같이 실시한다. 즉, 200∼700℃의 온도를 유지하는 챔버에 웨이퍼를 로딩한 후 15∼50℃/min의 속도로 램프업시켜 750∼900℃의 온도에서 10∼40분간 열처리를 실시한다. 이후 15∼50℃/min의 속도로 램프 다운시켜 200∼700℃의 온도에서 웨이퍼를 언로딩시킨다. 이때, 상기와 같은 열처리 공정은 질소 분위기에서 실시한다. 이와 같은 급랭에 의해 BPSG막의 표면에 압축 응력이 형성되어 표면에서의 수분 흡수를 억제한다. 이후 셀 지역의 BPSG막을 제거하기 위해 주변 회로 지역에 식각 방지 마스크를 형성하고, BOE 용액 또는 불산 용액을 사용한 습식 식각 공정을 실시하여 셀 지역의 BPSG막을 제거한다. 이때 제거하는 BPSG막의 두께는 상층 금속 배선과 충분히 절연될 수 있도록 3500∼12000Å 정도로 한다.In the process of manufacturing a semiconductor device, after forming a lower structure, that is, a capacitor or a lower metal wiring, a BPSG film is formed to a thickness of 7000 to 15000 kW by an atmospheric pressure chemical vapor deposition method to alleviate the high step difference between the cell region and the peripheral circuit region. At this time, the BPSG film has a boron concentration of 3.5 to 5.0 wt% and phosphorus concentration of about 2.5 to 4.5 wt% so that reflow can occur largely. Then, a heat treatment step for reflowing the wafer on which the BPSG film is formed is performed. The heat treatment process is carried out as shown in FIG. That is, the wafer is loaded into a chamber holding a temperature of 200 to 700 ° C, ramped up at a rate of 15 to 50 ° C / min, and heat treated for 10 to 40 minutes at a temperature of 750 to 900 ° C. The ramp is then ramped down at a rate of 15-50 ° C./min to unload the wafer at a temperature of 200-700 ° C. At this time, the heat treatment step as described above is carried out in a nitrogen atmosphere. By such quenching, compressive stress is formed on the surface of the BPSG film to suppress water absorption on the surface. Thereafter, an etch mask is formed in the peripheral circuit area to remove the BPSG film in the cell area, and a wet etching process using a BOE solution or a hydrofluoric acid solution is performed to remove the BPSG film in the cell area. At this time, the thickness of the BPSG film to be removed is about 3500-12000 kPa so as to be sufficiently insulated from the upper metal wiring.

상기와 같은 방법으로 BPSG막을 형성한 후 이를 습식 식각하면 도 4에 보인 바와 같이 식각 마스크의 경계면에서의 식각 속도는 다른 곳과 크게 다르지 않기 때문에 균일한 형상을 이루게 된다.When the BPSG film is formed and wet etched in the same manner as described above, as shown in FIG. 4, the etching speed at the interface of the etch mask is not significantly different from other places, thereby forming a uniform shape.

상술한 바와 같이 본 발명에 의하면 셀 지역에 형성된 BPSG막을 소정 두께 제거하기 위한 습식 식각 공정에서 주변 회로 영역에 형성된 마스크와의 계면에서의 과도 식각을 억제하므로써 균일한 계면을 형성할 수 있고, 후속 금속 배선 형성을 가능하게 하며 금속 배선간의 콘택 매립을 용이하게 한다.As described above, according to the present invention, in the wet etching process for removing a predetermined thickness of the BPSG film formed in the cell region, a uniform interface can be formed by suppressing excessive etching at the interface with the mask formed in the peripheral circuit region. It enables the formation of wiring and facilitates contact filling between metal wirings.

Claims (6)

소정의 공정을 통해 하부 구조가 형성된 웨이퍼에 BPSG막을 증착하는 단계;Depositing a BPSG film on a wafer having a lower structure formed through a predetermined process; 상기 BPSG막이 증착된 웨이퍼를 200 내지 700℃의 온도를 유지하는 반응로에 로딩시키는 단계;Loading the wafer on which the BPSG film is deposited into a reactor maintaining a temperature of 200 to 700 ° C .; 상기 반응로를 15℃/분 내지 50℃/분의 속도로 램프업시켜 750 내지 900℃의 온도에서 10 내지 40분간 열처리를 실시하여 BPSG막을 리플로우하는 단계;Ramping up the reactor at a rate of 15 ° C./min to 50 ° C./min and performing a heat treatment for 10 to 40 minutes at a temperature of 750 to 900 ° C. to reflow the BPSG film; 상기 반응로의 온도를 15℃/분 내지 50℃/분의 속도로 200 내지 700℃로 램프 다운시키고 상기 웨이퍼를 언로딩하는 단계; 및Ramping down the temperature of the reactor to 200-700 ° C. at a rate of 15 ° C./min to 50 ° C./min and unloading the wafer; And 상기 BPSG막의 소정 부분만을 식각하는 단계를 포함하는 반도체 소자의 BPSG막 형성 방법.And etching only a predetermined portion of the BPSG film. 제 1 항에 있어서, 상기 BPSG막은 상압화학기상증착 방법으로 7000 내지 15000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 BPSG막 형성 방법.2. The method of claim 1, wherein the BPSG film is formed to a thickness of 7000 to 15000 kPa by an atmospheric pressure chemical vapor deposition method. 제 1 항에 있어서, 상기 BPSG막은 3.5 내지 5.0wt%의 붕소와 2.5 내지 4.5wt%의 인 농도를 갖는 것을 특징으로 하는 반도체 소자의 BPSG막 형성 방법.The method of claim 1, wherein the BPSG film has a boron concentration of 3.5 to 5.0 wt% and phosphorus concentration of 2.5 to 4.5 wt%. 삭제delete 삭제delete 삭제delete
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