KR100607744B1 - Liquid crystal panel for OCB mode, liquid crystal display using the same and driving method thereof - Google Patents

Abstract

Disclosed are a liquid crystal panel, a liquid crystal display device using the same, and a driving method thereof, which are capable of speeding up to a bend state during a reset period in an OSC mode.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes an array substrate including a plurality of gate lines and a plurality of pixel electrodes, a counter substrate, and liquid crystals controlled in an OSC mode between the array substrate and the counter substrate. An LCD panel for an OSC mode including a layer; A voltage generator generating voltages for driving the liquid crystal panel; A timing controller for generating a reset control signal for initializing the liquid crystal during a reset period and a display control signal for displaying a predetermined image during the display period; Switching means for switching the output path of the voltages generated from the voltage generator to be changed; And a gate driver and a data driver for driving the liquid crystal panel using the changed switching voltages in the switching means, wherein the same voltage via the switching means is applied to the plurality of gate lines and the plurality of pixels during the reset period. Applied to the electrodes. Therefore, according to the present invention, it is possible to implement a faster initialization by removing the transverse electric field generated between the gate lines and the pixel electrodes when driving the reset section.

LCD, OSC mode, reset section, display section

Description

Liquid Crystal Panel for OCB mode, liquid crystal display using the same and driving method             

1A and 1B are diagrams for explaining an operation of a general OSC mode.

2 is a graph of light transmittance against voltage in a conventional OCB mode.

3 is a plan view of a liquid crystal panel having a conventional OCB mode.

4 is a side cross-sectional view taken along the line AA 'of FIG.

5 is an exemplary view illustrating a liquid crystal panel during the transition from the splay state to the bend state in FIG. 3.

6 is a side cross-sectional view of a liquid crystal panel having an OCB mode according to an embodiment of the present invention.

7 is a block diagram schematically illustrating a configuration of a liquid crystal display device capable of fast initialization according to an embodiment of the present invention.

8 is a view showing waveforms of respective voltages in the OSC mode according to the present invention.

<Name of the code for the main part of the drawing>

40: LCD panel for OSC mode

43: gate line 44: pixel electrode

46: common electrode 52: timing controller

53: gate driver 54: data driver

56: voltage generator 57, 58, 59: switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having an OSC mode, and more particularly to an OSC mode liquid crystal panel capable of speeding up to a bend state during a reset period, a liquid crystal display using the same, and a driving method thereof.

In general, a liquid crystal display device displays a desired image by individually supplying data voltages according to image information to liquid crystal cells arranged in a matrix form and adjusting light transmittance of the liquid crystal layer according to the supplied data voltage. It is a display device.

The liquid crystal layer is composed of liquid crystals filled between an array substrate and an opposing substrate opposed to the liquid crystal layer, and these liquid crystals are different in an array state according to their characteristics.

In particular, in the OBC (Optical Compensated Birefringence) mode, liquid crystals are initially oriented in a splay state (FIG. 1A) and bend during a reset period in which a predetermined voltage is applied to these liquid crystals. It is transferred to the bend state and is oriented (FIG. 1B).

As shown in FIG. 1A, generally, in OCB mode, liquid crystals near the alignment layers 1 and 2 are initially arranged with an initial tilt angle of 3 to 20 °, whereas liquid crystals in the center of the liquid crystal layer are zero. It will be arranged with a tilt angle of °.

When a high voltage is applied to the liquid crystal layers initially arranged in the splay state as described above, after a predetermined time, that is, a reset period passes, the liquid crystals in the center of the liquid crystal layer are in a bend state having an inclination angle of 90 ° as shown in FIG. 1B. Will be arranged.

In this case, the time taken for the liquid crystals in the center of the liquid crystal layer to be aligned from 0 ° to 90 ° during the reset period is usually several seconds.

2 is a graph of light transmittance with respect to the voltage of the conventional OCB mode.

As shown in FIG. 2, initially, when no voltage is applied, as shown in FIG. 1A, the liquid crystals in the center of the liquid crystal layer are arranged in a splay state, so that the light transmittance is relatively high.

As the voltage is gradually applied, the liquid crystals in the middle of the liquid crystal layer are gradually inclined by the applied voltage, and the light transmittance begins to decrease.

At this time, the liquid crystals in the middle of the liquid crystal layer have a significant inclination as the specific voltage (here, about 1.8 V) is exceeded, and is arranged in a bend state as shown in FIG. 1B. Close.

Therefore, in the OCB mode, the liquid crystals initially arranged in the splay state are applied with a voltage above a specific voltage and arranged in the bend state, and thus the voltage value is changed in the range of the bend state so that a predetermined image is displayed. .

3 is a plan view of a liquid crystal panel having a conventional OCB mode. 4 is a side cross-sectional view taken along the line AA ′ of FIG. 3. FIG. 5 is an exemplary view illustrating a liquid crystal panel during the transition from the splay state to the bend state in FIG. 3.

3 and 4, the liquid crystal panel having the OCB mode includes an array substrate 15, an opposing substrate 18 and a liquid crystal layer 17. As shown in FIG.

The array substrate 15 includes gate lines 4 arranged in a first direction, data lines 3 arranged in a second direction perpendicular to the gate lines 4, and the gate lines ( 4) and thin film transistors T formed at intersections of the data lines 3 and pixel electrodes 5 connected to the thin film transistors T.

In FIG. 4, reference numeral 10 denotes a lower substrate for forming the gate lines 4, the data lines 3, the thin film transistors T, and the pixel electrodes 5. A gate insulating film for insulating between the gate lines 4 and the pixel electrodes 5 is shown.

The counter substrate 18 has a common electrode 22 formed on the upper substrate 20. Although not shown in FIG. 4, the counter substrate 18 may further include a color filter for controlling color and a black matrix for controlling the aperture ratio.

The liquid crystal layer 17 may be formed of liquid crystals filled between the array substrate 15 and the opposing substrate 18, and these liquid crystals have OCB mode characteristics.

Since driving according to the OCB mode characteristic has already been described above, further description thereof will be omitted.

In a liquid crystal panel having a conventional OCB mode, the splay state is initialized by transitioning to a bend state, and then an image is displayed by changing a voltage applied in the bend state.

In this case, as shown in FIG. 4, the voltage applied to the liquid crystal panel is used as it is for initialization during the reset period. That is, a high potential gate voltage of approximately 20V is applied to each gate line 4, a data voltage of 10V is applied to each pixel electrode 5, and a voltage of 5V may be applied to the common electrode 22. . At this time, a voltage of 20V or more may be applied to the gate line 4 as necessary. The voltage applied to the pixel electrode 5 may be supplied via the thin film transistor T to the voltage supplied to the data line 3.

Accordingly, the arrangement of the liquid crystals of the liquid crystal layer 17 by the voltage difference 5V, ie, the electric field, between the pixel electrode 5 of the array substrate 15 and the common electrode 22 of the opposing substrate 18. It will be transformed into a state. That is, initially, the liquid crystals in the splay state are gradually transferred to the liquid crystals in the bend state.

Meanwhile, since a voltage of 20V is applied to the gate line 4 of the array substrate 15, the liquid crystals are also deformed by the voltage difference 15V between the gate line 4 and the common electrode 22. . In this case, the gate line 4 and the pixel electrode 5 are formed on substantially the same layer in the transverse direction on the array substrate 15, and the voltage applied to the gate line 4 and the pixel electrode ( There is also a potential difference between the voltages applied to 5) and an electric field is generated in the transverse direction. Therefore, the liquid crystals existing between the pixel electrode 5 and the gate line 4 due to the lateral electric field cause a problem in the transition to the bend state. That is, when the liquid crystal cells gradually have a high inclination angle due to the electric field between the pixel electrode 5 and the common electrode 22, the gate line 4 adjacent to the pixel electrode 5 and the pixel electrode 5. Due to the transverse electric field between the liquid crystal cells, which gradually have a high inclination angle, they are disturbed, and the time taken for the complete bend state with a 90 ° inclination angle to be delayed becomes slow.

An experimental drawing for this is shown in FIG. 5. As shown in FIG. 5, a tilt domain B is generated between the pixel electrode 5 and the gate line 4 by a transverse electric field, and the tilt region causes the bend in the initial splay state. There is a problem that the time taken to transition to the state is delayed.

Accordingly, when applied to the gate line 4, the pixel electrode 5 and the common electrode 22 with the voltages mentioned above in the conventional liquid crystal panel, it is impossible to speed up the initialization by shortening the reset period. .

As such, if the initialization of the liquid crystal panel having the OCB mode is not accelerated, it may take considerable time to view a predetermined image from the user's side, and a considerable dissatisfaction may be raised, which may be fatal in product sales.

As described above, in order to display a predetermined image on the liquid crystal panel of the OCB mode, when the power is supplied, the predetermined image is not immediately displayed, but the liquid crystals in the splay state are transferred to the bent liquid crystals during the reset period. After the image is initialized, a predetermined image is supplied to the liquid crystal panel and displayed as an image.

Accordingly, in the OCB mode liquid crystal panel, it is pointed out that being able to shorten the reset period and speed it up is more important than anything else.

However, when different voltages are applied to the gate line and the pixel electrode as in the related art, the transverse electric field is generated and the transition time from the splay state to the bend state is delayed, so that high speed cannot be realized.

Accordingly, the present invention has been made to solve the above-mentioned problems, by reducing the delay of the reset time according to the transverse electric field by the same voltage applied to the gate line and the pixel electrode can be speeded up during initialization An object of the present invention is to provide a liquid crystal panel, a liquid crystal display device using the same, and a driving method thereof.

In addition, the present invention provides a liquid crystal panel for the OSC mode, a liquid crystal display device using the same and a driving method thereof which can achieve a faster initialization by applying a voltage lower than the voltage applied when driving the voltage applied to the common electrode. There is another purpose in providing.

According to a first embodiment of the present invention for achieving the above object, the liquid crystal panel for the OSB mode, the plurality of gate lines arranged in a first direction; A plurality of data lines arranged in a second direction perpendicular to the plurality of gate lines; A plurality of thin film transistors formed at intersections of the gate lines and data lines; And an array substrate including a plurality of pixel electrodes connected to the thin film transistors, an opposing substrate facing the array substrate and provided with a common electrode, and between the array substrate and the opposing substrate in an OSC mode. The liquid crystal layer is filled with liquid crystals to be controlled, and the OSC mode is driven by being divided into a reset section for initializing the liquid crystals and a display section for displaying a predetermined image by controlling the initialized liquid crystals. The same voltage is applied to the plurality of gate lines and the plurality of pixel electrodes.

According to a second preferred embodiment of the present invention, a liquid crystal display device includes a plurality of gate lines and a plurality of data lines arranged vertically and crosswise, a plurality of thin film transistors formed at intersections of the gate lines and the data lines; An array substrate including a plurality of pixel electrodes connected to the thin film transistors, an opposing substrate facing the array substrate and provided with a common electrode, and controlled in an OSC mode between the array substrate and the opposing substrate. A liquid crystal panel for OSB mode including a liquid crystal layer filled with liquid crystals; A voltage generator generating voltages for driving the liquid crystal panel; A timing controller for generating a reset control signal for initializing the liquid crystal during a reset period and a display control signal for displaying a predetermined image during the display period; Switching means for switching such that an output path of voltages generated from the voltage generator is changed according to the reset control signal and the display control signal; And a gate driver and a data driver for driving the liquid crystal panel using the changed switching voltages in the switching means, wherein the same voltage via the switching means is applied to the plurality of gate lines and the plurality of pixels during the reset period. Applied to the electrodes.

Herein, the switching means supplies the same voltage among the voltages generated from the voltage generator to the gate driver and the data driver under the control of the reset control signal, and switches to supply the reset common voltage to the common electrode. Can be.

According to a third preferred embodiment of the present invention, a plurality of gate lines and a plurality of data lines vertically arranged in cross-section, a plurality of thin film transistors and the thin film transistors formed at the intersection of the gate lines and the data lines An array substrate including a plurality of pixel electrodes connected to each other, an opposing substrate facing the array substrate and provided with a common electrode, and a liquid crystal filled with liquid crystals controlled in an OSC mode between the array substrate and the opposing substrate A driving method of a liquid crystal display for driving a liquid crystal panel for an OSC mode including a layer comprises the steps of: generating a reset control signal for a reset section and a display control signal for a display section; When driving the reset section, the same voltage among the voltages generated from the voltage generator is output to the plurality of gate lines and the pixel electrodes of the liquid crystal panel under the control of the reset control signal, and a reset common voltage is applied to the liquid crystal panel. First switching to be output to the common electrode; Initializing the liquid crystals of the liquid crystal panel by the same voltage and the reset common voltage; Performing a second switching to output a high potential gate voltage, a data voltage, and a common voltage among the voltages generated from the voltage generator under control of the display control signal when driving a display period; And displaying an image on the liquid crystal panel using the high potential gate voltage, the data voltage, and the common voltage.
According to the first to third embodiments of the present invention, the same voltage may be one of a gate high potential voltage and a data voltage.

delete

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

The OCB mode is divided into a reset section and a display section according to its driving. Here, the reset period refers to a period for initializing the liquid crystal in the splay state to the bend state to initialize, and the display period is initialized to control the liquid crystal arranged in the bend state according to a predetermined gray scale voltage to obtain a desired image. It means the section to be displayed.

As described above, the liquid crystal display of the OCB mode transfers and initializes the liquid crystals arranged in the splay state during the reset period to the liquid crystals arranged in the bend state, and then a predetermined gray scale voltage is applied to the display period to display an image.

Therefore, the section in which the image is actually displayed in the OCB mode liquid crystal display device is limited to the display section, and the image is not displayed during the reset section. Therefore, it will be important to minimize the reset period by transitioning the liquid crystals to the bend state as soon as possible.

In the present invention, by applying the same voltage to the gate line and the pixel electrode provided in the liquid crystal panel, the liquid crystal having a splay state can be transferred to the bend state at high speed by minimizing the horizontal electric field.

In addition, in the present invention, the reset common voltage applied to the reset section to the common electrode provided in the liquid crystal panel is lower than the common voltage applied to the display section, thereby increasing the voltage difference between the pixel electrode and the common electrode more quickly. Can be transferred to the bend state.

6 is a side cross-sectional view of a liquid crystal panel having an OCB mode according to an embodiment of the present invention. Although FIG. 6 has the same structure as FIG. 4, it should be noted that voltages applied to the gate line, the pixel electrode, and the common electrode are different from those of FIG. 6.

As shown in FIG. 6, the liquid crystal panel 40 having the OCB mode includes gate lines 43 arranged in a first direction and data lines arranged in a second direction perpendicular to the gate lines 43. 3, thin film transistors (T in FIG. 3) formed at intersections of the gate lines 43 and the data lines, and pixel electrodes 44 connected to the thin film transistors. And a liquid crystal layer 48 made up of an array substrate 47, a counter substrate 49 having a common electrode 46, and liquid crystals filled between the array substrate 47 and the counter substrate 49. ).

In this case, gate lines 43 are formed on the lower substrate 41, a gate insulating layer 42 is formed on the gate lines 43, and the gate insulating layer 42 is formed on the array substrate 47. Pixel electrodes 44 are arranged on the substrate.

The counter substrate 49 may include a common electrode 46 formed on the upper substrate 45, and further include a color filter, a black matrix, and the like, which are not shown.

The liquid crystal layer 48 may be formed of liquid crystals filled between the array substrate 47 and the counter substrate 48, and these liquid crystals have OCB mode characteristics.

The liquid crystal panel 40 having the OCB mode configured as described above initializes the panel so that the liquid crystals of the liquid crystal layer 48 transition from the splay state to the bend state. The same voltage (Vgh = Vdata) is applied to the field 44. At the same time, a reset common voltage lower than the common voltage Vcom applied to the common electrode 46 is applied to the display section, which is a section displaying a predetermined image by applying different gray voltages to the liquid crystals transitioned to the bend state. Vcom_reset) is applied to the common electrode 46 during the reset period. In this case, the voltage Vgh applied to the gate lines 43 during the reset period is preferably the voltage Vdata applied to the pixel electrodes 44. That is, during the reset period, one of the high potential gate voltage Vgh and the data voltage Vdata is simultaneously supplied to the gate lines 43 and the pixel electrodes 44.

For example, during the reset period, the same data voltage Vdata of 10V is applied to the gate lines 43 and the pixel electrodes 44, and a reset common voltage of 0V is applied to the common electrode 46. Vcom_reset) may be applied. In this case, the same 10V data voltage Vdata is applied to the gate lines 43 and the pixel electrodes 44 so that a potential difference does not exist between the gate lines 43 and the pixel electrodes 44. There is no tilt region according to the transverse electric field so that the liquid crystals may be transferred to the bend state at a higher speed. In addition, a potential difference of 10 V exists between the pixel electrodes 44 and the common electrode 46, so that a faster initialization may be performed. Conventionally, a common voltage Vcom of 5V is applied to the common electrode, and in this case, only a 5V potential difference exists between the pixel electrodes and the common electrode, so that the potential difference of about 5V is higher than that of the present invention (a potential of 10V). As a result, the time required for fast initialization becomes longer.

Although not shown in FIG. 6, even when the voltage Vgh applied to the gate lines 43 is applied as it is to the voltage Vdata of the pixel electrodes 44, the transverse electric field is removed to obtain a faster bend state. May be enabled.

For example, during the reset period, the same high potential voltage Vgh of 20 V is applied to the gate lines 43 and the pixel electrodes 44, respectively, and a reset common voltage of 0 V is applied to the common electrode 46. Vcom_reset) may be applied. In this case, both the gate lines 43 and the pixel electrodes 44 are applied with the same high-potential voltage Vgh of 20 V, so that a potential difference does not exist between them so that a transverse electric field is not generated. Accordingly, the tilt region according to the transverse electric field does not exist, and thus the liquid crystals may be transferred to the bend state at a higher speed. In addition, a potential difference of 20 V exists between the pixel electrodes 44 and the common electrode 46, and thus, as described above, a potential difference of 10 V when the data voltage Vdata of 10 V is applied to the pixel electrodes 44. Since the potential difference is larger by about 10V, the initialization can be performed as quickly as that.

Meanwhile, when the reset period passes and the display period passes, voltages Vgh, Vdata, and Vcom for displaying an image are applied to the liquid crystal panel 40. That is, a high potential voltage Vgh of 20V is applied to the gate lines 43, different gradation voltages (range of 0 to 10V) are applied to the pixel electrodes 44, and the common electrode 46 is applied. ) Is applied a common voltage (Vcom) of 5V.

Accordingly, the thin film transistor is turned on by the high potential voltage applied to the gate lines 43, and the gray voltage supplied to the data lines is applied to the pixel electrodes 44 via the thin film transistor. To be authorized. Accordingly, the amount of light that is deformed and transmitted through the liquid crystals of the liquid crystal layer 48 according to an electric field caused by a potential difference between the gray voltage applied to the pixel electrodes 44 and the common voltage Vcom applied to the common electrode 46. This control is performed to display a predetermined image.

In this case, an image composed of a plurality of frames is displayed on the liquid crystal panel in units of frames in the display section.

Hereinafter, a liquid crystal display device for supplying different voltages to the liquid crystal panel 40 according to the reset period and the display period so that initialization and an image are displayed will be described.

7 is a block diagram schematically illustrating a configuration of a liquid crystal display device capable of fast initialization according to an embodiment of the present invention.

Referring to FIG. 7, the LCD device includes a digital video card 51, a timing controller 52, a DC-DC converter 55, a voltage generator 56, a first switch 57, and a second switch ( 58, a third switch 59, a gate driver 53, a data driver 54, a liquid crystal panel 40 for the OSC mode, and the like.

The digital video card 51 converts external analog image data into digital image data, and detects synchronization signals Vsync and Hsync from the analog image data and supplies them to the timing controller 52.

In the OCB mode, the timing controller 52 is divided into a reset section and a display section to generate a reset control signal and a display control signal for driving the liquid crystal panel 40 in each section. Here, the reset control signal is a signal for initializing the liquid crystal panel 40 during the reset period, and is generated depending on whether power is supplied to the DC-DC converter 55. That is, the timing controller 52 detects when the power is supplied to the DC-DC converter 55, that is, when the user turns on the power to watch the image displayed on the liquid crystal panel 40. By generating a reset control signal for initializing the liquid crystal panel 40 during the reset period. To this end, the timing controller 52 may be provided with means (not shown) for detecting whether power is supplied to the DC-DC converter 55.

On the other hand, when the reset section has elapsed and becomes the display section, the timing controller 52 uses the gate driver 53 and the data driver (B) using the digital image data and the synchronization signal supplied from the digital video card 51. A display control signal for driving 54 is generated. The display control signal is transmitted to the data driver 54 and the first display control signal including a gate shift clock (GSC), a gate start pulse (GSP), a gate output enable (GOE), and the like, which are supplied to the gate driver 53. The second display control signal may be divided into a source shift clock (SSC), a source start pulse (SSP), a source output enable (SOE), and the like.

Meanwhile, the DC-DC converter 55 converts a single DC voltage of a predetermined range input from a power supply unit (not shown) into a DC voltage having a predetermined size, that is, a reference supply voltage Vdd, to the voltage generator 56. Supply it.

The voltage generator 56 supplies a common driving voltage of the gate driver 53, the data driver 54, and the liquid crystal panel 40 by using the reference supply voltage to generate a joule driving voltage (eg, a high potential gate voltage Vgh). ), Low potential gate voltage (Vgl), data voltage (Vdata), common voltage (Vcom). In this case, the voltage generator 56 supplies a common reset voltage Vcom_reset to the common electrode of the liquid crystal panel 40 during the reset period in addition to the driving voltage.

Accordingly, the voltage generator 56 may generate a high potential gate voltage Vgh, a low potential gate voltage Vgl, a data voltage Vdata, a common voltage Vcom, a reset common voltage Vcom_reset, and the like. .

For convenience of description, the high potential gate voltage Vgh is 20V, the low potential gate voltage Vgl is -5V, the data voltage Vdata is 10V, the common voltage Vcom is 5V, and the reset common voltage Vcom_reset. ) Is set to 0V.

In this case, the driving voltage generated by the voltage generator 56 (high potential gate voltage Vgh, low potential gate voltage Vgl, data voltage Vdata, common voltage Vcom, etc.) and the reset common voltage are the same. The timing controller 52 is varied according to the reset control signal and the display control signal generated differently according to the reset section and the display section so as to be supplied to the gate driver 53, the data driver 54, and the liquid crystal panel 40. do.

To this end, the liquid crystal display includes a first switch 57 connected between the voltage generator 56, the gate driver 53, and the data driver 54, the voltage generator 56, and the data driver ( 54 and a second switch 58 connected between the first switch 57 and a third switch 59 connected between the voltage generator 56 and the liquid crystal panel 40, respectively. Can be.

At this time, the timing controller 52 simultaneously supplies the reset control signal during the reset period and the display control signal during the display period to the first to third switches 57 to 59, respectively. Accordingly, all of the first to third switches 57 to 59 are supplied from the voltage generator 56 under the control of the reset control signal and the display control signal generated by the timing controller 52. Switch to change the output path of voltages Vgh, Vdata, Vcom, Vcom_reset.

The first switch 57 is controlled by the reset control signal generated from the timing controller 52 during the reset period so that the data voltage Vdata generated from the voltage generator 56 is applied to the gate driver 53 and the gate switch 53. The high potential gate voltage Vgh generated from the voltage generator 56 is controlled to be supplied to the data driver 54 and is controlled by the display control signal generated by the timing controller 52 when the display period is changed. It is switched to be supplied to the gate driver 53.

The second switch 58 is controlled by the reset control signal generated from the timing controller 52 during the reset period so that the data voltage Vdata generated from the voltage generator 56 is the first switch 57. When the display period is changed, the data voltage generated by the voltage generator 56 is supplied to the data driver 54 under the control of the display control signal generated by the timing controller 52. do.

The third switch 59 is controlled by the reset control signal generated from the timing controller 52 during the reset period, so that the reset common voltage Vcom_reset generated from the voltage generator 56 is applied to the liquid crystal panel 40. When switching to be supplied to the display section, and the display section is a display period, the common voltage Vcom generated from the voltage generator 56 is controlled by the display control signal generated by the timing controller 52 to the liquid crystal panel 40. It is switched to be supplied.

At this time, the data voltage Vdata generated from the voltage generator 56 by switching the first and second switches 57 and 58 is reset to the gate driver 53 and the data driver 54 in the reset period. The data voltage Vdata supplied to the gate driver 53 and the data driver 54 is bypassed as it is and is supplied to the liquid crystal panel 40. Accordingly, the same data voltage Vdata is supplied to the gate lines and the pixel electrodes of the liquid crystal panel 40 in the reset section, and is also driven from the voltage generator 56 by switching of the third switch 59. The generated reset common voltage Vcom_reset (lower than common voltage Vcom) is supplied. Therefore, the same data voltage Vdata is applied to the gate line and the pixel electrode of the liquid crystal panel 40 so that there is no potential difference therebetween, so that no transverse electric field is generated and the liquid crystals in the splay state are bent more quickly. Can be initialized with. In addition, the reset common voltage Vcom_reset, which is 0V, is lower than the common voltage Vcom of 5V, thereby making the potential difference between the pixel electrode and the common electrode larger, thereby further facilitating rapid initialization of the liquid crystal layer.

In the display section, the high potential gate voltage Vgh is supplied to the gate driver 53 by the first switch 57, and the data voltage Vdata is supplied by the second switch 58. 54, and the common voltage Vcom is applied to the common electrode of the liquid crystal panel 40 by the third switch 59.

The process of displaying a predetermined image on the liquid crystal panel 40 using the high potential gate voltage Vgh, the data voltage Vdata, and the common voltage Vcom supplied as described above is the same as a conventional driving method.

That is, when the reset section has elapsed in the timing controller 52 to become the display section, the first display control signals GSC, GSP, and GOE are supplied to the gate driver 53, and the second display control signal SSC is provided. , SSP and SOE and digital image data R, G, and B are supplied to the data driver 54. At the same time, a display control signal is supplied from the timing controller 52 to the first to third switches 57 to 59 to be controlled by the display control signal, and the high potential gate voltage is controlled by the first switch 57. Vgh is supplied to the gate driver 53, the data voltage Vdata is supplied to the data driver 54 by the second switch 58, and the common voltage (V) is supplied by the third switch 59. Vcom) is applied to the common electrode of the liquid crystal panel 40.

In this case, the gate driver 53 sequentially applies the high potential gate voltage Vgh output from the first switch 57 to the liquid crystal panel 40 under the control of the first display control signal. Under the control of the second display control signal, the data driver 54 generates the data voltage Vdata output from the second switch 58 as a gradation voltage according to the gradation value and supplies it to the liquid crystal panel 40. do. Therefore, the gray voltage is supplied on the gate line in synchronization with the high potential gate voltage Vgh being sequentially applied to the gate lines of the liquid crystal panel 40, and the potential difference between the gray voltage and the common voltage is applied to the gate lines. As a result, the liquid crystal layer is controlled to display a predetermined image.

In FIG. 7, the first and second switches 57 and 58 are configured to supply the same data voltage Vdata to the gate driver 53 and the data driver 54 during the reset period. The first and second switches 57 and 58 may be configured to supply the same high potential gate voltage Vgh to the data driver 54. As such, the same high potential gate voltage Vgh is supplied to the pixel electrode of the liquid crystal panel 40 through the gate driver 53 and the data driver 54 by the first and second switches 57 and 58. As a result, not only the transverse electric field is removed, but also a faster initialization can be performed by increasing the potential difference between the pixel electrode and the reset common voltage Vcom_reset.

Hereinafter, a method of driving a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to FIG. 8.

8 is a view illustrating waveforms of voltages in the OSC mode in accordance with the present invention.

As described above, in order to display an image on the screen in the LCD having the OSC mode, the display is driven by being divided into a reset section and a display section. Here, the reset section represents a section for initializing the splay state of the liquid crystal layer to the bend state before displaying an image on the screen, and the display section represents a section for displaying a predetermined image by controlling the liquid crystal layer initialized to the bend state. .

First, the data voltage Vdata is controlled by the first and second switches 57 and 58 under the control of the reset control signal supplied from the timing controller 52 during the reset period, and the gate driver 53 and the data driver 54. The reset common voltage Vcom_reset is supplied to the liquid crystal panel 40 by the third switch 59. In this case, the gate driver 53 and the data driver 54 bypass the data voltage as they are and supply the liquid crystal panel 40.

Accordingly, the same data voltage Vdata of 10 V is applied to the pixel electrodes and the gate lines of the liquid crystal panel 40, and a reset common voltage Vcom_reset of 0 V is applied to the common electrode of the liquid crystal panel 40. Will be. Therefore, there is no potential difference between the gate lines and the pixel electrodes, and thus the transverse electric field is eliminated, thereby quickly initializing the liquid crystals in the splay state to the liquid crystals in the bend state. The reset common voltage Vcom_reset, which is lower than the common voltage Vcom, is applied to the common electrode of the liquid crystal panel 40 so that the potential between the pixel electrodes and the common electrode becomes larger, thereby initializing the liquid crystal layer. It can be faster to implement fast initialization faster.

When the initialization to the bend state is completed during such a reset period, the high potential gate voltage Vgh is controlled by the first switch 57 under the control of the display control signal supplied from the timing controller 52 during the display period. The data voltage Vdata by the second switch 58 and the common voltage Vcom by the third switch 59 respectively correspond to the gate driver 53, the data driver 54 and the liquid crystal panel 40. Is supplied.

In addition, the high potential gate voltage Vgh is sequentially supplied from the gate driver 53 to the liquid crystal panel 40 by the display control signal generated from the timing controller 52, while the data driver The data voltage Vdata is generated as a gray voltage corresponding to the gray value from 54, and is supplied to the liquid crystal panel 40.

Accordingly, the thin film transistors connected to the respective gate lines of the liquid crystal panel 40 are turned on by the sequentially supplied high potential gate voltage Vgh, and the grayscale voltage is applied through the turned on thin film transistors to make the pixel. Applied to the electrodes. Therefore, the liquid crystal layer is controlled by the potential difference between the gradation voltage of the pixel electrode and the common voltage Vcom of the common electrode to vary the light transmittance so that a predetermined image is displayed.

Accordingly, the present invention may apply the same voltage to the gate lines and the pixel electrodes during the reset period, and apply a lower reset common voltage Vcom_reset to the common electrode, thereby implementing a faster initialization.

As described above, according to the present invention, the same voltage is applied to the gate lines and the pixel electrodes, thereby eliminating the transverse electric field therebetween, so as to quickly transition from the splay state to the bend state during the reset period, thereby enabling rapid initialization. Can be implemented.

At this time, a lower reset common voltage Vcom_reset may be applied to the common voltage, thereby facilitating initialization by a larger potential difference.

Claims (13)

A plurality of gate lines arranged in a first direction; A plurality of data lines arranged in a second direction perpendicular to the plurality of gate lines; A plurality of thin film transistors formed at intersections of the gate lines and data lines; And A plurality of pixel electrodes connected to the thin film transistors, respectively Array substrate comprising a, An opposite substrate facing the array substrate and provided with a common electrode; A liquid crystal layer in which liquid crystals controlled in an OSC mode are filled between the array substrate and the opposite substrate Made of The OSC mode is driven by being divided into a reset section for initializing the liquid crystals and a display section for displaying a predetermined image by controlling the initialized liquid crystals, and the plurality of gate lines and the plurality of pixels when the reset period is driven. The liquid crystal panel for the OSC mode, characterized in that the same voltage is applied to the electrodes. The liquid crystal panel of claim 1, wherein a reset common voltage lower than a common voltage is applied to the common electrode when the reset section is driven. The liquid crystal panel of claim 1, wherein the same voltage is one of a high potential gate voltage and a data voltage. The display device of claim 1, wherein the high potential gate voltage is sequentially applied to the plurality of gate lines during driving of the display period, and a gray voltage corresponding to the gray value of the data voltage is applied to the plurality of pixel electrodes. The liquid crystal panel for the OSB mode, characterized in that the common voltage is applied to the common electrode. And a plurality of gate lines and a plurality of data lines vertically intersected, a plurality of thin film transistors formed at intersections of the gate lines and the data lines, and a plurality of pixel electrodes connected to the thin film transistors, respectively. An LCD substrate for an OSC mode including an array substrate, a counter substrate facing the array substrate and provided with a common electrode, and a liquid crystal layer filled with liquid crystals controlled in an OSC mode between the array substrate and the opposing substrate; A voltage generator generating voltages for driving the liquid crystal panel; A timing controller for generating a reset control signal for initializing the liquid crystal during a reset period and a display control signal for displaying a predetermined image during the display period; Switching means for switching such that an output path of voltages generated from the voltage generator is changed according to the reset control signal and the display control signal; And A gate driver and a data driver for driving the liquid crystal panel using switching changed voltages in the switching means, And the same voltage is applied to the plurality of gate lines and the plurality of pixel electrodes during the reset period. The method of claim 5, wherein the switching unit supplies the same voltage among the voltages generated from the voltage generator to the gate driver and the data driver under the control of the reset control signal, and resets the common voltage to the common electrode. Liquid crystal display, characterized in that switched to supply. 7. The liquid crystal display device according to claim 6, wherein the same voltage is one of a high potential gate voltage and a data voltage. 7. The liquid crystal display device according to claim 6, wherein the same voltage switched by the switching means is supplied to the liquid crystal panel via the gate driver and the data driver. The switching device of claim 5, wherein the switching means supplies a high potential gate voltage among the voltages generated from the voltage generator to the gate driver under the control of the display control signal, and supplies a data voltage to the data driver. And switch to supply a common voltage greater than the reset common voltage to the common electrode. And a plurality of gate lines and a plurality of data lines vertically intersected, a plurality of thin film transistors formed at intersections of the gate lines and the data lines, and a plurality of pixel electrodes connected to the thin film transistors, respectively. A liquid crystal panel for an OSC mode including an array substrate, an opposing substrate facing the array substrate and provided with a common electrode, and a liquid crystal layer filled with liquid crystals controlled in an OSC mode between the array substrate and the opposing substrate. In the driving method of a liquid crystal display device for driving, Generating a reset control signal for a reset section and a display control signal for a display section; When driving the reset section, the same voltage among the voltages generated from the voltage generator is output to the plurality of gate lines and the pixel electrodes of the liquid crystal panel under the control of the reset control signal, and a reset common voltage is applied to the liquid crystal panel. First switching to be output to the common electrode; Initializing the liquid crystals of the liquid crystal panel by the same voltage and the reset common voltage; Performing a second switching to output a high potential gate voltage, a data voltage, and a common voltage among the voltages generated from the voltage generator under control of the display control signal when driving a display section; And Displaying an image on the liquid crystal panel using the high potential gate voltage, the data voltage, and the common voltage; Method of driving a liquid crystal display device comprising a. The method of claim 10, wherein the same voltage is one of a gate high potential voltage and a data voltage, and is simultaneously applied to a plurality of gate lines and a plurality of pixel electrodes of the liquid crystal panel. . The method of claim 10, wherein the reset common voltage has a lower level voltage than the common voltage. The liquid crystal panel of claim 10, wherein the high potential gate voltage is sequentially supplied to the liquid crystal panel by a gate driver when the display period is driven, and the data voltage is changed into a gray voltage according to a gray value by a data driver. The common voltage is supplied to the common electrode of the liquid crystal panel.

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