KR100605783B1 - Out pulse controling circuit - Google Patents

Abstract

The present invention relates to an output pulse control circuit, comprising: a first pulse control unit for selectively outputting a first pulse signal in response to an input signal and increasing a pulse width of an input signal by a predetermined size according to a first specific signal; A second pulse control unit for selectively outputting a second pulse signal in which the pulse width of the first pulse signal is increased by a predetermined magnitude by receiving the first pulse signal according to the second specific signal, and receiving the second pulse signal Receives and latches the third pulse control unit for selectively outputting the third pulse signal having increased the pulse width of the second pulse signal by a predetermined size according to the third specific signal and the first, second and third pulse signals. It is provided with a latch unit for outputting, it is characterized in that the pulse width can be easily adjusted.

Description

Output pulse control circuit

1 is a conventional output pulse control circuit diagram.

2 is an output pulse control circuit diagram according to an embodiment of the present invention.

3 is a timing diagram when the specific signal S1 is enabled according to an embodiment of the present invention.

4 is a timing diagram when the specific signal S2 is enabled according to an embodiment of the present invention.

5 is a timing diagram when the specific signal S3 is enabled according to an embodiment of the present invention.

The present invention relates to an output pulse control circuit, and more particularly, to an output pulse control circuit capable of easily adjusting a pulse width by receiving a specific signal from the outside.

As the speed of the semiconductor memory device increases, the operating frequency increases, and accordingly, the period of signals using pulses involved in the internal operation is shortened. In proportion to this, the width of the pulse signal is also reduced. However, current semiconductor memory devices are continuously increasing in speed, and thus the period of pulses is gradually reduced.

The pulses should be designed to have a sufficient width to enable high speed operation of the semiconductor memory device. However, the width of the pulse is further reduced in high voltage tests such as burn in tests or fast conditions.

This may cause problems such as failure to maintain sufficient pulse width or missing pulses in the operation of the device. This problem can be more serious for SDRAM operating in synchronization with the clock.

A conventional output pulse circuit for this purpose will be described with reference to FIG.

The conventional output pulse control circuit is composed of inverters I1 to I6, PMOS capacitor CA1, NMOS capacitor CA2, and metal options M1 to M4.

As described above, the conventional output pulse adjusting circuit adjusts the pulse width by adding a PMOS capacitor or an NMOS capacitor to a delay unit formed of an inverter chain.

As described above, the conventional output pulse control circuit is in the form of a metal option using a physical switch, and thus, it is difficult to arbitrarily adjust the pulse width in the state of manufacturing a wafer or the package.

That is, the output pulse width should be adjusted by arbitrarily modifying the circuit, using a FIB (Focus Ion Beam) device, or replacing a mask to arbitrarily adjust the output pulse width. Therefore, there was a problem that the cost is consumed accordingly.

 An object of the present invention for solving the above problems is to be able to easily adjust the pulse width using a specific test signal.

The present invention for achieving the above object is a first pulse control unit for receiving an input signal and selectively outputs the first pulse signal to increase the pulse width of the input signal by a predetermined size according to the first specific signal; A second pulse control unit receiving the first pulse signal and selectively outputting a second pulse signal in which the pulse width of the first pulse signal is increased by a predetermined magnitude according to the second specific signal; A third pulse control unit receiving a second pulse signal and selectively outputting a third pulse signal in which the pulse width of the second pulse signal is increased by a predetermined size according to the third specific signal; And a latch unit configured to receive and latch the first, second, and third pulse signals and output the latch signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an output pulse control circuit diagram according to an embodiment of the present invention.

As shown in FIG. 2, the output pulse control circuit is comprised of the pulse control parts 10, 20, 30, and the latch part 40. As shown in FIG.

The first pulse controller 10 includes a first delay unit 11, a first NOR gate NOR1, a first inverter I11, and a first transfer unit 12.

The first delay unit 11 is composed of a plurality of inverter chains I7 to I10 to delay the input signal IN.

The first NOR gate NOR1 receives the non-delayed input signal IN and the delayed input signal IN through the first delay unit 11, performs a noah operation, and outputs it.

The first transfer unit 12 includes a transmission gate TG1 and an inverter I12, and outputs an output of the inverted first NOR gate NOR1 to the node K through the first inverter I11. At this time, the transmission gate TG1 is controlled by the specific signal S1 input from the outside. That is, the transmission gate TG1 is driven when the specific signal S1 is enabled.

The second pulse controller 20 includes a second delay unit 21, a second NOR gate NOR2, a second inverter I17, and a second transfer unit 22.

The second delay unit 21 is composed of a plurality of inverter chains I13 to I16 to delay the input signal IN.

The second NOR gate NOR2 receives the non-delayed input signal IN and the delayed input signal IN through the second delay unit 21 to perform the NOA operation and output the received NO.

The second transfer unit 22 includes a transmission gate TG2 and an inverter I18, and outputs the output of the second NOR gate NOR2 that is inverted through the inverter I17 to the node K. At this time, the transmission gate TG2 is controlled by the specific signal S2 input from the outside. That is, the transmission gate TG2 is driven when the specific signal S2 is enabled.

The third pulse controller 30 includes a third delay unit 31, a third NOR gate NOR3, a third inverter I23, and a third transfer unit 32.

The third delay unit 31 is composed of a plurality of inverter chains I19 to I22 to delay the input signal IN.

The third NOR gate NOR3 receives the non-delayed input signal IN and the delayed input signal IN through the third delay unit 31 to perform the NOA operation and output it.

The third transfer part 32 includes a transmission gate TG3 and an inverter I24, and outputs an output of the third noah gate NOR3 inverted through the third inverter I23 to the node K. At this time, the transmission gate TG3 is controlled by the specific signal S3 input from the outside. That is, the transmission gate TG3 is driven when the specific signal S3 is enabled.

The latch unit 40 maintains the logic state of the node K by using the inverters I25 to I26. That is, the latch unit 40 prevents the output of the node K from floating. The output of the latch unit 40 is inverted through the inverter I27 and output as the output signal OUT.

3 is a timing diagram when the specific signal S1 according to the embodiment of the present invention is enabled, and shows a timing diagram of the output signals of the nodes A to K in FIG.

When the specific signal S1 is enabled, it can be seen that the output curve of the node E of the first pulse controller 10 and the total output curve of the node K are similar. That is, when the specific signal S1 is enabled, the pulse width is increased by the first delay unit 11 of the first pulse control unit 10, and the output extended by the first delay unit 11 is applied to the latch unit 40. Through the output signal (OUT) through.

4 is a timing diagram when the specific signal S2 according to the embodiment of the present invention is enabled, and shows a timing diagram of the output signals of the nodes A to K in FIG.

When the specific signal S2 is enabled, the output of the node E enters the input of the second pulse controller 20. The pulse width of the node E is increased by the second delay unit 21, and is output to the node K through the second transfer unit 22.

FIG. 5 is a timing diagram when the specific signal S3 according to the embodiment of the present invention is enabled, and shows a timing diagram of output signals of the nodes A to K in FIG.

When the specific signal S3 is enabled, the output of the node G enters the input of the third pulse controller 30. The output of the node G is increased in pulse width by the third delay unit 31, and is output to the node K through the third transfer unit 32.

That is, when the specific signal S3 is enabled, all of the delay units 11, 12, 13 pass through, and the pulse width is increased the most, so that the output signal OUT having a wide pulse width is output.

In this way, by using the specific signals (S1, S2, S3), the pulse width can be adjusted depending on how many input signals (IN) pass through the pulse control unit (10, 20, 30), to make the desired pulse width It may be provided with a plurality of pulse control unit.

As described above, the output pulse adjusting circuit according to the present invention has an effect of easily adjusting the pulse width.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

A first pulse control unit receiving an input signal and selectively outputting a first pulse signal in which the pulse width of the input signal is increased by a predetermined size according to a first specific signal; A second pulse control unit receiving the first pulse signal and selectively outputting a second pulse signal in which the pulse width of the first pulse signal is increased by a predetermined magnitude according to a second specific signal; A third pulse control unit receiving the second pulse signal and selectively outputting a third pulse signal in which the pulse width of the second pulse signal is increased by a predetermined magnitude according to a third specific signal; And And a latch unit configured to receive and latch and output the first, second, and third pulse signals. According to claim 1, wherein the first pulse control unit A delay unit composed of a plurality of inverter chains to delay and output the input signal; Logic operation means for receiving a logic operation by receiving the input signal and the output of the delay unit; And  And a transmission unit having a transmission gate controlled by the first specific signal and an inverting means, for transmitting an output of the logic operation means. The method of claim 1, wherein the second pulse control unit A delay unit composed of a plurality of inverter chains to delay and output the input signal; Logic operation means for receiving a logic operation by receiving the input signal and the output of the delay unit; And  And a transmission unit having a transmission gate controlled by the second specific signal and an inverting means, for transmitting an output of the logic operation means. According to claim 1, wherein the third pulse control unit A delay unit composed of a plurality of inverter chains to delay and output the input signal; Logic operation means for receiving a logic operation by receiving the input signal and the output of the delay unit; And  And a transmission unit having a transmission gate controlled by the third specific signal and an inverting means to transfer an output of the logic operation means.

Images