KR100604043B1 - Semicondoctor device and its fabrication method - Google Patents
Semicondoctor device and its fabrication method Download PDFInfo
- Publication number
- KR100604043B1 KR100604043B1 KR1020030027104A KR20030027104A KR100604043B1 KR 100604043 B1 KR100604043 B1 KR 100604043B1 KR 1020030027104 A KR1020030027104 A KR 1020030027104A KR 20030027104 A KR20030027104 A KR 20030027104A KR 100604043 B1 KR100604043 B1 KR 100604043B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- manufacturing
- ion implantation
- semiconductor device
- annealing
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000001816 cooling Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 32
- 238000005468 ion implantation Methods 0.000 abstract description 22
- 238000009792 diffusion process Methods 0.000 abstract description 17
- 239000002019 doping agent Substances 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 12
- 239000010408 film Substances 0.000 abstract description 5
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000004904 shortening Methods 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 5
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체 소자 제조 방법에 관한 것으로, 보다 자세하게는 소정의 구조물이 형성된 기판에 이온주입 하는 제 1공정, 상기 기판에 압축응력이 걸린 박막을 증착시키는 제 2공정, 상기 기판을 스파이크 급속 열처리시키는 제 3공정을 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.반도체 소자 제조 공정 중, 이온주입 후 어닐링 공정에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a first step of ion implantation into a substrate on which a predetermined structure is formed, a second step of depositing a thin film subjected to compressive stress on the substrate, and a rapid rapid heat treatment of the substrate. And a third step. The present invention relates to an annealing step after ion implantation during a semiconductor device manufacturing step.
본 발명의 상기 목적은 소정의 구조물이 형성된 기판에 이온주입 하는 제 1공정; 상기 기판에 압축응력이 걸린 박막을 증착시키는 제 2공정; 및 상기 기판을 어닐링시키는 제 3공정을 특징으로 하는 반도체 소자 및 그의 제조 방법에 의해서 달성된다.The above object of the present invention is a first step of ion implantation into a substrate on which a predetermined structure is formed; Depositing a thin film subjected to compressive stress on the substrate; And a third step of annealing the substrate, and a manufacturing method thereof.
따라서, 본 발명의 반도체 소자의 제조 방법은 압축응력이 걸린 박막 필름을 플라스마 화학기상증착법으로 증착하여 어닐링 하여 TED의 근본 원인인 침입형 실리콘 원자의 확산 방향을 표면 방향으로 유도함으로써, 확산에 동반된 도펀트에 의한 도핑 깊이 증가를 근본적으로 제거하여 65nm이하 기술에서 문제가 되고 있는 정션 형성 방법에 사용할 수 있다.Therefore, in the method of manufacturing a semiconductor device of the present invention, the thin film film subjected to the compressive stress is deposited by annealing by plasma chemical vapor deposition and annealed to induce the diffusion direction of the invasive silicon atoms, which is the root cause of TED, to the surface direction. It can fundamentally eliminate the increase in doping depth caused by the dopant and can be used in the junction formation method which is a problem in the technology of 65 nm or less.
또한, 이미 양산공정에 적용되고 있는 기존 기술(이온주입, RTA)을 그대로 사용할 수 있다는 점에서 기술개발기간단축, 개발비용절감, 생산비용절감 등의 장점이 있다.In addition, the existing technology (ion implantation, RTA) that is already applied to the mass production process can be used as it is, there are advantages such as shortening the technology development period, development cost reduction, production cost reduction.
압축응력, junction depth, 이온주입, RTACompressive stress, junction depth, ion implantation, RTA
Description
도 1 내지 도 2는 본 발명에 따른 반도체 제조 방법의 공정도.1 to 2 are process drawings of a semiconductor manufacturing method according to the present invention.
도 3은 본 발명에 따른 반도체 소자의 제조 공정의 플로우차트.3 is a flowchart of a manufacturing process of a semiconductor device according to the present invention;
본 발명은 반도체 소자 제조 방법에 관한 것으로, 보다 자세하게는 반도체 소자 제조 공정 중, 이온주입 후 어닐링 공정에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an annealing process after ion implantation in a semiconductor device manufacturing process.
종래의 어닐링(annealing) 방법은 주로 서크(soak) 어닐링 방법으로, 이 방법을 사용할 경우, 130nm기술이 적용 한계로 알려져 있다. 이를 극복하기 위하여, 다양한 어닐링 방법이 제안되었으나 상용화할 수 있는 것은 스파이크(spike) 어닐링 방법 이외에는 없다.The conventional annealing method is mainly a soak annealing method. When this method is used, 130 nm technology is known as an application limit. In order to overcome this, various annealing methods have been proposed, but there is nothing other than a spike annealing method that can be commercialized.
스파이크 어닐링은 기존의 어닐링 방법과 비교할 때, 상대적으로 어닐링 시간이 짧고, 어닐링 온도가 높다.Spike annealing has a relatively short annealing time and a high annealing temperature when compared with the conventional annealing method.
일반적으로 스파이크 어닐링의 온도는 1050℃ 이상이며, 서크 어닐링의 온도는 1020℃ 이하이다.Generally, the temperature of spike annealing is at least 1050 ° C, and the temperature of spike annealing is at most 1020 ° C.
스파이크 어닐링이 통상적인 서크 어닐링보다 도핑 깊이가 작은 경우에 적합한 이유는 다음과 같다.The reason why spike annealing is suitable in the case where the doping depth is smaller than a conventional spike annealing is as follows.
어닐링의 목적은 크게 두 가지로 나눌 수 있다.The purpose of annealing can be largely divided into two.
첫째, 이온주입과정에 발생한 결함의 제거이다.First is the elimination of defects that occur during ion implantation.
둘째, 이온주입된 도펀트의 활성화(activation)이다. Second is the activation of ion implanted dopants.
여기서, 주목해야할 점은 이온주입 중 다량 발생하는 실리콘 침입형 원자의 거동이다. 실리콘 침입형 원자는 확산 시 도펀트(dopant)의 일부를 동반하여, 도핑 깊이를 증가시키는 효과(transient enhanced diffusion : TED)가 나타난다.Here, it should be noted that the behavior of silicon interstitial atoms generated in large quantities during ion implantation. Silicon invasive atoms are accompanied by a portion of the dopant upon diffusion, resulting in a transition enhanced diffusion (TED).
통상적인 어닐링 온도와 스파이크 어닐링 온도에서의 확산계수변화를 비교하면, 도펀트의 확산계수에는 큰 차이가 없는 반면에 실리콘 침입형 원자의 확산 계수는 고온에서 약 1.5배 증가한다. Comparing the diffusion coefficient change at the conventional annealing temperature and the spike annealing temperature, there is no significant difference in the diffusion coefficient of the dopant, while the diffusion coefficient of the silicon interstitial atoms increases about 1.5 times at high temperature.
따라서, 고온에서 어닐링을 할 경우, 도펀트의 확산속도 증가보다는 침입형 원자의 확산속도 증가가 더 두드러져, 빠른 시간 내에 결함은 사라지고, 도펀트만의 확산이 진행되는 현상이 나타난다. Therefore, when annealing at high temperature, the diffusion rate of the invading atoms is more pronounced than the diffusion rate of the dopant, so that the defect disappears quickly and the diffusion of the dopant only appears.
따라서, 짧은 시간(0.1초 이하)의 고온 어닐링을 실시하여, 효과적으로 이온주입 결함을 제거함과 동시에 도펀트의 확산 거리도 줄여주는 것이 스파이크 어닐링의 원리라고 할 수 있다. 더불어, 온도가 높을수록 도펀트 중에서 활성화되는 비율이 증가하여, 저항도 낮추어 주는 효과도 나타난다. Therefore, the principle of spike annealing is to perform high temperature annealing for a short time (0.1 sec or less), effectively eliminating ion implantation defects, and reducing the diffusion distance of the dopant. In addition, as the temperature increases, the rate of activation in the dopant increases, thereby lowering the resistance.
하지만 위와 같은 장점에도 불구하고, 스파이크 어닐링은 한계를 가지고 있다. Despite the above advantages, however, spike annealing has its limitations.
즉, 이온주입되는 도펀트의 양이 증가(1014atom/㎠ 이상)하고, 깊이가 감소하는 경우(보통의 경우, 1keV이하)에는 결함의 밀도가 높아, 도펀트를 동반한 실리콘 침입형 원자의 확산현상이 스파이크 어닐링 조건에서도 발생한다.In other words, when the amount of dopant implanted is increased (10 14 atoms / cm 2 or more) and the depth is decreased (usually 1 keV or less), the density of defects is high, and diffusion of silicon invading atoms accompanying the dopant is high. The phenomenon also occurs in spike annealing conditions.
이러한 결과로, 스파이크 어닐링으로 구현할 수 있는 정션(junction)의 깊이는 25nm이상으로 알려져 있다.As a result, the depth of the junction that can be realized by spike annealing is known to be 25 nm or more.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 이온주입 후 플라즈마 화학기상증착법(plasma-enhanced chemical vapor deposition : PECVD)으로 압축응력이 걸린 산화물(oxide) 또는 질화물(nitride)을 증착시키고, 표면에 응력이 걸린 상태에서 어닐링을 하여, TED의 근본 원인인 침입형 실리콘 원자의 확산 방향을 표면 방향으로 유도함으로써, 확산에 동반된 도펀트에 의한 도핑 깊이 증가를 근본적으로 제거하도록 하는 반도체 소자의 제조 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, after the ion implantation of the oxide (oxide) or nitride (nitride) subjected to compressive stress by plasma-enhanced chemical vapor deposition (PECVD) A semiconductor that is deposited and annealed under stress on the surface to induce the diffusion direction of an invasive silicon atom, which is the root cause of the TED, toward the surface, thereby essentially eliminating the increase in the doping depth caused by the dopant accompanying diffusion. It is an object of the present invention to provide a method for manufacturing a device.
본 발명의 상기 목적은 소정의 구조물이 형성된 기판에 이온주입 하는 제 1공정, 상기 기판에 압축응력이 걸린 박막을 증착시키는 제 2공정, 상기 기판을 스파이크 급속 열처리시키는 제 3공정을 특징으로 하는 반도체 소자 및 그의 제조 방법에 의해서 달성된다.The above object of the present invention is a semiconductor comprising a first step of ion implantation into a substrate having a predetermined structure, a second step of depositing a thin film subjected to compressive stress on the substrate, and a third step of rapidly heat-treating the substrate. It is achieved by the device and its manufacturing method.
본 발명은 반도체 제조 공정 중, 이온주입 후 어닐링 공정에 관한 것으로, 웨이퍼의 표면에 얇게(30nm이하)하여 주는 경우에 사용할 수 있다. The present invention relates to an annealing process after ion implantation in a semiconductor manufacturing process, and can be used when the surface of a wafer is made thin (30 nm or less).
본 발명에서 제안하는 공정을 적용하면, 현재 65nm이하 기술에서 문제가 되고 있는 정션 깊이 20nm 이하의 소자를 쉽게 구현할 수 있다.By applying the process proposed in the present invention, it is possible to easily implement devices with a junction depth of 20 nm or less, which is currently a problem in the technology of 65 nm or less.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
도 1은 소정의 구조물이 형성된 기판에 이온 주입 공정을 행하는 공정도이다.1 is a process chart for performing an ion implantation process on a substrate on which a predetermined structure is formed.
채널을 형성하기 위하여 게이트가 형성된 기판에 LDD 이온 주입 공정 또는 S/D(Source/Drain) 이온 주입 공정을 한다.In order to form a channel, an LDD ion implantation process or a source / drain (S / D) ion implantation process is performed on the gated substrate.
이온주입시 도핑 깊이를 얇게 하기 위하여 수 nm깊이로 이온 주입 공정을 행한다. In order to reduce the doping depth at the time of ion implantation, an ion implantation process is performed to several nm depth.
도 2는 이온 주입 공정이 끝난 기판에 산화물 또는 질화물을 증착하는 공정도이다.2 is a process diagram for depositing an oxide or nitride on the substrate after the ion implantation process.
최근 새롭게 발표된 PE-CVD방법을 사용하면, 압축응력이 걸린 산화물 또는 질화물 필름을 증착할 수 있다. 이러한 필름을 실리콘웨이퍼 위에 증착하면, 실리 콘웨이퍼 표면에는 인장응력이 인가된다.Using the recently announced PE-CVD method, it is possible to deposit oxide or nitride films subjected to compressive stress. When such a film is deposited on a silicon wafer, a tensile stress is applied to the silicon wafer surface.
상기 웨이퍼에 인장응력을 걸면, 웨이퍼의 재질인 실리콘 원자간의 거리가 증가하여 실리콘 침입형 원자는 결정 내에서 원자간 거리가 큰 방향으로 이동한다.When the tensile stress is applied to the wafer, the distance between silicon atoms, which is a material of the wafer, increases, and the silicon invading atoms move in a direction in which the interatomic distance is large within the crystal.
따라서, 상기 압축응력이 걸린 산화물 또는 질화물 필름을 웨이퍼 표면에 증착시킨 상태에서 어닐링을 실시하면 실리콘 침입형 원자가 웨이퍼의 표면 쪽으로 이동한다.Therefore, when annealing is performed while the oxide or nitride film subjected to the compressive stress is deposited on the wafer surface, silicon invasive atoms move toward the surface of the wafer.
상기와 같은 방법으로 TED의 근본 원인인 침입형 실리콘 원자의 확산 방향을 표면 방향으로 유도함으로써, 확산에 동반된 도펀트에 의한 도핑 깊이 증가를 근본적으로 제거할 수 있다.In this way, by inducing the diffusion direction of the invasive silicon atoms, which is the root cause of the TED, to the surface direction, it is possible to fundamentally eliminate the increase in the doping depth caused by the dopant accompanying diffusion.
따라서, 순수한 도펀트 자체의 확산현상으로 도핑 깊이가 결정되므로 10nm 수준의 정션 깊이도 구현 가능하여, 65nm 기술은 물론 35nm 기술에까지 적용 가능한 정션을 형성할 수 있다.Therefore, since the doping depth is determined by the diffusion phenomenon of pure dopant itself, it is possible to implement a junction depth of 10 nm level, thereby forming a junction applicable to 65 nm technology as well as 35 nm technology.
정션 깊이(junction depth)의 조절을 위하여 압축 응력이 걸린 질화물 또는 산화물을 소정의 구조물이 형성된 기판에 증착하여 어닐링 하여 원하는 정션 깊이를 가지는 반도체 소자를 제조할 수 있다.In order to adjust the junction depth, a semiconductor device having a desired junction depth may be manufactured by depositing and annealing a nitride or oxide subjected to compressive stress on a substrate having a predetermined structure.
일 실시예로 상기 압축응력이 걸리는 질화물은 PE-nitride이고, Si 표면에 발생하는 결함과 스페이서(spacer)구조와의 연관성을 고려할 때 상기 압축응력이 걸리는 산화물은 PE-TEOS가 적당하다.In one embodiment, the compressive stress nitride is PE-nitride, and considering the correlation between defects occurring on the Si surface and the spacer structure, the compressive stress oxide is preferably PE-TEOS.
상기 증착공정은 PE-CVD을 이용하여 압축응력이 걸린 산화물 또는 질화물을 증착시킨다. 이때, 증착온도는 400-500℃로 한다.The deposition process uses PE-CVD to deposit oxides or nitrides subjected to compressive stress. At this time, the deposition temperature is 400-500 ℃.
상기 PE-CVD로 증착된 질화물 또는 산화물의 두께는 4~50nm이다.The nitride or oxide deposited by PE-CVD is 4-50 nm thick.
산화물 또는 질화물이 100nm이상의 두께로 증착될 경우에는 채널에 영향을 줄 수 있다.If oxides or nitrides are deposited to a thickness of 100 nm or more, the channel may be affected.
산화물 또는 질화물을 증착시킨 기판을 어닐링 실시하는데 상기 어닐링은 스파이크 급속 열처리(Spike Rapid Thermal Annealing)가 적당하다.The annealing is performed on the substrate on which the oxide or nitride is deposited. Spike Rapid Thermal Annealing is suitable for the annealing.
상기 스파이크 급속 열처리의 조건은 온도가 1050℃ 이상, 시간은 0.1sec 이하, 승온속도는 150℃/sec 이상, 냉각온도속도는 70℃/sec 이상으로 한다.The spike rapid heat treatment may be performed at a temperature of 1050 ° C. or higher, a time of 0.1 sec or less, a temperature increase rate of 150 ° C./sec or more, and a cooling temperature rate of 70 ° C./sec or more.
도 3은 본 발명에 따른 반도체 소자의 제조 공정의 플로우차트이다.3 is a flowchart of a manufacturing process of a semiconductor device according to the present invention.
소정의 구조물이 형성된 기판에 이온주입 하는 제 1공정, 상기 기판에 압축응력이 걸린 질화물 또는 산화물을 증착시키는 제 2공정 및 상기 기판을 어닐링시키는 제 3공정으로 이루어져 있다.A first step of ion implantation into a substrate having a predetermined structure, a second step of depositing a nitride or oxide subjected to a compressive stress on the substrate and a third step of annealing the substrate.
상기 제 2공정에서 증착은 PE-CVD이고, 400~500℃의 온도범위내에서 증착 공정을 한다.In the second process, the deposition is PE-CVD, and the deposition process is performed within a temperature range of 400 to 500 ° C.
상기 어닐링은 스파이크 급속 열처리공정으로 한다.The annealing is a spike rapid heat treatment step.
상기와 같은 본 발명의 특징은 이온주입과 급속 열처리를 사용하여 도핑을 실시하는 모든 경우에 대하여 도핑 깊이를 감소시킬 수 있다는 점이다.As a feature of the present invention as described above, the doping depth can be reduced for all cases of doping using ion implantation and rapid heat treatment.
이는 65nm이하 기술에서 문제가 되고 있는 정션 형성 방법으로 사용할 수 있다.This can be used as a junction formation method that is a problem in the technology of 65nm or less.
더불어, 현재 R&D수준인 다른 도핑방법과 비교할 때 이미 양산공정에 적용되고 있는 기존 기술(이온주입, 급속 열처리)을 그대로 사용할 수 있다.In addition, compared to other doping methods at the current R & D level, existing technologies (ion implantation, rapid heat treatment) already applied to the mass production process can be used as they are.
상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.
따라서, 본 발명의 반도체 소자의 제조 방법은 압축응력이 걸린 옥사이드 필름을 플라스마 화학기상증착법으로 증착하여 어닐링 하여 TED의 근본 원인인 침입형 실리콘 원자의 확산 방향을 표면 방향으로 유도함으로써, 확산에 동반된 도펀트에 의한 도핑 깊이 증가를 근본적으로 제거하여 65nm이하 기술에서 문제가 되고 있는 정션 형성 방법에 사용할 수 있다.Therefore, in the method of manufacturing a semiconductor device of the present invention, an oxide film subjected to compressive stress is deposited and annealed by plasma chemical vapor deposition to induce the diffusion direction of an invasive silicon atom, which is the root cause of TED, to the surface direction, It can fundamentally eliminate the increase in doping depth caused by the dopant and can be used in the junction formation method which is a problem in the technology of 65 nm or less.
또한, 이미 양산공정에 적용되고 있는 기존 기술(이온주입, RTA)을 그대로 사용할 수 있다는 점에서 기술개발기간단축, 개발비용절감, 생산비용절감 등의 장점이 있다.In addition, the existing technology (ion implantation, RTA) that is already applied to the mass production process can be used as it is, there are advantages such as shortening the technology development period, development cost reduction, production cost reduction.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030027104A KR100604043B1 (en) | 2003-04-29 | 2003-04-29 | Semicondoctor device and its fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030027104A KR100604043B1 (en) | 2003-04-29 | 2003-04-29 | Semicondoctor device and its fabrication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040092789A KR20040092789A (en) | 2004-11-04 |
| KR100604043B1 true KR100604043B1 (en) | 2006-07-24 |
Family
ID=37373125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030027104A KR100604043B1 (en) | 2003-04-29 | 2003-04-29 | Semicondoctor device and its fabrication method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100604043B1 (en) |
-
2003
- 2003-04-29 KR KR1020030027104A patent/KR100604043B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040092789A (en) | 2004-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6358806B1 (en) | Silicon carbide CMOS channel | |
| US6930007B2 (en) | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance | |
| KR100305623B1 (en) | Fabrication method of semiconductor device using ion implantation | |
| CN100336186C (en) | Method for forming nickel silicide and semiconductor device | |
| US7511350B2 (en) | Nickel alloy silicide including indium and a method of manufacture therefor | |
| US5895955A (en) | MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch | |
| US8120120B2 (en) | Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility | |
| TW517312B (en) | Method for forming semiconductor device having epitaxial channel layer using laser treatment | |
| JPH10321840A (en) | Polysilicon gate electrode of mos element and its manufacture | |
| US6812073B2 (en) | Source drain and extension dopant concentration | |
| US20100270622A1 (en) | Semiconductor Device Having a Strain Inducing Sidewall Spacer and a Method of Manufacture Therefor | |
| US6294415B1 (en) | Method of fabricating a MOS transistor | |
| KR100624427B1 (en) | Fabrication method of poly crystalline Si and semiconductor device by the same | |
| US7494857B2 (en) | Advanced activation approach for MOS devices | |
| KR100604043B1 (en) | Semicondoctor device and its fabrication method | |
| WO2005096357A1 (en) | Method for manufacturing semiconductor device | |
| JP2000252366A (en) | Method for manufacturing dual gate structure of cmos device | |
| KR100806797B1 (en) | Manufacturing metfod of semiconductor device | |
| US20070048906A1 (en) | Method for fabricating semiconductor device | |
| JP3744895B2 (en) | Manufacturing method of CMOS semiconductor device | |
| KR20050118686A (en) | Improved gate electrode for semiconductor devices | |
| KR100396691B1 (en) | Method for forming salicide layer of semiconductor device | |
| JP4066022B2 (en) | Manufacturing method of semiconductor device | |
| KR100370156B1 (en) | method for manufacturing of semiconductor device | |
| KR100756766B1 (en) | Method for manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| N231 | Notification of change of applicant | ||
| E902 | Notification of reason for refusal | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110620 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |