KR100601914B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to the structure of a non-volatile static random access memory, and more particularly, to improve the vulnerability of the nvSRAM structure using the conventional SONOS device by using a non-volatile memory device in which the oxide film is laminated instead of the conventional SONOS device.

The object of the present invention is to provide two NMOS transistors and two PMOS transistors for forming an SRAM latch; Two NMOS pass gates for reading and writing "H" and "L" states formed in said SRAM latch; Two stacked oxide nonvolatile memory devices for storing respective " H " and " L " states stored in the SRAM latch when the power is turned off; And two NMOS pass gates and two NMOS recall gates as unit cells of nvSRAM as trigates for controlling read, write, and erase of the stacked oxide nonvolatile memory device.

Therefore, since the semiconductor device of the present invention proposes a new nvSRAM structure using a laminated oxide nonvolatile device, the program speed is very fast, and thus the capacitor capacity for maintaining the system constant voltage for a predetermined time is reduced to 1/100 or less. have.

nvSRAM, Oxide Stack NVM Device, Hot Electron Injection, Trigate

Description

Semiconductor device             

1 is a cross-sectional view of an nvSRAM structure using a conventional SONOS device.

2 is a cross-sectional view of a laminated oxide flash memory device of the present invention.

Fig. 3 is a circuit diagram showing an nvSRAM structure using the laminated oxide flash memory device of the present invention.

4 is a circuit diagram illustrating a static current path occurring in a program mode.

Fig. 5 is a sectional view of a laminated oxide flash memory device in the present invention.

The present invention relates to the structure of Non-Volatile Static Random Access Memory (nvSRAM), and more particularly, to improve the vulnerability of the nvSRAM structure using an existing SONOS device by using a non-volatile memory device having an oxide layer instead of the conventional SONOS device. It is about.

1 is a diagram illustrating a nvSRAM unit cell structure using a conventional SONOS device.

Conventional nvSRAM unit cells have two NMOS transistors and two PMOS transistors to form an SRAM latch, "H" formed on the SRAM latch, two NMOS pass gates to read and write the "L" state, and power off. Two SONOS transistors to store each of the "H" and "L" states stored in the SRAM latch, and finally a trigate to control the read, write, and erase of the SONOS transistors. Two NMOS recall gates comprise a total of eight NMOS transistors, two PMOS transistors, and two SONOS transistors.

The operation of nvSRAM using a conventional SONOS device is described below. First, when the system is operating, all Vrcl, Vpas, and Vse are all 0 [V] to turn off all of the trigates to isolate the SONOS transistors from the SRAM latches. When the system is powered off without being affected by the change, the SRAM latch state is stored in each SONOS transistor through the erase mode and the program mode.

First, in the erase mode, the negative SON voltage applied to the SONOS gate can vary depending on various factors such as erase speed, erase time, and ONO stack structure. Apply 0 [V] to Vrcl and 0 [V] to Vpas for a certain time. In most cases, the biasing time in erase mode is often less than 10 [msec].

Under this erase mode bias condition, both the recall gate and the pass gate are off, the SONOS transistor enters the storage mode, and most of the electric field due to the voltage applied to the SONOS gate is concentrated in the ONO layer. As a result of the strong electric field applied to the ONO layer, holes stored in the surface of the silicon substrate where the SONOS gate is located tunnel through the tunnel oxide layer of the SONOS gate and trapped in a trap existing in the nitride layer, or electrons trapped in the nitride layer tunnel the tunnel oxide layer. It exits to the silicon substrate and becomes an erased state where the threshold voltage of the SONOS transistor is lowered.

The program mode is +10 to +15 [V] on the SONOS gate. (The positive voltage applied to the SONOS gate can be changed by various factors such as program speed, program time, ONO stack structure, and dynamic write inhibition (DWI) characteristics.) ) And apply 0 [V] to Vrcl and “H” (VOLs to indicate High status, which is the voltage recognized by Logic as High, usually 2.5 [V]) to Vpas for a certain period of time. . In most cases, the bias time in program mode is often less than 10 [msec].

In this program mode bias condition, the recall gate is turned off so that the Vcc voltage is not affected. The pass gate is affected by the ON states according to the respective "H" and "L" states stored in the SRAM latch. As shown in FIG. 1, when "H" is stored on the left side and "L" on the right side of the SRAM latch, the gate and source voltage difference of the pass gate connected to the left side "H" is almost 0 [V]. The silicon substrate under the SONOS gate enters a deep depletion state due to the positive voltage applied to the SONOS gate. In this deep depletion state, the electric field due to the positive voltage applied to the SONOS gate is mostly caught in the deep depletion region, so that almost no electric field is applied to the ONO layer. Therefore, a program operation in which electrons tunnel through the tunnel oxide film and traps the trap of the nitride film Does not occur. This phenomenon is called DWI, and since such deep depletion occurs in an unbalanced state, as it returns to equilibrium with time, the deep depletion phenomenon disappears and no more DWI occurs. In other words, the program is not performed by the DWI at the beginning of the program, but after a certain time, the DWI phenomenon disappears and the program is performed. Depending on the device structure, the DWI characteristics appear differently. In most cases, the DWI lasts for 1 to 100 [msec] time.

On the contrary, the gate of the pass gate connected to the right side "L" and the source voltage difference are almost "H" [V] and are turned on so that the silicon substrate under the SONOS gate is almost "L" [V] (mostly 0 [V]). And the majority of the program voltage applied to the SONOS gate is caught by the ONO layer, so that electrons gathered on the surface of the silicon substrate tunnel through the tunnel oxide film and trapped in the trap of the nitride film. The threshold voltage of the transistor is increased.

Therefore, in the program mode, the SONOS transistor connected to "H" is suppressed by DWI to maintain the initial erased state, and has a low threshold voltage. The SONOS transistor connected to "L" performs a program operation. It has a high threshold voltage.

Next, when the system is powered on, a recall operation is performed to load the data stored in the SONOS device into the SRAM latch. This recall operation is applied with 0 [V] for Vse, "H" for Vrcl, and "H" for Vpas. .

In the recall operation bias condition, both the recall gate and the pass gate are turned on and the erased left SONOS device is turned on, so that the current flows through the left side of the SRAM latch to the "H" state, and the programmed right SONOS device is turned on. Is off and no current flows, so the right side of the SRAM latch is in the "L" state.

Therefore, the data of the SRAM can be safely stored even if the system is turned off through the erase mode, program mode, and recall mode operations.

In the case of nvSRAM using the conventional SONOS device, it is important to improve the DWI characteristics as well as the program speed because one program is selectively programmed by one side of the program according to the state of the SRAM latch when the data is stored. It is very difficult to improve this important factor, the DWI characteristic, and the threshold voltage window (the difference between the threshold voltage of the programmed SONOS transistor and the threshold voltage of the SONOS transistor where the DWI occurs) is constant even if the program time is increased during selective programming by the DWI mechanism. Can not increase above voltage.

In addition, the thickness of the tunnel oxide of the SONOS transistor is very small (usually around 20Å) and the retention characteristics are very poor, and the constant voltage required for data storage of the SRAM latch when the system goes off due to the relatively slow programming speed of the SONOS device. There is a problem in that a capacitor of a considerably large value is required to maintain a predetermined time.

Accordingly, an object of the present invention is to provide a semiconductor device having a new nvSRAM structure using a nonvolatile device in which oxide films are stacked.

The object of the present invention is to provide two NMOS transistors and two PMOS transistors for forming an SRAM latch; Two NMOS pass gates for reading and writing "H" and "L" states formed in said SRAM latch; Two stacked oxide nonvolatile memory devices for storing respective " H " and " L " states stored in the SRAM latch when the power is turned off; And two NMOS pass gates and two NMOS recall gates as unit cells of nvSRAM as trigates for controlling read, write, and erase of the stacked oxide nonvolatile memory device.

The above object of the present invention is to provide a semiconductor device comprising: a semiconductor substrate of a first conductive type; A second conductivity type MOS transistor including a first well of a second conductivity type formed in one region of the substrate, a gate formed above the well of the second conductivity type, and a first conductivity type impurity region formed below both sides of the gate; A first well of a first conductivity type formed with a first well of the second conductivity type and an isolation layer in a region of the substrate, a gate formed on the first well of the first conductivity type, and both sides of the gate A first conductivity type MOS transistor including a second conductivity type impurity region formed below; A second well of a first conductivity type formed in one region of the substrate with the first well of the first conductivity type interposed between the device isolation layer; A second well of a second conductivity type formed under the second well of the first conductivity type; A pass gate and a source / drain region of a second conductivity type formed in the second well of the first conductivity type; A stacked oxide structure gate and a source / drain region of a second conductivity type formed in the second well of the first conductivity type spaced apart from the pass gate; A recall gate and a source / drain region of a second conductivity type formed in the second well of the first conductivity type spaced apart from the multilayer oxide structure gate; And an impurity region of a first conductivity type formed in the second well of the first conductivity type.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

2 illustrates a structure of a nonvolatile memory device according to the present invention. The stacked oxide film 104 and the polysilicon gate 105 are sequentially deposited on the P-type silicon substrate 101, and the source 103 and the drain 102 are formed on both sides of the gate. The laminated oxide film 104 is composed of a tunnel oxide film 106, a storage oxide film 107, and a block oxide film 108. The tunnel oxide film 106 is a single layer or a multilayer of the first tunnel oxide film 106-1 and the second tunnel oxide film 106-2. The block oxide film 108 is also a single layer or a multilayer of the first block oxide film 108-1 and the second block oxide film 108-2.

When the tunnel oxide film is used as a single layer, it is preferable that the tunnel oxide film is formed of any one of SiO ₂ , Al ₂ O ₃ , and Y ₂ O _{3. When the} tunnel oxide film is used as a multilayer, the first tunnel oxide film is Al ₂ O ₃ , Y ₂ O. ₃ , HfO ₂ , ZrO ₂ , BaZrO ₂ , BaTiO ₃ , Ta ₂ O ₅ , CaO, SrO, BaO, La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , In Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ or Lu ₂ O ₃ In any case, the second tunnel oxide film is preferably made of any one of SiO ₂ , Al ₂ O _3, or Y ₂ O ₃ .

The storage oxide film is HfO ₂ , ZrO ₂ , BaZrO ₂ , BaTiO ₃ , Ta ₂ O ₅ , CaO, SrO, BaO, La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ or Lu ₂ O It is preferable to consist of any one of _three .

When the block oxide film is used as a single layer, it is preferable that the block oxide film is formed of any one of SiO ₂ , Al ₂ O ₃ , and Y ₂ O _{3. When the} block oxide film is used as a multilayer, the first block oxide film is SiO ₂ , Al ₂ O _3, or It is preferably made of any one of Y ₂ O ₃ , the second block oxide film is Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , ZrO ₂ , BaZrO ₂ , BaTiO ₃ , Ta ₂ O ₅ , CaO, SrO, BaO, La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , _{Ho 2 O 3, Er 2 O} 3, Tm 2 O 3, is preferably formed by any of the Yb ₂ O ₃ or Lu ₂ O _3.

In the program of the device, the thermal electrons are injected into the potential well formed in the storage oxide film by jumping over the energy barrier of the tunnel oxide film, thereby increasing the threshold voltage. In this case, the threshold voltage is lowered by tunneling out electrons stored in the potential well of the storage oxide film by the F / N tunneling method to the silicon substrate. In the case of a read, a current flowing by applying a voltage between the threshold voltage of the program state and the threshold voltage of the erase state is applied to the gate to detect whether the program is in the program state or the erase state.

3 is a view illustrating an nvSRAM unit cell structure using a stacked oxide film according to the present invention. The nvSRAM cell of the present invention is almost the same as a conventional nvSRAM cell, and has a structure in which a stacked oxide flash memory element is replaced instead of only a SONOS transistor.

Therefore, the nvSRAM unit cell of the present invention has two NMOS transistors and two PMOS transistors for forming an SRAM latch, "H" formed in the SRAM latch, two NMOS pass gates for reading and writing the "L" state, and a power supply off. Two stacked oxide flash memory devices to store each of the "H" and "L" states stored in the SRAM latch, and finally a trigate to control the read, write, and erase of the stacked oxide flash memory device. Two low NMOS pass gates and two NMOS recall gates consist of eight NMOS transistors, two PMOS transistors, and two stacked oxide flash memory devices.

Unlike the conventional nvSRAM structure, a bias is separately applied to a P well in which a pass gate, a recall gate, and a stacked oxide flash memory device, which are used as trigates, are located. Therefore, unlike the prior art, it should be isolated from the P well in which the SRAM latch is located. (A separate bias is applied to the P well in which the stacked oxide flash memory device and the trigate are located. Make and separate P wells)

Referring to FIG. 3, the operation of the nvSRAM using the stacked oxide flash memory device according to the present invention will be described. When the system is turned on, data stored in the stacked oxide flash memory device is loaded into the SRAM latch while going through a recall mode and an erase mode. At the same time, all data stored in the stacked oxide flash memory device is erased.

First of all, recall mode is applied to Vse, Vref [V], Vb 0 [V], Vrcl H, Vpas H, Vcc + Vcc_rcl, and both Pass Gate and Recall Gate are On. If the stacked oxide flash memory device on the left is erased and the stacked oxide flash memory device on the right is programmed, the left stacked oxide flash memory is on. Since the stacked oxide flash memory device on the right side is in the off state, no current flows, and the right side of the SRAM latch is in the "L" state. When the system is turned on, data stored in the stacked oxide flash memory device is loaded into the SRAM latch through the recall mode. Here, the Vse voltage applied in the recall mode is set to Vref, which is usually set to a middle value between the threshold voltage of the programmed cell and the threshold voltage of the erased cell. In case of + Vcc_rcl applied to Vcc, if too high voltage is used, program operation may occur during recall, so it should be set to the voltage that program operation does not occur in recall mode.

After the recall mode operation is completed, the erase mode is immediately performed. The erase mode is described as Vse = -Vers [V], Vb = + Vbers / 0 [V], Vrcl = 0 [V], Vpas = 0 [V], When the bias of Vcc = 0 [V] is applied for a predetermined time, both the pass gate and the recall gate are in the off state, so that the stacked oxide flash memory device is in a storage state, and most of the voltages applied to Vse and Vb are applied to the stacked oxide flash memory device. The stacked oxide film is interposed between the gate and the silicon substrate. As a result of the strong electric field applied to the stacked oxide film, electrons trapped in the potential well of the stacked oxide film are tunneled out to the silicon substrate, thereby reducing the threshold voltage of the stacked oxide flash memory device. In the case of most stacked oxide flash memory devices, the thickness of the tunneling oxide film is about 100 μs for good retention characteristics, so the erasing by electron tunneling is very slow, such as 100 [msec]. Cannot be erased at this point. Therefore, in the case of the nvSRAM using the multilayer oxide flash memory device as in the present invention, after the recall mode operation is completed when the system is turned on, both of the multilayer oxide flash memory devices connected to the SRAM latch must be erased through the erase mode operation. .

Next, when the system is off, it goes through a program mode that stores the “H” and “L” states of the SRAM latch in a stacked oxide flash memory device. In the case of the program mode bias, + Vpgm [V] for Vse and 0 [V for Vb. ], H to Vrcl, H to Vpas, and + Vcc_pgm [V] to Vcc. Under these bias conditions, both stacked oxide flash memory devices are turned on because they are all erased and the left side of the SRAM latch is “H”, so the Vgs of the left pass gate becomes 0 [V] and is off. As the current does not flow, the left stacked oxide flash memory device remains erased. Since the right side of the SRAM latch is in the “L” state, the Vgs of the right pass gate becomes “H” and is in the on state. Since it is also On, current flows. Therefore, electrons forming the channel of the stacked oxide film NVM are accelerated by the Vcc drain voltage and injected into the stacked oxide flash memory device (thermal electron injection) to increase the threshold voltage of the right stacked oxide flash memory device. In the case of programming a stacked oxide flash memory device, the program speed is very fast, within 100 [usec], because a hot electron injection method is used. In program mode, you can apply + Vpgm [V] to Vse for a certain time (constant voltage program) or program it (step voltage program) while increasing the voltage at a constant speed.

4 illustrates a static current path occurring in the program mode. When the right side of the SRAM latch is in the "L" state, a static current path such as 401 is generated. Therefore, the potential of 402 is changed by this static current path. If the potential of 402 becomes high enough to turn on the opposite NMOS of the SRAM latch, an error may occur that the potential on the right side suddenly changes from the “L” state to the “H” state. . Therefore, in the program mode, the potential change due to the static current should be suppressed as much as possible. In the program mode, the potential of 402 cannot rise above the value of Vcc minus the trigate threshold voltage, ie, Vcc-Vt_tirgate. This problem can be solved by increasing the 402 to suppress the potential of the 402 from rising above a certain value.

5 is a cross-sectional view of an nvSRAM using the stacked oxide flash memory device of the present invention. PMOS and NMOS for SRAM are formed in N well and P well, and tri-layer stacked oxide flash memory device is formed in P well 2, and P well 2 is formed by P well 1 and S for deep S well formation. Are separated. Vpas, Vrcl, and Vse are applied to the respective pass gates, recall gates, and stacked oxide flash memory device gates constituting the trigate, Vcc is applied to the right drain of the recall gate, and Vb is applied to P well 2.

As in the present invention, the nvSRAM structure using the stacked oxide flash memory device has a very fast program speed, so that when the system is turned off, the capacitance capacity for maintaining a constant voltage for a predetermined time can be reduced to 1/100 or less and erased. A threshold voltage difference between the stacked oxide flash memory device and the programmed stacked oxide flash memory device may be greatly increased to 5 [V] or more. In addition, the thickness of the tunnel oxide is much higher than that of the nvSRAM using the SONOS device, and the retention characteristics are much higher. First of all, the program characteristics are not affected by the DWI characteristics, so the program characteristics are not affected by the DWI. Also, in the program mode, the SRAM latch-connected stacked oxide flash memory device in the “H” state is completely blocked by the pass gate, so the threshold of the stacked oxide flash memory device connected to the SRAM “H” node is increased even though the program time is increased. The voltage does not increase.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the semiconductor device of the present invention has the following effects by proposing a new nvSRAM structure using a laminated oxide nonvolatile device.

First, since the program speed is very fast, the capacitor capacity for maintaining the system constant voltage for a certain time can be reduced to less than 1/100.

Second, since the thermal electron injection is programmed, the thermal electron efficiency and the injected electrons are very likely to be trapped in the potential well of the stacked oxide nonvolatile device, and thus the erased stacked oxide nonvolatile memory device and the programmed stacked oxide nonvolatile memory The threshold voltage difference of the device can be greatly increased to 5 [V] or more.

Third, the thickness of the tunnel oxide film is so great that the retention characteristics are superior to that of the nvSRAM using the SONOS device.

Fourth, in the case of nvSRAM using a SONOS device, a SONOS device that should not be programmed also has a problem that a threshold voltage increases due to a long program time, whereas a nvSRAM using a laminated oxide flash memory device as in the present invention. Since the current is completely blocked by the pass gate, even if the program time is increased, the threshold voltage of the stacked oxide flash memory device connected to the SRAM “H” node does not increase.

Fifth, in the case of nvSRAM using the SONOS device, the program characteristic is affected by the DWI characteristic, but in the case of the stacked oxide layer, the program characteristic is not affected by the DWI.

Claims (14)

In a semiconductor device, Two NMOS transistors and two PMOS transistors to form an SRAM latch; Two NMOS pass gates for reading and writing "H" and "L" states formed in said SRAM latch; Two stacked oxide nonvolatile memory devices for storing respective " H " and " L " states stored in the SRAM latch when the power is turned off; And Two NMOS pass gates and two NMOS recall gates as trigates for controlling read, write, and erase of the stacked oxide nonvolatile memory device. The semiconductor device comprising a unit cell of nvSRAM. The method of claim 1, And biasing the wells in which the pass gate, the recall gate, and the stacked oxide nonvolatile memory device are located. The method of claim 1, And the well in which the SRAM latch is formed and the well in which the pass gate and the stacked oxide nonvolatile memory device are located are separated by deep wells of different conductivity types. The method of claim 1, And the stacked oxide nonvolatile memory device comprises a stacked oxide film and a polysilicon gate. The method of claim 4, wherein And said laminated oxide film is comprised of a tunnel oxide film, a storage oxide film and a block oxide film. The method of claim 5, The tunnel oxide film is a semiconductor device, characterized in that a single layer or a multilayer of the first tunnel oxide film and the second tunnel oxide film. The method of claim 6, The single layer tunnel oxide film is a semiconductor device, characterized in that any one of SiO ₂ , Al ₂ O ₃ and Y ₂ O ₃ . The method of claim 6, The first tunnel oxide layer of the multilayer tunnel oxide layer is Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , ZrO ₂ , BaZrO ₂ , BaTiO ₃ , Ta ₂ O ₅ , CaO, SrO, BaO, La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ A semiconductor device according to any one of O ₃ , Tm ₂ O ₃ , Yb ₂ O _3, and Lu ₂ O ₃ , wherein the second tunnel oxide layer is any one of SiO ₂ , Al ₂ O _3, and Y ₂ O ₃ . The method of claim 4, wherein And the block oxide film is a single layer or a multilayer of a first block oxide film and a second block oxide film. The method of claim 9, A semiconductor device, characterized in that any one of SiO ₂ , Al ₂ O ₃ and Y ₂ O ₃ of the single layer block oxide film. The method of claim 9, The first block oxide film of the multilayer block oxide film is any one of SiO ₂ , Al ₂ O ₃ and Y ₂ O ₃ , and the second block oxide film is Al ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , ZrO ₂ , BaZrO ₂ , BaTiO ₃ , Ta ₂ O ₅ , CaO, SrO, BaO, La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd A semiconductor device comprising any one of ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O _3, and Lu ₂ O ₃ . In a semiconductor device, A first conductive semiconductor substrate; A second conductivity type MOS transistor including a first well of a second conductivity type formed in one region of the substrate, a gate formed above the well of the second conductivity type, and a first conductivity type impurity region formed below both sides of the gate; A first well of a first conductivity type formed with a first well of the second conductivity type and an isolation layer in a region of the substrate, a gate formed on the first well of the first conductivity type, and both sides of the gate A first conductivity type MOS transistor including a second conductivity type impurity region formed below; A second well of a first conductivity type formed in one region of the substrate with the first well of the first conductivity type interposed between the device isolation layer; A second well of a second conductivity type formed under the second well of the first conductivity type; A pass gate and a source / drain region of a second conductivity type formed in the second well of the first conductivity type; A stacked oxide structure gate and a source / drain region of a second conductivity type formed in the second well of the first conductivity type spaced apart from the pass gate; A recall gate and a source / drain region of a second conductivity type formed in the second well of the first conductivity type spaced apart from the multilayer oxide structure gate; And An impurity region of a first conductivity type formed in the second well of the first conductivity type A semiconductor device comprising a. The method of claim 12, And the impurity region of the first conductivity type is separated by a drain region of the recall gate and an isolation layer. The method of claim 12, And the second well of the second conductivity type separates the first well of the first conductivity type and the second well of the first conductivity type.

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