KR100599779B1 - Plasma display panel - Google Patents

Abstract

The plasma display panel of the present invention enables stable driving by preventing unnecessary discharge in the gap portion of the address electrode for dual scan driving.

A plasma display panel according to the present invention comprises: a first substrate and a second substrate facing each other while maintaining a gap; Barrier ribs disposed in a space between the first substrate and the second substrate to form discharge cells; Phosphor layers formed in the discharge cells; Discharge sustain electrodes formed on a first substrate corresponding to each of the discharge cells; And address electrodes formed on the second substrate to cross the discharge sustain electrodes, wherein the address electrodes extend along one side of the second substrate, and the same surface of the second substrate. The second address electrodes are formed to extend to the other side of the second substrate while maintaining a gap corresponding to the first address electrodes, wherein the front ends of the first address electrodes and the second address electrodes positioned in the gap Become ground.

Plasma Display, Gap, Ground, Dual Scan

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

1 is an exploded perspective view schematically showing a plasma display panel according to the present invention.

2 is a cross-sectional view taken along the line A-A of FIG.

3 is a partial plan view of FIG. 1.

4 is a circuit diagram formed by a first address electrode and a second address electrode.

5 is a ground state circuit diagram of the first address electrode.

6 is a ground state circuit diagram of a second address electrode.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP, hereinafter referred to as PDP) for displaying an image by dual driving.

In general, PDP uses red (R), green (G), and blue (B) visible light generated by exciting a phosphor with vacuum ultra-violet (VUV) emitted from plasma obtained through gas discharge. A display device for implementing an image. This PDP can realize a 60-inch or larger screen with a thickness of only 10 cm or less, and is a self-luminous display device such as a cathode ray tube, so that there is no distortion caused by color reproduction and viewing angle, and the manufacturing method is simpler than LCD. It also has strengths in terms of productivity and cost.

A typical AC PDP forms address electrodes in one direction on a rear substrate, covers the address electrodes with a dielectric layer, and has stripe-shaped partition walls between each address electrode on the dielectric layer, and between the partition walls. And red (R), green (G), and blue (B) phosphor layers, and discharge sustain electrodes on the front substrate facing the rear substrate along the direction crossing the address electrodes. It is formed by covering with a dielectric layer and an MgO protective film. Of course, the discharge sustaining electrode is composed of a pair of X and Y electrodes which cause surface discharge, and these X and Y electrodes are usually composed of a transparent electrode which causes surface discharge and a bus electrode which applies a discharge voltage thereto. A discharge cell is formed at the point where the address electrodes on the rear substrate and the pair of X and Y electrodes on the front substrate cross each other.

Thus, millions of unit discharge cells are arranged in a matrix form in the PDP, and the discharge cells arranged in the matrix form are simultaneously driven by a driving method using a memory characteristic.

In more detail, in order to generate a discharge between the X electrode and the Y electrode constituting the pair of discharge sustaining electrodes, a potential difference of more than a specific voltage is required, and the voltage at this boundary is called a firing voltage (Vf: Firing Voltage). do. At this time, when an address voltage is applied between the Y electrode and the address electrode, the discharge is initiated to form a plasma in the discharge cell, and the electrons and ions in the plasma move toward the electrode having the opposite polarity, so that a current flows.

On the other hand, a dielectric layer is applied to each electrode of the AC PDP so that most of the transferred space charges are stacked on the dielectric layer having the opposite polarity, so that the net space potential between the Y electrode and the address electrode is originally applied to the address voltage. It becomes smaller than Va, the discharge is weakened, and the address discharge is extinguished. At this time, a relatively small amount of electrons are accumulated on the X electrode side, and a relatively large amount of ions are accumulated on the Y electrode side. The charges accumulated on the dielectric layers covering the X electrode and the Y electrode are accumulated as wall charges (Qw). The space voltage formed between the X and Y electrodes by these wall charges is referred to as wall voltage (Vw).

Subsequently, when a constant voltage (Vs: discharge holding voltage) is applied between the X electrode and the Y electrode, the sum of the magnitudes of the discharge holding voltage Vs and the wall voltage Vw (Vs + Vw) is the discharge starting voltage. If it is higher than (Vf), the discharge occurs in the discharge cell, and the vacuum ultraviolet light (VUV) generated at this time excites the phosphor layer and emits visible light through the transparent front substrate so that the PDP realizes an image.

As the PDP becomes larger in size, a scan period in which the discharge cells are addressed by applying a scan pulse to the Y electrode and an address voltage to the address electrode becomes longer, so that the sustain period during which the sustain discharge occurs is shortened. It becomes difficult to implement an image effectively.

Therefore, the dual scan drive method is adopted. This driving method separates the address electrode into a portion provided on the upper side and a portion provided on the lower side of the PDP, and simultaneously scans the address period by applying the address voltage on both sides.

However, for this dual scan driving method, the address electrodes are formed into upper and lower address electrodes that maintain a gap using a screen mask. Therefore, when the address voltage is applied to the upper and lower address electrodes, stable driving of the PDP is hindered, such as unnecessary discharge caused by electrons accumulated at the tip of the upper and lower address electrodes positioned in the gap.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a plasma display panel which can prevent unnecessary discharge in the gap portion of the address electrode for dual scan driving and thereby can be stably driven.

Plasma display panel according to the present invention,

A first substrate and a second substrate facing each other while maintaining a spacing;

Barrier ribs disposed in a space between the first substrate and the second substrate to form discharge cells;

Phosphor layers formed in the discharge cells;

Discharge sustain electrodes formed on a first substrate corresponding to each of the discharge cells; And

Address electrodes formed on the second substrate to cross the discharge sustain electrodes;

The address electrodes extend to the other side of the second substrate while maintaining a gap corresponding to the first address electrodes on the first side of the second substrate and the first surface of the second substrate. A second address electrode formed;

The leading ends of the first address electrodes and the second address electrodes positioned in the gap are grounded.

The first address electrode is grounded through the second address electrode. The second address electrode is grounded through the first address electrode.

The gap is provided with a resistor to interconnect corresponding ends of the first address electrode and the second address electrode.

For this reason, the first address electrode is grounded through the resistor and the second address electrode provided in the gap. The second address electrode is grounded through the resistor provided in the gap and the first address electrode.

The resistor has an electrical resistance higher than that of the address electrode.

The resistor is preferably formed at a position corresponding to the non-discharge region formed between the discharge cells.

The resistor is formed independently of each address electrode.

The first address electrode and the second address electrode have a stripe shape.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view schematically showing a plasma display panel according to the present invention.

Referring to this figure, the PDP is schematically described. The PDP seals the first substrate (1, hereinafter referred to as front substrate) and the second substrate (3, hereinafter referred to as back substrate) to face each other. It is formed by filling an inert gas between the front substrate 1 and the back substrate 3. In the space formed between the front substrate 1 and the back substrate 3, a plurality of partition walls 5 are arranged to form a plurality of discharge cells 7R, 7G, 7B. In the discharge cells 7R, 7G, and 7B, fluorescent layers 8R, 8G, and 8B are formed of phosphors of red (R), green (G), and blue (B) colors.

On the front substrate 1, X and Y electrodes 9 and 11 are formed to extend along one direction (x axis direction in the drawing), and the X and Y electrodes 9 and 11 are formed on the y axis. In the direction corresponding to each discharge cell 7R, 7G, 7B. On the back substrate 3, the address electrodes 13 are formed along the direction crossing the X and Y electrodes 9 and 11 (y-axis direction in the drawing), and the address electrodes 13 are formed. They are arranged at intervals corresponding to each discharge cell 7R, 7G, 7B in the x axis direction. That is, the X and Y electrodes 9 and 11 and the address electrodes 13 are arranged in a corresponding structure while crossing the respective discharge cells 7R, 7G and 7B. Discharge cells 7R, 7G, and 7B are formed at portions where the discharge sustaining electrodes 9, 11 and the address electrodes 13 intersect.

The partition walls 5 provided between the front substrate 1 and the rear substrate 3 are parallel to each other while maintaining a distance corresponding to the other partition walls 5 and the discharge cells 7R, 7G, and 7B that are adjacent to each other. Disposed, the discharge cells 7R, 7G, and 7B necessary for plasma discharge are partitioned in the space between the front substrate 1 and the back substrate 3. This embodiment illustrates a stripe-type barrier rib structure formed only of barrier ribs 5 arranged in parallel with the address electrodes 13 (y axis direction).

In addition, the barrier rib structure of the present invention is not limited to the above-described stripe barrier rib structure, and the barrier ribs 5 formed in the direction parallel to the address electrodes 13 (y-axis direction) and the barrier ribs 5 intersect with the barrier ribs 5. It includes a closed partition structure for partitioning the discharge cells (7R, 7G, 7B) independently by partitions (not shown) formed in the direction (x axis direction). In addition, the barrier rib structure of the present invention includes a closed barrier rib structure for forming the discharge cells 7R, 7G, and 7B in a quadrangular shape, and a closed barrier rib structure for forming hexagonal and octagonal shapes.

The X and Y electrodes 9 and 11 forming the discharge sustaining electrodes correspond to both sides of one discharge cell 7R, 7G and 7B, and are formed on the front substrate 1. The X and Y electrodes 9 and 11 may be formed of the transparent electrodes 9a and 11a and the bus electrodes 9b and 11b, respectively, as shown in the present embodiment, and the transparent electrodes 9a and 11a or the buses may be formed. It may be formed only by the electrodes 9b and 11b, respectively.

The transparent electrodes 9a and 11a are formed in a stripe type extending in the direction crossing the address electrode 13 (x-axis direction), and partially protrude toward the center of the discharge cells 7R, 7G, and 7B. It may be formed in a protrusion (not shown). In addition, since the transparent electrodes 9a and 11a block surface areas of the discharge cells 7R, 7G and 7B as part of causing surface discharge inside the discharge cells 7R, 7G and 7B, the blocking of visible light is minimized. It is preferable to be formed of a transparent material so as to ensure the light emission luminance, it may be formed of an indium tin oxide (ITO) electrode.

In addition, the bus electrodes 9b and 11b are designed to compensate for the high electrical resistance of the transparent electrodes 9a and 11a to ensure the electrical conductivity of the transparent electrodes 9a and 11a. Preferably, it may be formed of an aluminum (Al) electrode. The bus electrodes 9a and 11a are formed in a stacked structure on the transparent electrodes 9a and 11a formed on the front substrate 1 and extend in a direction (x-axis direction) that intersects the address electrode 13. Since the bus electrodes 9b and 11b are made of an opaque material, the bus electrodes 9b and 11b are disposed to correspond to the partition wall 5, and are formed to have a width smaller than that of the partition wall 5 to emit visible light from the discharge cells 7R, 7G, and 7B. It is desirable to minimize blocking.

The X and Y electrodes 9 and 11 formed as described above are covered with a stacked structure of the dielectric layer 15 and the MgO passivation layer 17 to accumulate wall charges during PDP driving. The dielectric layer 15 is preferably formed of a transparent dielectric so as to improve the transmittance of visible light. The MgO protective film 17 prevents ions of the ionized atoms from colliding with the dielectric layer 15 and damaging the dielectric layer 15, and improves the emission of secondary electrons when the ions collide.

The address electrodes 13 scan-driven in interaction with the Y electrode 11 are covered with the dielectric layer 19 to form wall charges in the discharge cells 7R, 7G, and 7B to cause address discharge. The partitions 5 described above are formed on the dielectric layer 19.

FIG. 2 is a cross-sectional view taken along the line A-A of FIG. 1, and FIG. 3 is a partial plan view of FIG. 1.

Referring to the drawings, the address electrode 13 will be described further. For the dual scan driving, the address electrodes 13 maintain the gaps g in the center of the second substrate 3 while maintaining the gaps g. And the second address electrode 13b. That is, the first address electrodes 13a are extended to one side (corresponding to the right side of FIG. 2 and the upper side of FIG. 3) of the second substrate 3, and the second address electrodes 13b are formed on the second substrate 3. It extends to the other side of (corresponding to the left side of FIG. 2 and the lower side of FIG. 3). Of course, the first and second address electrodes 13a and 13b are provided on the same surface of the second substrate 3 and have a stripe-like structure corresponding to each other.

In driving the PDP configured as described above, one frame is composed of a plurality of subfields, and each subfield is applied to the X, Y electrodes 9 and 11 and the address electrode 13. According to the driving waveform, a reset period, a scan period, and a sustain period are provided.

First, in the reset period, wall charges are formed at appropriate polarities and amounts in each of the address electrode 13, the Y electrode 11, and the X electrode 9, so that the wall charge can be smoothly performed in the scan period. It is a section to adjust the distribution of.

The scan period proceeds following this reset period. In this scan period, an address voltage Va is applied to the first address electrode 13a and a scan pulse is applied to the Y electrode 11 intersecting the first address electrode 13a so as to discharge the corresponding discharge cells 7R, 7G, and 7B. ) And at the same time an address voltage Va is applied to the second address electrode 13b and a scan pulse is applied to the Y electrode 11 intersecting the second address electrode 13b so that the corresponding discharge cell 7R is applied. , 7G, 7B).

That is, when the scan pulse applied to the Y electrode 11 is omitted and described, the address voltage Va is applied to the second address electrode 13b separately from the application of the address voltage Va to the first address electrode 13a. The scan drive is applied to address the discharge cells 7R, 7G, and 7B corresponding to each other. This makes it possible to shorten the scan period in one subfield and to increase the sustain period for actually displaying an image.

The front ends of the first address electrodes 13a and the second address electrodes 13b positioned in the gap g are grounded to stabilize the driving of the PDP. As a result, during scan driving due to the application of the address voltage Va, electrons are not collected at the front ends of the two electrodes 13a and 13b, and unnecessary discharge is not generated.

4 is a circuit diagram formed by a first address electrode and a second address electrode.

Referring to the circuit diagram with reference to the drawings, the front ends of the first and second address electrodes 13a and 13b shown in this embodiment are provided in a straight line with each other, so that the second and first address electrodes 13b corresponding to each other. And ground through 13a).

To this end, the resistor 21 is provided in the gap g. The resistor 21 is electrically connected to the corresponding ends of the first address electrode 13a and the second address electrode 13b on the second substrate 3 while being opposite to each other, that is, the second and first address electrodes ( 13b, 13a) to ground.

Accordingly, the first and second address electrodes 13a and 13b are connected to each other by the resistor 21 provided in the gap g and the resistors 21 interposed therebetween. Ground through 13b and 13a, respectively.

The resistor 21 is formed of a material having an electrical resistance higher than that of the first and second address electrodes 13a and 13b. The resistor 21 may be formed of various materials, and detailed arrangement thereof will be omitted. As described above, the resistor 21 having a high resistance can ground the electrodes 13a and 13b so that the first and second address electrodes 13a and 13b smoothly drive the scan with the Y electrode 11. The two electrodes 13a and 13b are electrically connected to prevent unnecessary discharge from occurring between the terminals. When the resistor 21 is assumed to have a constant address voltage Va, power consumption decreases as the electrical resistance increases to the previous limit.

In addition, the resistor 21 is formed on the second substrate 3 at a position corresponding to the non-discharge region between the discharge cells 7R, 7G, and 7B, as shown in FIG. It is preferable not to disturb the scan drive between the Y electrodes 11.

The resistor 21 is preferably formed independently of each address electrode 13 to form a ground circuit as shown in FIG. 4 for each address electrode 13.

5 is a ground state circuit diagram of the first address electrode.

Referring to the drawing, the first address electrode 13a is driven to scan. Referring to FIG. 1, an address voltage Va is applied to the first address electrode 13a, and a Y electrode (intersecting the first address electrode 13a) is applied. When a scan pulse is applied to 11, the first address electrode 13a and the Y electrode 11 scan drive to address the corresponding discharge cells 7R, 7G, and 7B. At this time, the address voltage Va applied to the first address electrode 13a is grounded through the resistor 21 and the second address electrode 13b connected thereto after the scan driving (path a).

6 is a ground state circuit diagram of a second address electrode.

Referring to the drawing, the second address electrode 13b is driven to scan. When the address voltage Va is applied to the second address electrode 13b and crosses the second address electrode 13b ( When a scan pulse is applied to 11, the second address electrode 13b and the Y electrode 11 scan drive to address the corresponding discharge cells 7R, 7G, and 7B. At this time, the address voltage Va applied to the second address electrode 13b is grounded through the resistor 21 and the first address electrode 13a connected thereto after the scan driving (path b).

The first and second address electrodes 13a and 13b simultaneously perform a scan drive while interacting with the Y electrodes 11 on each side.

As described above, the PDP realizes scan driving on both sides of the PDP simultaneously by the first address electrode 13a, the second address electrode 13b, and the corresponding Y electrodes 11 and 11, thereby scanning in one subfield. Shorten the time taken by the period.

In addition, the PDP electrically connects the first and second address electrodes 13a and 13b through resistors 21 provided between the first and second address electrodes 13a and 13b, thereby eliminating unnecessary connection therebetween. The discharge is prevented from occurring, and after the scan driving, the address voltage Va on one side is grounded to the other side to stably realize the driving of the PDP, that is, the dual scan driving.

After this scan period, the addressed discharge cells 7R, 7G, and 7B emit light by applying discharge sustain voltages to the X and Y electrodes 9 and 11 to realize an image. At this time, as the sustaining period becomes longer, the light emission efficiency of the discharge cells 7R, 7G, and 7B is improved.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to the scope of the invention.

As described above, according to the plasma display panel according to the present invention, resistors are provided in gaps at the ends of the first and second address electrodes separately formed on the second substrate for dual scan driving. When the address voltage is applied while the address electrodes are electrically connected, each of the first and second address electrodes is grounded to apply an address voltage to the first or second address electrode and a scan pulse to the corresponding Y electrode to discharge the discharge cell. In the scan driving addressing, an unnecessary discharge is prevented from occurring at the ends of the first and second address electrodes located in the gap, thereby enabling stable driving of the PDP.

Claims (10)

A first substrate and a second substrate facing each other while maintaining a spacing; Barrier ribs disposed in a space between the first substrate and the second substrate to form discharge cells; Phosphor layers formed in the discharge cells; Discharge sustain electrodes formed on a first substrate corresponding to each of the discharge cells; And Address electrodes formed on the second substrate to cross the discharge sustain electrodes; Including; The address electrodes extend to the other side of the second substrate while maintaining a gap corresponding to the first address electrodes on the first side of the second substrate and the first surface of the second substrate. A second address electrode formed; A tip located on the gap side of the first address electrode is grounded through the second address electrode located on the opposite side, and a tip located on the gap side of the second address electrode is connected through the first address electrode located on the opposite side of the first address electrode. Grounded plasma display panel. delete delete The method of claim 1, A resistor is provided in the gap, and the plasma display panel interconnects corresponding ends of the first address electrode and the second address electrode. The method of claim 4, wherein And the first address electrode is grounded through a resistor provided in a gap and a second address electrode. The method of claim 4, wherein And the second address electrode is grounded through a resistor provided in the gap and the first address electrode. The method of claim 4, wherein And the resistor has an electrical resistance higher than that of the address electrode. The method of claim 4, wherein And the resistor is formed at a position corresponding to a non-discharge area formed between discharge cells. The method of claim 4, wherein And the resistor is formed independently of each address electrode. The method of claim 1, And the first address electrode and the second address electrode have a stripe shape.

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