KR100596768B1 - Chemical mechanical polishing method for semiconductor apparatus - Google Patents

Chemical mechanical polishing method for semiconductor apparatus Download PDF

Info

Publication number
KR100596768B1
KR100596768B1 KR1019990046077A KR19990046077A KR100596768B1 KR 100596768 B1 KR100596768 B1 KR 100596768B1 KR 1019990046077 A KR1019990046077 A KR 1019990046077A KR 19990046077 A KR19990046077 A KR 19990046077A KR 100596768 B1 KR100596768 B1 KR 100596768B1
Authority
KR
South Korea
Prior art keywords
polishing
chemical mechanical
mechanical polishing
semiconductor device
film
Prior art date
Application number
KR1019990046077A
Other languages
Korean (ko)
Other versions
KR20010038194A (en
Inventor
조영아
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019990046077A priority Critical patent/KR100596768B1/en
Publication of KR20010038194A publication Critical patent/KR20010038194A/en
Application granted granted Critical
Publication of KR100596768B1 publication Critical patent/KR100596768B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 화학기계적연마 방법에 관한 것으로, 종래에는 각 단계별로 사용하는 공정조건을 다르게 적용 할 경우 공정불안 및 장비의 불안정 요인이 될 수 있고, 제 2단계에서 느린 제거비의 조건을 적용함에따라 균일도 악화와 산화막 침식이 심해지며, 서로다른 선택비를 가지는 슬러리를 사용 할 경우 두개 이상의 슬러리 라인이 필요하게되는 문제점이 있었다. 따라서, 본 발명은 반도체소자가 형성된 반도체기판 상부에 절연막을 증착하고, 그 절연막에 형성된 컨택을 통해 상기 반도체소자의 특정영역에 접속되는 금속배선을 형성하기위해 상기 컨택상에 홀을 형성하고 그 상부에 배리어막을 형성한 후 그 상부에 텅스텐막을 증착하고 이를 평탄화하는 화학기계적연마 방법에 있어서, 상기 형성된 텅스텐막을 평탄도가 우수한 고압 및 고속의 조건에서 화학기계적연마를 실시하여 일부를 제거하는 제 1단계 연마공정과; 상기 웨이퍼의 표면에 잔류하는 텅스텐막을 상기 제 1단계 연마공정과 동일한 조건에서 상기 사용한 슬러리를 순수로 희석한 것을 사용하여 연마하는 제 2단계 연마공정을 포함하여 이루어지는 반도체장치의 화학기계적연마 방법을 통해 별도의 슬러리 라인이 필요하지 않고, 고압 및 고속조건을 사용하므로 공정시간이 단축됨과 아울러 평탄도가 향상되어 연마 후 세정이 쉽고 과연마 시간이 감소함과 동시에 텅스텐의 선택비가 향상되어 산화막의 침식이 감소하며, 각 단계에 의한 공정조건의 변화가 없어 장비의 불안정을 미연에 방지 할 수 있는 효과가 있다. The present invention relates to a chemical mechanical polishing method of a semiconductor device, and in the related art, when different process conditions are used for each step, process instability and equipment instability can be caused, and the condition of slow removal ratio is applied in the second step. Deterioration of the uniformity and the erosion of the oxide film is severe, and when using a slurry having a different selectivity, there was a problem that two or more slurry lines are required. Therefore, the present invention deposits an insulating film on the semiconductor substrate on which the semiconductor device is formed, and forms a hole on the contact and forms a hole on the contact to form a metal wiring connected to a specific region of the semiconductor device through the contact formed on the insulating film. In the chemical mechanical polishing method of forming a barrier film on the top and depositing a tungsten film on the top and flattening the first step, the first step of removing a part of the formed tungsten film by performing chemical mechanical polishing under high pressure and high speed conditions with excellent flatness Polishing process; Through a chemical mechanical polishing method of a semiconductor device comprising a second step polishing step of polishing the tungsten film remaining on the surface of the wafer using the diluted slurry of pure water under the same conditions as the first step polishing step. It does not require a separate slurry line and uses high pressure and high speed conditions, which shortens the process time and improves flatness, so it is easy to clean after polishing, reduces over-polishing time, and improves the selectivity of tungsten. It is reduced, and there is no change in process conditions by each step, which can prevent the instability of equipment in advance.

Description

반도체장치의 화학기계적연마 방법{CHEMICAL MECHANICAL POLISHING METHOD FOR SEMICONDUCTOR APPARATUS}Chemical mechanical polishing method for semiconductor devices {CHEMICAL MECHANICAL POLISHING METHOD FOR SEMICONDUCTOR APPARATUS}

도 1은 화학기계적연마 과정을 보인 수순단면도.1 is a cross-sectional view showing a process of chemical mechanical polishing.

*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***

1 : 반도체기판 2 : 산화막1: semiconductor substrate 2: oxide film

3 : 컨택 4 : 티타늄3: contact 4: titanium

5 : 티타늄질화막 6 : 텅스텐막5: titanium nitride film 6: tungsten film

본 발명은 반도체장치의 화학기계적연마 방법에 관한 것으로, 특히 2단계를 통해서 텅스텐을 화학기계적연마(2 step metal Chemical Mechanical Polishing)함에 있어서 화학기계적연마용 슬러리(slurry)의 텅스텐 선택비 감소로 인하여 발생하는 산화막 침식(oxide erosion)을 감소시키고 공정속도를 개선하기에 적당하도록 한 반도체장치의 화학기계적연마 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for chemical mechanical polishing of semiconductor devices, in particular due to the reduction of the tungsten selectivity of the slurry for chemical mechanical polishing in the two step metal chemical mechanical polishing process. The present invention relates to a chemical mechanical polishing method of a semiconductor device which is suitable for reducing oxide erosion and improving process speed.

일반적인 텅스텐의 화학기계적연마 방법을 도 1a 내지 도1c의 수순단면도를 참조하여 설명하면 다음과 같다.A general chemical mechanical polishing method of tungsten is described below with reference to the procedure cross-sectional view of FIGS. 1A to 1C.

반도체소자(미도시)가 형성된 반도체기판(1) 상부에 차례로 산화막(2), 컨택(3)을 형성하고, 금속막이 증착될 영영에 맞추어 컨택(3)의 일부를 건식각한 다음 그 구조물 상부에 차례로 티타늄(4), 티타늄질화막(5), 텅스텐막(6)을 증착하는 금속막 형성공정과; 상기 형성된 텅스텐막을 화학기계적연마를 통하여 일부 제거하는 제 1단계 연마공정과; 상기 잔류하는 텅스텐막을 상기 산화막(2)이 드러나도록 연마하는 제 2단계 연마공정으로 이루어진다.The oxide film 2 and the contact 3 are sequentially formed on the semiconductor substrate 1 on which the semiconductor device (not shown) is formed, and a part of the contact 3 is dry-etched in accordance with the region on which the metal film is to be deposited, and then the upper portion of the structure. A metal film forming step of depositing titanium (4), titanium nitride film (5), and tungsten film (6) in turn; A first step of polishing to partially remove the formed tungsten film through chemical mechanical polishing; The remaining tungsten film is subjected to a second step polishing step in which the oxide film 2 is exposed.

종래 반도체장치의 화학기계적연마 방법을 첨부한 도 1a 내지 도1c의 일반적인 화학기계적연마 방법의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.Referring to the procedure cross-sectional view of the general chemical mechanical polishing method of Figures 1a to 1c attached to the conventional chemical mechanical polishing method of the semiconductor device as follows.

먼저, 도 1a에 도시한 바와같이 반도체소자(미도시)가 형성된 반도체기판(1) 상부에 산화막(2)을 증착하고, 반도체소자(미도시)에 연결되는 컨택(3)을 형성하 고, 금속막이 증착될 영영에 맞추어 컨택(3)의 일부를 건식각한 다음 그 구조물 상부전면에 차례로 텅스텐막(6)과 컨택(3)의 접착성 향상을 위한 티타늄(4)과, 텅스텐막(6)과 컨택(3)의 반응을 방지하기위한 티타늄질화막(5)을 증착한 후 그 상부 전면에 텅스텐막(6)을 화학기상증착 방식으로 증착한다.First, as illustrated in FIG. 1A, an oxide film 2 is deposited on a semiconductor substrate 1 on which a semiconductor device (not shown) is formed, and a contact 3 connected to the semiconductor device (not shown) is formed. A part of the contact 3 is dry-etched in accordance with the region in which the metal film is to be deposited, and then titanium (4) and tungsten film (6) for improving the adhesion between the tungsten film 6 and the contact 3 on the upper surface of the structure. Titanium nitride film (5) to prevent the reaction of the) and the contact (3) is deposited, and then a tungsten film (6) is deposited on the entire upper surface by chemical vapor deposition.

그 다음, 도 1b에 도시한 바와같이 빠른 연마를 위한 슬러리를 사용하거나, 빠른 제거비(removal rate)를 가지는 공정조건을 적용하여 상기 형성한 텅스텐막(6)의 일부를 연마하여 제거한다.Next, as shown in FIG. 1B, a part of the formed tungsten film 6 is polished and removed by using a slurry for fast polishing or by applying process conditions having a fast removal rate.

그 다음, 도 1c에 도시한 바와같이 세밀한 연마를 위하여 느린 연마를 위한 슬러리를 사용하거나, 느린 제거비를 가지는 공정조건을 적용하여 상기 잔류하는 텅스텐막(6)을 상기 산화막(2)이 드러나도록 연마한다.Then, as shown in FIG. 1C, polishing the remaining tungsten film 6 to expose the oxide film 2 by using a slurry for slow polishing for fine polishing or by applying a process condition having a slow removal ratio. do.

즉, 제 1단계 연마공정에서 빠른 제거비를 가지는 조건을 적용한 경우에는 제 2단계의 연마공정에서는 느린 제거비를 가지는 공정조건을 적용하고, 서로다른 슬러리를 사용하는 경우에는 상기 제 1단계 연마공정과 제 2단계 연마공정에서 산화막(2)에 대한 텅스텐막(6)의 선택비가 서로 다른 슬러리를 사용하여 연마한다. That is, when a condition having a fast removal ratio is applied in the first step polishing step, a process condition having a slow removal ratio is applied in the second step polishing step, and when using different slurries, the first step and the first step In the two-step polishing step, polishing is performed using slurries having different selectivity ratios of the tungsten film 6 to the oxide film 2.

그러나, 상기한 바와 같은 종래 반도체장치의 화학기계적연마 방법은 각 단계별로 사용하는 공정조건을 다르게 적용 할 경우 공정불안 및 장비의 불안정 요인이 될 수 있고, 제 2단계에서 느린 제거비의 조건을 적용함에따라 균일도 악화와 산화막 침식이 심해지며, 서로다른 선택비를 가지는 슬러리를 사용 할 경우 두개 이상의 슬러리 라인이 필요하게되는 문제점이 있었다. However, the chemical mechanical polishing method of the conventional semiconductor device as described above may cause process instability and instability of equipment when different process conditions are used in each step, and in the second step, the condition of slow removal ratio is applied. As a result, uniformity deterioration and oxide erosion worsen, and there is a problem in that two or more slurry lines are required when using slurry having different selectivity.                         

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 순수에 희석시킨 슬러리를 사용함으로써 모든 단계에서 빠른 제거비를 가지는 공정조건을 사용하여 양산시간을 줄이고 산화막 침식을 감소시킬 수 있는 반도체장치의 화학기계적연마 방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to reduce the mass production time and reduce the erosion of the oxide film by using a process condition having a fast removal ratio at all stages by using a slurry diluted in pure water. The present invention provides a method for chemical mechanical polishing of a semiconductor device that can be reduced.

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체장치의 화학기계적연마 방법은 반도체소자가 형성된 반도체기판 상부에 상기 반도체소자의 특정영역을 노출시키는 컨택 홀을 갖는 절연막을 형성하고, 상기 절연막 상에 상기 컨택 홀을 통해 상기 반도체소자의 노출된 특정영역과 접촉되게 베리어막을 형성한 후 그 상부에 텅스텐막을 상기 컨택 홀을 채우도록 증착하고 평탄화하는 화학기계적연마 방법에 있어서, 상기 증착된 텅스텐막을 평탄도가 우수한 고압 및 고속의 조건에서 화학기계적연마를 실시하여 일부 두께 제거하는 제 1단계 연마공정과; 상기 텅스텐막의 연마되지 않은 나머지 두께와 상기 베리어막을 상기 제 1단계 연마공정과 동일한 조건에서 상기 사용한 슬러리를 순수로 희석한 것을 사용하여 연마하는 제 2단계 연마공정을 포함한다. The chemical mechanical polishing method of a semiconductor device for achieving the object of the present invention as described above forms an insulating film having a contact hole for exposing a specific region of the semiconductor device on the semiconductor substrate on which the semiconductor device is formed, and on the insulating film In the chemical mechanical polishing method of forming a barrier film in contact with the exposed specific region of the semiconductor device through the contact hole and depositing and planarizing a tungsten film to fill the contact hole on the top, the deposited tungsten film is flatness A first step of polishing to remove a part of the thickness by performing chemical mechanical polishing under conditions of excellent high pressure and high speed; And a second step polishing step of polishing the remaining thickness of the tungsten film and the barrier film using pure dilution of the used slurry under the same conditions as the first step polishing step.

상기한 바와 같은 본 발명에 의한 반도체장치의 화학기계적연마 방법을 상기 일반적인 화학기계적연마의 수순을 나타낸 도 1a 내지 도1c의 수순단면도를 참고하여 상세히 설명하면 다음과 같다.The chemical mechanical polishing method of the semiconductor device according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1C showing the general chemical mechanical polishing procedure.

먼저, 도 1a에 도시한 바와같이 반도체소자(미도시)가 형성된 반도체기판(1) 상부에 산화막(2)을 증착하고, 반도체소자(미도시)에 연결되는 컨택(3)을 형성하고, 금속막이 증착될 영영에 맞추어 컨택(3)의 일부를 크기는 0.1~0.2㎛, 높이는 1000~4000Å이 되도록 건식각한 다음 그 구조물 상부전면에 차례로 텅스텐막(6)과 컨택(3)의 접착성 향상을 위한 티타늄(4)과, 텅스텐막(6)과 컨택(3)의 반응을 방지하기위한 티타늄질화막(5)을 증착하여 배리어막을 형성하는데, 물리기상증착방식으로 증착하는경우 티타늄(4)/티타늄질화막(5)을 300~800Å정도 증착하고, 화학기상증착방식으로 증착하는경우에는 티타늄질화막(5)만을 300~800Å정도 증착한다. First, as illustrated in FIG. 1A, an oxide film 2 is deposited on a semiconductor substrate 1 on which a semiconductor device (not shown) is formed, a contact 3 connected to a semiconductor device (not shown) is formed, and a metal A part of the contact 3 is dry etched to have a size of 0.1 to 0.2 µm and a height of 1000 to 4000 mm in accordance with the film to be deposited, and then the adhesion between the tungsten film 6 and the contact 3 is sequentially improved on the upper surface of the structure. To form a barrier film by depositing titanium (4) for deposition and titanium nitride film (5) for preventing the reaction of the tungsten film (6) and the contact (3). The titanium nitride film 5 is deposited at about 300 to 800 mW, and in the case of vapor deposition by chemical vapor deposition, only the titanium nitride film 5 is deposited at about 300 to 800 mW.

상기 형성한 배리어막의 상부전면에 텅스텐막(6)을 화학기상증착 방식으로 1000~10000Å증착한다The tungsten film 6 is deposited on the upper surface of the formed barrier film by 1000 to 10,000 kPa by chemical vapor deposition.

그 다음, 도 1b에 도시한 바와같이 상기 형성된 텅스텐막(6)을 제거비가 4000Å/min이상으로 연마하는데, 연마 압력은 3~10 psi, 연마판(platen)의 속도는 30~120 rpm, 캐리어(carrier)의 속도는 30~120rpm, 슬러리의 유량은 100~200㎖/min의 조건에서 화학기계적연마를 실시하여 2/3정도를 연마한다. 이때, 상기와 같이 고압 및 고속으로 연마를 실시하면 평탄도가 우수해진다.Then, as shown in FIG. 1B, the formed tungsten film 6 is polished with a removal ratio of 4000 kPa / min or more, the polishing pressure is 3 to 10 psi, the speed of the plate is 30 to 120 rpm, the carrier The carrier speed is 30 ~ 120rpm and the slurry flow rate is about 2/3 by chemical mechanical polishing under the condition of 100 ~ 200ml / min. At this time, when the polishing at high pressure and high speed as described above, the flatness is excellent.

그다음, 도 1c에 도시한 바와같이 상기 웨이퍼의 표면에 잔류하는 텅스텐막(6)을 상기 제 1단계 연마공정과 동일한 조건에서 상기 사용한 슬러리만을 순수(Deionized Water)로 희석한 것을 사용하여 연마하는데, 순수로 희석시키기위해 믹서를 이용하여 상기 제 1단계에서 사용한 슬러리와 순수를 슬러리 내부의 고형질 농도(solid concentration)가 낮아지도록 잘 섞어서 사용함으로써 산화막에 대한 텅스텐의 선택비를 향상시키고 산화막의 침식을 억제 할 수 있다.Then, as shown in FIG. 1C, the tungsten film 6 remaining on the surface of the wafer is polished by diluting only the used slurry with deionized water under the same conditions as the first step polishing process. By using a mixer to dilute with pure water, the slurry used in the first step and pure water are mixed well to lower the solid concentration in the slurry, thereby improving the selectivity of tungsten to the oxide film and reducing the erosion of the oxide film. Can be suppressed.

상기 순수와 혼합한 슬러리를 사용할 경우와 기존의 슬러리를 사용하는 경우에 대한 제거비와 평탄도 및 산화막에 대한 텅스텐의 선택비는 하기 표 1에 나타낸 바와 같다.The removal ratio, the flatness, and the selectivity of tungsten to the oxide film when using the slurry mixed with the pure water and when using the conventional slurry are shown in Table 1 below.

공정조건Process conditions 제거비Removal cost 평탄도flatness 선택비Selectivity 압력pressure 속도speed 슬러리Slurry [Å/min][Å / min] [%][%] 산화막에 대한 텅스텐의 선택비Selectivity of Tungsten to Oxides A조건A condition 고압High pressure 고속high speed 기존existing 38003800 5.545.54 55.855.8 고압High pressure 고속high speed 순수로 희석Dilute with pure 23002300 11.211.2 6363 B조건B condition 고압High pressure 저속sleaze 기존existing 26002600 1212 83.383.3 고압High pressure 저속sleaze 순수로 희석Dilute with pure 13001300 14.314.3 78.278.2 C조건C condition 저압Low pressure 고속high speed 기존existing 30003000 14.914.9 26.826.8 저압Low pressure 고속high speed 순수로 희석Dilute with pure 17001700 7.17.1 34.734.7

상기 표 1에 나타낸 바와 같이 공정의 조건을 바꾸어 가면서 측정한 결과 같은 공정조건에서 기존의 슬러리를 이용할 경우와 비교하여 순수로 희석한 슬러리는 상기 모든 조건에서 1000~1500Å/min의 제거비가 감소하여 속도는 낮아지지만 산화막에 대한 텅스텐의 선택비는 고속의 조건인 A조건과 C조건에서 높아지게 되며 고압의 조건을 이용한 A조건과 B조건에서는 평탄도가 향상됨을 알 수 있다. As shown in Table 1, as a result of measuring the process conditions, the slurries diluted with pure water compared to the case of using the existing slurry under the same process conditions, the removal rate of 1000 ~ 1500 Å / min under all the above conditions reduced the speed Although t is lowered, the selectivity of tungsten to the oxide film is increased under conditions A and C, which are high speed conditions, and the flatness is improved under conditions A and B using high pressure conditions.

상기 각 조건의 일 실시예로써 3000Å의 텅스텐을 화학기계적연마를 통해 연마 완료되는 시간을 측정하는데, 상기 설명한 바와같이 제 1연마공정에서 2/3에 해당히는 2000Å을 연마하고, 순수로 희석한 슬러리를 사용한 제 2연마공정에서 1/3에 해당하는 1000Å을 연마하는데 걸린 시간을 하기 표 2에 나타내었다.As an example of each of the above conditions, the polishing time of 3000 tungsten was measured by chemical mechanical polishing. As described above, in the first polishing process, 2/3 of 2000 tungsten was ground and diluted with pure water. In the second polishing process using the slurry, the time taken to polish 1000 Å corresponding to 1/3 is shown in Table 2 below.

조 건Condition 제 1연마공정First polishing process 제 2연마공정Second Grinding Process 총 소요시간Total Time A조건A condition 32sec32sec 26sec26sec 58sec58sec B조건B condition 46sec46sec 46sec46sec 92sec92sec C조건C condition 40sec40sec 35sec35sec 75sec75sec

상기 표 2에 의해 고압 및 고속의 조건을 이용한 A조건에서 가장빠른 공정시간을 얻을 수 있음을 알 수 있다.Table 2 shows that the fastest process time can be obtained under A condition using high pressure and high speed conditions.

상기 상세히 설명한 본 발명을 정리하면, 텅스텐막(6)을 화학기계적연마를 통하여 평탄화함에있어서 제 1연마공정에서는 고압 및 고속의 조건에서 2/3를 연마하고, 제 2연마공정에서는 상기 제 1연마공정과 같은 고압과 고속의 조건에서 슬러리만을 순수를 이용하여 슬러리 내의 고형질 농도가 낮아지도록 잘 희석하여 사용하여 웨이퍼 표면에 잔류하는 텅스텐막(6)을 연마하면, 빠른속도로 균일하게 연마할 수 있을 뿐만 아니라 산화막에 대한 텅스텐의 선택비가 높아져 산화막의 침식을 감소시킬 수 있다. In summary, the present invention described in detail above, in the planarization of the tungsten film 6 through chemical mechanical polishing, in the first polishing process, two thirds are polished under high pressure and high speed, and in the second polishing process, the first polishing is performed. When the tungsten film (6) remaining on the surface of the wafer is polished by diluting the slurry with pure water so that the solid concentration in the slurry is lowered under high pressure and high speed conditions such as the process, it can be uniformly polished at high speed. In addition, the selectivity of tungsten to the oxide film is increased, thereby reducing the erosion of the oxide film.

상기한 바와 같은 본 발명에 의한 반도체장치의 화학기계적연마 방법은 한 종류의 슬러리만을 이용하므로 별도의 슬러리 라인이 필요하지 않고, 순수로 희석한 슬러리를 제거비가 높은 고압 및 고속조건에서 사용하므로 공정시간이 단축됨과 아울러 평탄도가 향상되어 연마 후 세정이 쉽고 과연마 시간(over polishing time)이 감소함과 동시에 텅스텐의 선택비가 향상되어 산화막의 침식이 감소하며, 각 단계에 의한 공정조건의 변화가 없어 장비의 불안정을 미연에 방지 할 수 있는 효과가 있다.The chemical mechanical polishing method of the semiconductor device according to the present invention as described above does not require a separate slurry line because only one type of slurry is used, and because the slurry diluted with pure water is used under high pressure and high speed with high removal ratio, process time In addition to the shortening and improved flatness, it is easy to clean after polishing, reduce over polishing time, and improve the selectivity of tungsten to reduce erosion of oxide film, and there is no change of process condition by each step. It is effective to prevent instability of equipment.

Claims (6)

반도체소자가 형성된 반도체기판 상부에 상기 반도체소자의 특정영역을 노출시키는 컨택 홀을 갖는 절연막을 형성하고, 상기 절연막 상에 상기 컨택 홀을 통해 상기 반도체소자의 노출된 특정영역과 접촉되게 베리어막을 형성한 후 그 상부에 텅스텐막을 상기 컨택 홀을 채우도록 증착하고 평탄화하는 화학기계적연마 방법에 있어서,An insulating film having a contact hole for exposing a specific area of the semiconductor device is formed on the semiconductor substrate on which the semiconductor device is formed, and a barrier film is formed on the insulating film to be in contact with the exposed specific area of the semiconductor device through the contact hole. In the chemical mechanical polishing method of depositing and planarizing a tungsten film to fill the contact hole thereon, 상기 증착된 텅스텐막을 평탄도가 우수한 고압 및 고속의 조건에서 화학기계적연마를 실시하여 일부 두께 제거하는 제 1단계 연마공정과; A first step polishing step of removing the thickness of the deposited tungsten film by performing chemical mechanical polishing under high pressure and high speed with excellent flatness; 상기 텅스텐막의 연마되지 않은 나머지 두께와 상기 베리어막을 상기 제 1단계 연마공정과 동일한 조건에서 상기 사용한 슬러리를 순수로 희석한 것을 사용하여 연마하는 제 2단계 연마공정을 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 화학기계적연마 방법.And a second step polishing step in which the remaining thickness of the tungsten film and the barrier film are polished by diluting the used slurry with pure water under the same conditions as the first step polishing step. Chemical mechanical polishing method. 제 1항에 있어서, 상기 텅스텐막을 텅스텐의 제거비가 4000Å/min이상인 공정조건에서 제 1단계 연마공정에서는 2/3, 제 2단계 연마공정에서는 1/3을 연마하는 것을 특징으로하는 반도체장치의 화학기계적연마 방법.2. The chemistry of the semiconductor device according to claim 1, wherein the tungsten film is polished at 2/3 in the first polishing step and 1/3 in the second polishing step under process conditions in which the removal rate of tungsten is 4000 mW / min or more. Mechanical polishing method. 제 1항에 있어서, 상기 화학기계적연마의 공정조건은 연마 압력은 3~10 psi, 연마판의 속도는 30~120 rpm, 캐리어의 속도는 30~120rpm, 슬러리 유량은 100~200㎖/min인 것을 특징으로하는 반도체장치의 화학기계적연마 방법.The process conditions of the chemical mechanical polishing is a polishing pressure of 3 ~ 10 psi, the polishing plate speed of 30 ~ 120 rpm, the carrier speed of 30 ~ 120rpm, slurry flow rate is 100 ~ 200ml / min A method of chemical mechanical polishing of a semiconductor device, characterized in that. 제 1항에 있어서, 상기 텅스텐막 하부에 형성된 컨택상의 홀의 크기는 0.1~0.2㎛이고, 높이는 1000~4000Å임을 특징으로하는 반도체장치의 화학기계적연마 방법.The method of claim 1, wherein the contact hole formed in the lower portion of the tungsten film has a size of 0.1 to 0.2 µm and a height of 1000 to 4000 microns. 제 1항에 있어서, 상기 텅스텐막 하부에 형성하는 배리어층은 물리기상증착방식으로 티타늄/티타늄질화막을 300~800Å증착하거나 화학기상증착방식으로 티타늄질화막을 300~800Å증착하는 것을 특징으로하는 반도체장치의 화학기계적연마 방법.2. The semiconductor device according to claim 1, wherein the barrier layer formed under the tungsten film is formed by depositing 300-800 kW of the titanium / titanium nitride film by physical vapor deposition or 300-800 kW of the titanium nitride film by chemical vapor deposition. Chemical mechanical polishing method. 제 1항에 있어서, 상기 텅스텐막은 1000~10000Å증착하는 것을 특징으로하는 반도체장치의 화학기계적연마 방법.A method of chemical mechanical polishing of a semiconductor device according to claim 1, wherein the tungsten film is deposited at 1000 to 10,000 kPa.
KR1019990046077A 1999-10-22 1999-10-22 Chemical mechanical polishing method for semiconductor apparatus KR100596768B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990046077A KR100596768B1 (en) 1999-10-22 1999-10-22 Chemical mechanical polishing method for semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990046077A KR100596768B1 (en) 1999-10-22 1999-10-22 Chemical mechanical polishing method for semiconductor apparatus

Publications (2)

Publication Number Publication Date
KR20010038194A KR20010038194A (en) 2001-05-15
KR100596768B1 true KR100596768B1 (en) 2006-07-04

Family

ID=19616532

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990046077A KR100596768B1 (en) 1999-10-22 1999-10-22 Chemical mechanical polishing method for semiconductor apparatus

Country Status (1)

Country Link
KR (1) KR100596768B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100732310B1 (en) * 2001-06-28 2007-06-25 주식회사 하이닉스반도체 Method for chemical mechanical polishing of semiconductor device
KR100587601B1 (en) * 2003-12-15 2006-06-08 매그나칩 반도체 유한회사 planarization method of semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0955362A (en) * 1995-08-09 1997-02-25 Cypress Semiconductor Corp Manufacture of integrated circuit for reduction of scratch
KR970023786A (en) * 1995-10-20 1997-05-30 김광호 Polishing method of silicon on insulator (SOI) wafer
KR19980048378A (en) * 1996-12-17 1998-09-15 김광호 Planarization method of semiconductor device
KR19980063426A (en) * 1996-12-13 1998-10-07 포만제프리엘 Improvements to Chemical-Mechanical Polishing of Semiconductor Wafers
JPH10270399A (en) * 1997-03-24 1998-10-09 Motorola Inc Method for polishing different conductive layer in semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0955362A (en) * 1995-08-09 1997-02-25 Cypress Semiconductor Corp Manufacture of integrated circuit for reduction of scratch
KR970023786A (en) * 1995-10-20 1997-05-30 김광호 Polishing method of silicon on insulator (SOI) wafer
KR19980063426A (en) * 1996-12-13 1998-10-07 포만제프리엘 Improvements to Chemical-Mechanical Polishing of Semiconductor Wafers
KR19980048378A (en) * 1996-12-17 1998-09-15 김광호 Planarization method of semiconductor device
JPH10270399A (en) * 1997-03-24 1998-10-09 Motorola Inc Method for polishing different conductive layer in semiconductor device

Also Published As

Publication number Publication date
KR20010038194A (en) 2001-05-15

Similar Documents

Publication Publication Date Title
US6350694B1 (en) Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials
US6638863B2 (en) Electropolishing metal layers on wafers having trenches or vias with dummy structures
US5302233A (en) Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP)
KR100271769B1 (en) Method for manufacturing semiconductor device, etchant composition and semiconductor device for manufacturing semiconductor device therefor
JP2001148386A (en) Barrier layer buff processing after copper cmp
KR19990077428A (en) Chemical mechanical polishing of multiple material substrates and slurry having improved selectivity
CA2456225A1 (en) Forming a semiconductor structure using a combination of planarizing methods and electropolishing
US6443807B1 (en) Polishing process for use in method of fabricating semiconductor device
US20040253809A1 (en) Forming a semiconductor structure using a combination of planarizing methods and electropolishing
US20060261041A1 (en) Method for manufacturing metal line contact plug of semiconductor device
US6114215A (en) Generating non-planar topology on the surface of planar and near-planar substrates
US20030119324A1 (en) Method for manufacturing metal line contact plug of semiconductor device
KR100596768B1 (en) Chemical mechanical polishing method for semiconductor apparatus
US6395635B1 (en) Reduction of tungsten damascene residue
KR100645841B1 (en) Polysilicon Plug Forming Method Using Abrasive Stopping Film
KR100444311B1 (en) Method for manufacturing isolation layer of semiconductor device using two-step cmp processes
KR19990073000A (en) Method of forming a semiconductor device
KR100197994B1 (en) Method for forming a contact hole in semiconductor device
KR100390838B1 (en) Method for forming landing plug contact in semiconductor device
US7074702B2 (en) Methods of manufacturing semiconductor devices
US6899597B2 (en) Chemical mechanical polishing (CMP) process using fixed abrasive pads
KR100403197B1 (en) Method of forming a metal wiring in a semiconductor device
KR20010058992A (en) Method for fabricating using chemical mechanical polishing
KR100560288B1 (en) A method for forming isolation layer of semiconductor device
JP2002270557A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee