KR100594325B1 - Method of manufacturing semiconductor device having notched gate mosfet - Google Patents

Abstract

The cell transistor formed in the cell array region adopts a notched gate structure transistor capable of multi-bit operation using localized bits while applying a spacer electrode to the gate, and in the peripheral circuit region according to the function of the transistor. Disclosed is a method of manufacturing a semiconductor device for forming a transistor having a structure optimized to satisfy different requirements. In the method of manufacturing a semiconductor device according to the present invention, a notch gate structure, a first channel region formed in a semiconductor substrate under the notched gate structure, and the first channel region are disposed at both sides of a cell array region of the semiconductor substrate. A source / drain region to be formed; a first gate insulating layer formed between the first channel region and the notch gate structure; and a source / drain region between the first channel region and the notch gate structure. A cell transistor including a memory layer locally formed in an adjacent region is formed. A plurality of peripheral circuit transistors including at least one transistor having a structure different from that of the cell transistor are formed in the peripheral circuit region at the same time as the cell transistor formation.

Notch Gate, Multi-Bit, Cell Array, Peripheral, Process Integration, SONOS

Description

A method of manufacturing a semiconductor device having a transistor having a notched gate structure

1A to 1O are cross-sectional views illustrating a manufacturing method of a semiconductor device according to a first embodiment of the present invention in order of processing.

2A through 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, according to a process sequence.

3A to 3K are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention, according to a process sequence.

4A through 4N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention, according to a process sequence.

<Explanation of symbols for the main parts of the drawings>

Reference Signs List 100: semiconductor substrate, 102: device isolation region, 112: lower oxide film, 114: memory layer, 116: upper oxide film, 120: dummy pattern, 120h: opening, 132: first insulating film, 134: first photoresist pattern, 140 : First conductive layer, 142: oxide film, 150: second conductive layer, 162: second photoresist pattern, 164: extension region, 166: third photoresist pattern, 168: extension region, 170: insulating spacer, 172: Source / drain region, 174 recess region, 180: metal silicide film.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to facilitate process integration in forming a transistor capable of multi-bit operation in a cell array region simultaneously with a metal oxide semiconductor field effect transistor (MOSFET) in a peripheral circuit region. A method for manufacturing a semiconductor device.

Recently, as a form of nonvolatile memory devices widely used in mobile communication systems, memory cards, etc., they are referred to as silicon-oxide-nitride-oxide-silicon (SONOS) or metal-oxide-nitride-oxide-silicon (MONOS). Types of nonvolatile memory devices have been proposed. Most of the SONOS type semiconductor memory devices proposed so far employ a stacked SONOS type transistor structure in which the ONO structure exists over the entire channel region of the transistor. In such a structure, since the ONO structure exists throughout the channel region of the transistor, it has a high initial threshold voltage (Vth) and a high program current in the cell transistor. Therefore, due to the high initial Vth, it is difficult to integrate on one chip with other logic products having a low initial Vth. Further, in the stacked SONOS cell transistor, electrons accumulated in the storage node layer in ONO may move in the horizontal direction along the storage node layer, and thus the erase operation may not be performed intact. Moreover, as the FET is highly scaled with the rapid development of the semiconductor industry, various problems are generated, such as an increase in the leakage current with the reduction of the device size.

Meanwhile, in order to operate a general flash memory device, in addition to a cell transistor array formed in a cell array region, an LV (low voltage) formed in a peripheral circuit region and a core region (hereinafter, simply referred to as a “peripheral circuit region”). MOSFET or HV (high voltage) MOSFET circuit block, e.g. P / E controller, data load latch, word line decoder, address buffer, sense It is necessary to form circuit blocks such as amplifiers. In order to integrate a cell transistor array having a storage node and a circuit block of a peripheral circuit region on a single chip, such as a SONOS structure, efficient process integration between the cell array region and the peripheral circuit region is required. In particular, when forming a cell transistor having a multi-bit operable structure using localized bits, a process of forming a cell transistor array in a cell array region and a high voltage transistor in a peripheral circuit region And in order to maintain a unique function and electrical characteristics of each transistor in the process of simultaneously forming a low voltage transistor, transistors having a structure designed separately for each function can be easily implemented without increasing the process difficulty. Process design is required.

The present invention is to solve the above problems in the prior art, while solving the problems associated with the formation of a transistor having a reduced size required in the scaling technology for the ultra-high integration device implementation, and at the same time multi-bit operation A semiconductor device manufacturing method capable of easily integrating a cell transistor forming process and a transistor forming process for peripheral circuits is provided.

In order to achieve the above object, in the method of manufacturing a semiconductor device according to the present invention, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. A notch gate structure in the cell array region of the semiconductor substrate, a first channel region formed in the semiconductor substrate under the notch gate structure, a source / drain region formed on both sides of the first channel region, and the first channel region interposed therebetween A first gate insulating layer formed between the channel region and the notched gate structure, and a memory layer locally formed in an area adjacent to the source / drain region between the first channel region and the notched gate structure. A cell transistor is formed. A plurality of peripheral circuit transistors including at least one transistor having a structure different from that of the cell transistor are simultaneously formed in the peripheral circuit region as the cell transistor is formed.

The peripheral circuit transistor may include a high voltage transistor and a low voltage transistor.

A method of manufacturing a semiconductor device according to the present invention includes forming a high voltage transistor having the same structure as the cell transistor in the peripheral circuit region at the same time as forming the cell transistor, and simultaneously forming the cell transistor in the peripheral circuit region at the same time as forming the cell transistor. The method may include forming a low voltage transistor having a second gate insulating layer having a smaller thickness than the first gate insulating layer of the transistor and a second channel region having a shorter length than the first channel region.

In the first exemplary embodiment for forming the cell transistor, the high voltage transistor, and the low voltage transistor, first, a stacked structure consisting of a first insulating film, a memory layer, and a second insulating film is formed in a cell array region and a peripheral circuit region on the semiconductor substrate. Form. The first gate insulating layer is formed in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region. The second gate insulating layer is formed in a region in which the low voltage transistor is to be formed in the peripheral circuit region. A gate of a cell transistor, a gate of a high voltage transistor, and a gate of a low voltage transistor are simultaneously formed in the cell array region and the peripheral circuit region, respectively. The remaining portion of the stacked structure is removed so that a portion of the stacked structure remains only between the semiconductor substrate and the gate of the cell transistor, the gate of the high voltage transistor, and the gate of the low voltage transistor. Ion implantation is performed to form an extension region defining the length of the second channel region. Ion implantation is performed in the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining the length of the first channel region. Source / drain regions are simultaneously formed in the cell array region and the peripheral circuit region, respectively.

In addition, the method of manufacturing a semiconductor device according to the present invention may include forming a high voltage transistor and a low voltage transistor having a different structure from the cell transistor in the peripheral circuit region at the same time as the cell transistor is formed. In this case, a low voltage having a second gate insulating film having a thickness smaller than that of the first gate insulating film of the cell transistor and a second channel region having a shorter length than the first channel region in the peripheral circuit region at the same time as the cell transistor is formed. Form a transistor.

In a second exemplary embodiment for forming the cell transistor, the high voltage transistor, and the low voltage transistor, a stacked structure composed of a first insulating film, a memory layer, and a second insulating film is formed in a cell array region and a peripheral circuit region on the semiconductor substrate, respectively. do. The first gate insulating layer is formed in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region. The second gate insulating layer is formed in a region in which the low voltage transistor is to be formed in the peripheral circuit region. A gate of a cell transistor, a gate of a high voltage transistor, and a gate of a low voltage transistor are simultaneously formed in the cell array region and the peripheral circuit region, respectively. The remaining portion of the stacked structure is removed so that a portion of the stacked structure remains only between the semiconductor substrate and the gate of the cell transistor, the gate of the high voltage transistor, and the gate of the low voltage transistor. Only the memory layer is selectively removed from a portion of the stacked structure remaining under the gate of the high voltage transistor and the gate of the low voltage transistor in the peripheral circuit region. Ion implantation is performed in the semiconductor substrate under the gate of the low voltage transistor to form an extension region defining the length of the second channel region. Ion implantation is performed in the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining the length of the first channel region. Source / drain regions are simultaneously formed in the cell array region and the peripheral circuit region, respectively.

Further, in the third exemplary embodiment for forming the cell transistor, the high voltage transistor, and the low voltage transistor, a laminated structure composed of a first insulating film, a memory layer, and a second insulating film, respectively, in a cell array region and a peripheral circuit region on the semiconductor substrate. To form. The first gate insulating layer is formed in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region. The second gate insulating layer is formed in a region in which the low voltage transistor is to be formed in the peripheral circuit region. A second conductive layer covering both sidewalls of the first conductive layer in a state in which a third insulating film is interposed between the first conductive layer formed on the first gate insulating film and the first conductive layer in the cell array region; The gate of the cell transistor is formed. A gate of a high voltage transistor including a third conductive layer formed on the first gate insulating layer and a fourth conductive layer in a spacer form covering both sidewalls of the third conductive layer is formed in the peripheral circuit region. A gate of a low voltage transistor including a fifth conductive layer formed on the second gate insulating layer and a sixth conductive layer in the form of a spacer covering both sidewalls of the fifth conductive layer is formed in the peripheral circuit region. A portion of the stacked structure is removed such that the memory layer remains only between the semiconductor substrate and the second conductive layer in the cell array region. Ion implantation is performed in the semiconductor substrate under the gate of the low voltage transistor to form an extension region defining the length of the second channel region. Ion implantation is performed in the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining the length of the first channel region. Source / drain regions are simultaneously formed in the cell array region and the peripheral circuit region, respectively.

In the fourth exemplary embodiment for forming the cell transistor, the high voltage transistor and the low voltage transistor, a stacked structure consisting of a first insulating film, a memory layer and a second insulating film is selectively formed only in the cell array region on the semiconductor substrate. The first gate insulating layer is formed in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region. The second gate insulating layer is formed in a region in which the low voltage transistor is to be formed in the peripheral circuit region. A second conductive layer covering both sidewalls of the first conductive layer in a state in which a third insulating film is interposed between the first conductive layer formed on the first gate insulating film and the first conductive layer in the cell array region; The gate of the cell transistor is formed. A gate of a high voltage transistor including a third conductive layer formed on the first gate insulating layer and a fourth conductive layer in a spacer form covering both sidewalls of the third conductive layer is formed in the peripheral circuit region. A gate of a low voltage transistor including a fifth conductive layer formed on the second gate insulating layer and a sixth conductive layer in the form of a spacer covering both sidewalls of the fifth conductive layer is formed in the peripheral circuit region. A portion of the stacked structure is removed such that the memory layer remains only between the semiconductor substrate and the second conductive layer in the cell array region. Ion implantation is performed in the semiconductor substrate under the gate of the low voltage transistor to form an extension region defining the length of the second channel region. Ion implantation is performed in the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining the length of the first channel region. Source / drain regions are simultaneously formed in the cell array region and the peripheral circuit region, respectively.

According to the present invention, a process of integrating a memory cell of a nonvolatile memory device into a peripheral circuit can be simplified, and the transistor of the peripheral circuit region manufactured at the same time as the cell transistor can be formed to have a notched gate structure. Leakage current can be reduced. In addition, the overlap capacitance between the source / drain and the gate can be reduced, thereby improving the performance of the memory device.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

 The following exemplary embodiments can be modified in many different forms, and the scope of the present invention is not limited to the following exemplary embodiments. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the accompanying drawings, the size or thickness of the films or regions is exaggerated for clarity.

1A to 1O are cross-sectional views illustrating a manufacturing method of a semiconductor device according to a first embodiment of the present invention in order of processing.

In the first embodiment, a case of process integration for simultaneously forming a cell transistor formed in the cell array region, and a high voltage transistor and a low voltage transistor formed in the peripheral circuit region will be described as an example. In the first embodiment, the cell transistor, the high voltage transistor, and the low voltage transistor are each formed to have a notched gate structure, and each transistor is formed to have a different gate insulating film thickness according to its function.

Referring first to FIG. 1A, a device isolation region 102 is formed on a semiconductor substrate 100, such as a silicon substrate, having a cell array region, a peripheral circuit and a core region (hereinafter, simply referred to as a " peripheral circuit region "). To form an active region of the semiconductor substrate 100. In this example, a cell transistor (CELL Tr.) Is formed in the cell array region of the semiconductor substrate 100 and a high voltage transistor (HV MOSFET) and a low voltage transistor (LV MOSFET) are formed in the peripheral circuit region.

Referring to FIG. 1B, a lower oxide film 112, a memory layer 114, and an upper oxide film 116 are sequentially formed on an entire surface of the semiconductor substrate 100. The lower oxide layer 112 may serve as a tunnel, and may be formed, for example, in a thickness of about 20 to about 100 μm. The memory layer 114 is a film formed for trapping charge carriers, and charges may be stored, such as silicon nitride, amorphous silicon, polycrystalline silicon, silicon dots, SiGe, nanocrystals, and metals. Any kind of material may be used. Preferably, the memory layer 114 is made of silicon nitride. The memory layer 114 may be formed to a thickness of, for example, about 50 to about 100 microseconds. The upper oxide layer 116 may be formed to have a thickness of, for example, about 50 to about 250 kPa.

Referring to FIG. 1C, a dummy pattern 120 is formed on the upper oxide layer 116. The dummy pattern 120 serves as a molding for forming a gate of a transistor by a damascene process in a subsequent process, and the opening 120h of the dummy pattern 120 has a gate formed on the semiconductor substrate 100. It corresponds to the position. Since the dummy pattern 120 is to be selectively removed after the gate is formed in a subsequent process, the dummy pattern 120 is preferably made of a material having an etching selectivity with the upper oxide layer 116, for example, silicon nitride. The thickness of the dummy pattern 120 is determined in consideration of the height of the gate to be formed.

Referring to FIG. 1D, the upper oxide layer 116, the memory layer 114 and the lower oxide layer 112 exposed through the opening 120h are removed using the dummy pattern 120 as an etch mask. An upper surface of the semiconductor substrate 100 is exposed through the opening 120h.

Referring to FIG. 1E, a relatively thick first insulating layer 132 is formed on the exposed upper surface of the semiconductor substrate 100 and the dummy pattern 120. The first insulating layer 132 constitutes a gate insulating film of a transistor in a cell array region and a high voltage transistor in a peripheral circuit region. For example, the first insulating layer 132 may be formed of a silicon oxide layer having a relatively large thickness of about 50 to 250 kV. Thereafter, using the first photoresist pattern 134 as an etching mask, the first insulating layer 132 may be selectively removed only by a dry etching method in a region where the low voltage transistor (LV MOSFET) is to be formed in a peripheral circuit region. The upper surface of the semiconductor substrate 100 is exposed again through the opening 120h in the region where the LV MOSFET is to be formed. As a result, the first insulating layer 132 remains in the form of a spacer only on sidewalls of the dummy pattern 120 in the LV MOSFET formation region. Subsequently, a second insulating layer 136 is formed on the semiconductor substrate 100 exposed through the opening 120h in the LV MOSFET formation region. The second insulating film 136 constitutes a gate insulating film of the LV MOSFET, and is formed to have a thickness thinner than that of the first insulating film 132. For example, the second insulating layer 136 may have a thickness selected within a range of about 20 to about 100 GPa. The second insulating layer 136 may be formed of, for example, a silicon oxide film by thermal oxidation.

Referring to FIG. 1F, the first photoresist pattern 134 is removed, and a first conductive layer 140 is deposited by depositing a conductive material for forming a gate inside the opening 120h and on the dummy pattern 120. After the formation, the first conductive layer 140 is polished by a chemical mechanical polishing (CMP) process so that the first conductive layer 140 remains only in the opening 120h. The first conductive layer 140 remaining in the opening 120h constitutes a gate of the transistor in the cell array region and the peripheral circuit region, respectively. The first conductive layer 140 may be formed of, for example, doped polysilicon, metal, or metal silicide. In order to protect the surface of the first conductive layer 140, an oxide film 142 is formed on the first conductive layer 140.

Referring to FIG. 1G, the oxide layer 142 on the dummy pattern 120 and the dummy pattern 120 are sequentially removed by a wet etching method to expose the upper oxide layer 116.

Referring to FIG. 1H, the exposed portions of the first insulating layer 132 and the upper oxide layer 116 are removed by a strip process, and then a third insulating layer 146 is formed. The third insulating layer 146 may be formed of, for example, an oxide film formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. As will be appreciated by those skilled in the art, the process of removing the exposed portions of the first insulating film 132 and the upper oxide film 116 described above, and forming the third insulating film 146. The process may be omitted in some cases. When these processes are omitted, the third insulating layer 146 shown on the upper surface of the first conductive layer 140 in FIG. 1H is not formed. In this example, the case where the third insulating film 146 is formed will be described.

The conductive material is deposited on the entire surface of the resultant material on which the third insulating film 146 is formed and etched back to form a spacer in the form of a spacer through the third insulating film 146 on the sidewall of the first conductive layer 140. 2 conductive layer 150 is left. The second conductive layer 150 may be formed of, for example, doped polysilicon, metal, or metal silicide.

By forming a gate including the first conductive layer 140 and the second conductive layer in the cell array region and the peripheral circuit region as described above, the second conductive material is separated from the semiconductor substrate 100 in the cell array region and the peripheral circuit region. A notched gate structure is obtained in which the separation distance to the layer 150 is larger than the separation distance from the semiconductor substrate 100 to the first conductive layer 140.

Referring to FIG. 1I, the semiconductor substrate may be removed by removing the third insulating layer 146 and the memory layer 114 and the lower oxide layer 112 below the second insulating layer 146 exposed around the spacer-shaped second conductive layer 150. The top surface of 100 is exposed.

Referring to FIG. 1J, the semiconductor substrate 100 covers the HV MOSFET formation region of the cell array region and the peripheral circuit region with the second photoresist pattern 162 so that the LV MOSFET formation region of the peripheral circuit region is exposed. At least one of the second photoresist pattern 162, the first conductive layer 140, and the second conductive layer 150 as an ion implantation mask may be used to inject lightly doped drain (LDD) ion into the semiconductor substrate 100. An ion implantation is performed to form the extension region 164 in the semiconductor substrate 100 in the region where the LV MOSFET is to be formed. The ion implantation process may be performed by a gradient ion implantation process so that the extension region 164 may extend to the lower region of the memory layer 114. By forming the extension region 164 as described above, a channel region having a relatively short length is defined by the extension region 164 in the region where the LV MOSFET is to be formed.

Referring to FIG. 1K, after the second photoresist pattern 162 is removed, the peripheral circuit region is exposed so that the transistor formation region of the cell array region and the HV MOSFET formation region of the peripheral circuit region are exposed in the semiconductor substrate 100. The third photoresist pattern 166, the first conductive layer 140, and the second conductive layer 150 are formed as ion implantation masks while the LV MOSFET formation region is covered with the third photoresist pattern 166. LDD ion implantation and halo ion implantation are performed on the semiconductor substrate 100 to form an extension region 168 in an HV MOSFET formation region of the cell array region and the peripheral circuit region. In this step, unlike the ion implantation process in FIG. 1J, the inclination ion implantation process is not performed, and thus, the extension region (i.e. The length of the channel region defined by 168 becomes relatively long, so that the channel region defined by the extension region 164 in the region where the LV MOSFET is to be formed is larger than the length of the channel region defined by the extension region 168. The length becomes shorter.

Referring to FIG. 1L, after removing the third photoresist pattern 166, an insulating material is deposited on the entire surface of the resultant and then etched back to form an insulating spacer 170 on sidewalls of the second conductive layer 150. do. The insulating spacer 170 may be formed of an oxide film, a nitride film, or a combination thereof. When the third insulating film 146 is formed of an oxide film, the insulating spacer 170 may be formed of a nitride film to secure an etching selectivity with the third insulating film 146.

Referring to FIG. 1M, the semiconductor substrate 100 may be ion implanted using the first conductive layer 140, the second conductive layer 150, and the insulating spacer 170 as an ion implantation mask. Source / drain regions 172 are simultaneously formed in the cell array region and the peripheral circuit region of 100.

Referring to FIG. 1N, a portion of the third insulating layer 146 exposed on the first conductive layer 140 is etched using a wet or dry etching process to etch the first conductive layer 140 and the first layer. The recess region 174 is formed between the two conductive layers 150.

Referring to FIG. 1O, a metal silicide layer 180 is formed on the first conductive layer 140, the second conductive layer 150, and the source / drain regions 172 using a conventional salicide process. do. The first conductive layer 140 and the second conductive layer 150 may be electrically connected to each other by the metal silicide layer 180. The metal silicide layer 180 may be formed of, for example, cobalt silicide, nickel silicide, or titanium silicide.

According to the method of manufacturing the semiconductor device according to the first embodiment of the present invention described above, the cell transistor formed in the cell array region and the HV MOSFET formed in the peripheral circuit region are gated with the first insulating film 132 having a relatively large thickness. By forming the insulating film, a gate insulating film having a relatively large thickness can be formed, and the LV MOSFET formed in the peripheral circuit region forms a gate insulating film with the second insulating film 136 formed with a relatively small thickness to form a gate insulating film having a relatively small thickness. can do. Also, in the peripheral circuit region, the extension region 168 of the cell transistor and the extension region 168 of the HV MOSFET are formed so as to be located outside the memory layer 114 with respect to the transistor channel region. The extension region 164 is formed below the memory layer 114 at both sides of the transistor channel region. Thus, high performance transistors can be implemented in LV MOSFETs operating at low operating voltages. As described above, in the method of manufacturing the semiconductor device according to the first exemplary embodiment of the present invention, transistors having different structures according to the functions of the transistors in the cell array region and the peripheral circuit region can be easily implemented by efficient process integration.

2A through 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, according to a process sequence.

In the second embodiment, a case of process integration for simultaneously forming a cell transistor formed in a cell array region, and a high voltage transistor and a low voltage transistor formed in a peripheral circuit region will be described as an example. In the second embodiment, the cell transistor, the high voltage transistor, and the low voltage transistor are each formed to have a notched gate structure, and each transistor is formed to have a different gate insulating film thickness according to its function. The second embodiment is generally the same as the first embodiment, but one of the features distinguished from the first embodiment in the second embodiment includes a process of completely removing the memory layer from the transistor in the peripheral circuit region. In the second embodiment of the present invention described with reference to Figs. 2A to 2H, the same reference numerals as those in the first embodiment denote the same members, and detailed description thereof will be omitted here in order to avoid duplication of description. .

Referring to FIG. 2A, the process as described with reference to FIGS. 1A to 1I may be performed in the same manner as in the first embodiment, and the second conductive layer may be formed in the cell array region and the peripheral circuit region on the semiconductor substrate 100, respectively. A portion of the memory layer 116 is exposed below the layer 150.

Thereafter, in order to protect the memory layer 116 in the cell array region, a wet etching process is performed on the memory layer 114 formed in the peripheral circuit region while the cell array region is covered with the fourth photoresist pattern 204. Remove by For example, when the memory layer 114 is formed of a silicon nitride film, phosphoric acid (H ₃ PO ₄ ) may be used as a wet etchant.

Referring to FIG. 2B, after the fourth photoresist pattern 204 is removed, the remaining space after the memory layer 114 is removed from the peripheral circuit region may be entirely filled in the cell array region and the peripheral circuit region. An insulating material is deposited and etched back to form an insulating liner 210 on the sidewall of the second conductive layer 150. The insulating liner 210 is preferably composed of an oxide film.

Referring to FIG. 2C, the LDD ion implantation and the halo ion implantation are performed in the LV MOSFET formation region of the peripheral circuit region by the method described with reference to FIG. 164).

Referring to FIG. 2D, LDD ion implantation and halo ion implantation are performed in a transistor formation plan region of a cell array region and an HV MOSFET formation region of a peripheral circuit region by a method as described with reference to FIG. The extension region 168 is formed in the HV MOSFET formation scheduled region of the circuit region.

Referring to FIG. 2E, an insulating spacer 170 is formed on sidewalls of the insulating liner 210 in the same manner as described with reference to FIG. 1L.

Referring to FIG. 2F, the source / drain regions 172 are simultaneously formed in the cell array region and the peripheral circuit region of the semiconductor substrate 100 by the method described with reference to FIG. 1M.

Referring to FIG. 2G, a portion of the third insulating layer 146 is etched by the method described with reference to FIG. 1N to recess between the first conductive layer 140 and the second conductive layer 150. Area 174 is formed.

Referring to FIG. 2H, a metal silicide layer 180 is formed on the first conductive layer 140, the second conductive layer 150, and the source / drain region 172 in the same manner as described with reference to FIG. 1O. .

According to the semiconductor device manufacturing method according to the second embodiment of the present invention described above, the cell transistor formed in the cell array region and the HV MOSFET formed in the peripheral circuit region, as in the first embodiment, are formed with a relatively large thickness. By forming the gate insulating film with the first insulating film 132, a gate insulating film having a relatively large thickness can be formed, and the LV MOSFET formed in the peripheral circuit region is formed by forming the gate insulating film with the second insulating film 136 having a relatively small thickness. A gate insulating film of a small thickness can be formed. In addition, the extension region 168 of the cell transistor is formed outside the memory layer 114 around the channel region, and the extension region 164 of the LV MOSFET in the peripheral circuit region is formed of the cell transistor and the HV MOSFET. Compared with the case, the transistor channel length is short because the mutual separation distance is short. Thus, high performance transistors can be implemented in LV MOSFETs operating at low operating voltages. As described above, in the method of manufacturing a semiconductor device according to the second exemplary embodiment of the present invention, transistors having different structures according to the function of each transistor in the cell array region and the peripheral circuit region can be easily implemented by efficient process integration.

In addition, according to the method of manufacturing the semiconductor device according to the second embodiment of the present invention, in the cell array region, the memory layer 114 remains under the second conductive layer 150 constituting the transistor, whereas in the peripheral circuit region The memory layer 114 is removed below the second conductive layer 150 in the HV MOSFET and the LV MOSFET. When the memory layer 114 remains in the HV MOSFET, the charge is stored in the memory layer 114 through the Fowler-Nordheim (FN) or the Channel Hot-electron Injection (CHEI) method during the operation of the HV MOSFET. Cases may occur. This may result in disturbing the electrical circuit operation by changing the Vth of the peripheral circuit, and may degrade the distribution of the electrical performance of the device. According to the second exemplary embodiment of the present invention, since the memory layer 114 is removed from the peripheral circuit region, the possibility of the aforementioned problem may be eliminated.

3A to 3K are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention, according to a process sequence.

In the third embodiment, a case of process integration for simultaneously forming a cell transistor formed in the cell array region, and a high voltage transistor and a low voltage transistor formed in the peripheral circuit region will be described as an example. In the third embodiment, the cell transistor, the high voltage transistor, and the low voltage transistor are each formed to have a notched gate structure, and each transistor is formed to have a different gate insulating film thickness according to its function. The third embodiment includes a process of completely removing the memory layer from the transistor in the peripheral circuit region as in the second embodiment. One of the features distinguished from the second embodiment in the third embodiment is to remove the insulating film interposed between the first conductive layer 140 and the second conductive layer 150 in the peripheral circuit region. In the third embodiment of the present invention described with reference to Figs. 3A to 3K, the same reference numerals as those in the first and second embodiments denote the same members, and detailed descriptions thereof will be given herein in order to avoid duplication of description. Description is omitted.

Referring to FIG. 3A, the process described above with reference to FIGS. 1A through 1G may be performed in the same manner as in the first embodiment, and the dummy pattern may be exposed to expose the upper oxide layer 116 on the semiconductor substrate 100. 120).

Thereafter, the third insulating layer 146 covering the sidewall of the first conductive layer 140 in the peripheral circuit region is removed using the fifth photoresist pattern 302 covering the cell array region as an etching mask.

Referring to FIG. 3B, after removing the fifth photoresist pattern 302, the second conductive layer 150 in the form of a spacer is formed on the sidewall of the first conductive layer 140 in the same manner as described with reference to FIG. 1H. To form. As a result, in the cell array region, the second conductive layer 150 is a sidewall of the first conductive layer 140 with the third insulating layer 146 interposed between the first conductive layer 140. In the peripheral circuit region, the second conductive layer 150 is formed to directly contact the sidewall of the first conductive layer 140.

Referring to FIG. 3C, the third insulating layer 146 and the memory layer 114 exposed below the second conductive layer 150 in the form of a spacer and the lower portion below the spacers may be exposed in the same manner as described with reference to FIG. 1I. The oxide film 112 is removed to expose the top surface of the semiconductor substrate 100.

Referring to FIG. 3D, the memory layer 114 formed in the peripheral circuit region is removed by a wet etching process in the same manner as described with reference to FIG. 2A.

Referring to FIG. 3E, an insulating liner 210 is formed on sidewalls of the second conductive layer 150 in the same manner as described with reference to FIG. 2B.

Referring to FIG. 3F, LDD ion implantation and halo ion implantation are performed in the LV MOSFET formation region of the peripheral circuit region in the same manner as described with reference to FIG. 164).

Referring to FIG. 3G, LDD ion implantation and halo ion implantation are performed in the transistor formation region of the cell array region and the HV MOSFET formation region of the peripheral circuit region by the method described with reference to FIG. The extension region 168 is formed in the HV MOSFET formation scheduled region of the circuit region.

Referring to FIG. 3H, an insulating spacer 170 is formed on sidewalls of the insulating liner 210 in the same manner as described with reference to FIG. 2E.

Referring to FIG. 3I, the source / drain regions 172 are simultaneously formed in the cell array region and the peripheral circuit region of the semiconductor substrate 100 in the same manner as described with reference to FIG. 2F.

Referring to FIG. 3J, a portion of the third insulating layer 146 is etched in the cell array region in the same manner as described with reference to FIG. 2G to etch the first conductive layer 140 and the second conductive layer ( A recessed region 174 is formed between 150 and 150.

Referring to FIG. 3K, the metal silicide layer 180 is formed on the first conductive layer 140, the second conductive layer 150, and the source / drain region 172 in the same manner as described with reference to FIG. 2H. . As a result, in the cell array region, the first conductive layer 140 and the second conductive layer 150 may be electrically connected to each other by the metal silicide layer 180.

According to the method for manufacturing a semiconductor device according to the third embodiment of the present invention described above, cell transistors formed in the cell array region and HV MOSFETs formed in the peripheral circuit region are relatively similar to those of the first and second embodiments. A gate insulating film having a relatively large thickness can be formed by forming a gate insulating film with the first insulating film 132 having a large thickness, and the LV MOSFET formed in the peripheral circuit region is gated with a second insulating film 136 having a relatively small thickness. By forming the insulating film, a gate insulating film having a relatively small thickness can be formed. In addition, the extension region 168 of the cell transistor is formed outside the memory layer 114 around the channel region, and the extension region 164 of the LV MOSFET in the peripheral circuit region is formed of the cell transistor and the HV MOSFET. Compared with the case, the transistor channel length is short because the mutual separation distance is short. Thus, high performance transistors can be implemented in LV MOSFETs operating at low operating voltages. As described above, in the method of manufacturing the semiconductor device according to the third exemplary embodiment of the present invention, transistors having different structures according to the functions of the transistors in the cell array region and the peripheral circuit region can be easily implemented by efficient process integration. According to the method of manufacturing the semiconductor device according to the third embodiment of the present invention, the memory layer 114 remains under the second conductive layer 150 constituting the transistor in the cell array region as in the case of the second embodiment. In the peripheral circuit region, the memory layer 114 is removed under the second conductive layer 150 in the HV MOSFET and the LV MOSFET. Therefore, the possibility of the electrical performance deterioration of a peripheral circuit can be eliminated.

In particular, in the third embodiment of the present invention, unnecessary insulating layers are removed between the first conductive layer 140 and the second conductive layer 150 by fully utilizing the characteristics of the peripheral circuit element that does not require a storage node. Accordingly, in the third embodiment of the present invention, the process of forming the metal silicide layer 180 as described with reference to FIG. 3K may be omitted in the peripheral circuit region.

4A through 4N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention, according to a process sequence.

In the fourth embodiment, a case of process integration for simultaneously forming a cell transistor formed in the cell array region, and a high voltage transistor and a low voltage transistor formed in the peripheral circuit region will be described as an example. In the fourth embodiment, the cell transistor is formed to have a notched gate structure, and the cell transistor, the high voltage transistor, and the low voltage transistor are each formed to have different gate insulating film thicknesses according to their function. The fourth embodiment includes similar process steps as in the first embodiment. One of the features distinguished from the first embodiment in the fourth embodiment is a process of completely removing the memory layer from the transistors in the peripheral circuit region as in the second and third embodiments. However, the second and third embodiments differ in that the process of removing the memory layer of the transistor in the peripheral circuit region is performed before forming the gate forming conductive layer. In the fourth embodiment of the present invention described with reference to Figs. 4A to 4N, the same reference numerals as those in the first embodiment denote the same members, and detailed description thereof is omitted here to avoid duplication of description. .

Referring to FIG. 4A, a stack in which a lower oxide film 112, a memory layer 114, and an upper oxide film 116 are sequentially formed on a semiconductor substrate 100 is formed in the same manner as described with reference to FIGS. 1A and 1B. Proceed to the process.

Thereafter, the cell array region on the semiconductor substrate 100 is covered with a first mask pattern 402, for example, a photoresist pattern, and the first mask pattern 402 is used as an etch mask in the peripheral circuit region. The stack in which the lower oxide film 112, the memory layer 114, and the upper oxide film 116 are sequentially formed is removed. Subsequently, a fourth insulating layer 418 is formed on the surface of the semiconductor substrate 100 in the peripheral circuit region. The fourth insulating layer 418 may be formed of, for example, an oxide film formed by a thermal oxidation method.

Referring to FIG. 4B, after removing the first mask pattern 402, a dummy pattern 120 is formed on the upper oxide layer 116 and the fourth insulating layer 418 by the method described with reference to FIG. 1C. .

Referring to FIG. 4C, using the dummy pattern 120 as an etch mask, in the cell array region, the upper oxide layer 116 and the lower memory layer 114 and the lower oxide layer (exposed through the opening 120h) are exposed. 112 is removed, and in the peripheral circuit region, the fourth insulating layer 418 exposed through the opening 120h is removed to expose the top surface of the semiconductor substrate 100 through the opening 120h.

Referring to FIG. 4D, a relatively thick first insulating layer 132 is formed on the dummy pattern 120 in the same manner as described with reference to FIG. 1E, and the peripheral circuit is formed by using the second mask pattern 404 as an etching mask. The first insulating layer 132 is selectively etched only in the region in which the LV MOSFET is to be formed. At this time, the first insulating film 132 does not remain at all in the region where the LV MOSFET is to be formed and can be completely removed. To this end, in the case of using the dry etching process as shown in FIG. 1E, the etching time is set longer than that in FIG. 1E so that the first insulating layer 132 can be completely removed from the LV MOSFET region. As another method, even when a wet etching process using the second mask pattern 404 as an etching mask is used, the first insulating layer 132 may be completely removed from the LV MOSFET region. As a result, the inner wall of the opening 120h of the dummy pattern 120 is completely exposed in the LV MOSFET region.

Referring to FIG. 4E, after removing the second mask pattern 404, the first conductive layer 140 and the oxide layer 142 are formed in the same manner as described with reference to FIG. 1F.

Referring to FIG. 4F, the dummy pattern 120 is removed in the same manner as described with reference to FIG. 1G to expose the upper oxide layer 116 and the fourth insulating layer 418.

Referring to FIG. 4G, a second conductive layer 150 in the form of a spacer is formed on the sidewall of the first conductive layer 140 in the same manner as described with reference to FIG. 1H. As a result, the first insulating layer 132 is interposed between the first conductive layer 140 and the second conductive layer 150 in the HV MOSFET region of the cell array region and the peripheral circuit region, while in the peripheral circuit region. In the LV MOSFET region, an insulating film is not interposed between the first conductive layer 140 and the second conductive layer 150, and the second conductive layer 150 is directly in contact with the sidewall of the first conductive layer 140. .

Referring to FIG. 4H, in the cell array region, the upper oxide layer 116 and the memory layer 114 and the lower oxide layer 112 that are exposed around the spacer-shaped second conductive layer 150 are removed. The upper surface of the semiconductor substrate 100 is exposed, and in the peripheral circuit region, the fourth insulating layer 418 exposed around the second conductive layer 150 is removed to expose the upper surface of the semiconductor substrate 100. .

Referring to FIG. 4I, an extension region 164 is formed in an LV MOSFET formation region of a peripheral circuit region of the semiconductor substrate 100 in the same manner as described with reference to FIG. 1J.

Referring to FIG. 4J, the extension region 168 is formed in the semiconductor substrate 100 in the transistor formation region of the cell array region and the HV MOSFET formation region of the peripheral circuit region in the semiconductor substrate 100 in the same manner as described with reference to FIG. 1K. .

Referring to FIG. 4K, an insulating spacer 170 is formed on sidewalls of the second conductive layer 150 in the same manner as described with reference to FIG. 1L.

Referring to FIG. 4L, the source / drain regions 172 are simultaneously formed in the cell array region and the peripheral circuit region of the semiconductor substrate 100 by the method described with reference to FIG. 1M.

Referring to FIG. 4M, a recess region 174 is formed between the first conductive layer 140 and the second conductive layer 150 in the same manner as described with reference to FIG. 1N.

Referring to FIG. 4N, the metal silicide layer 180 is formed on the first conductive layer 140, the second conductive layer 150, and the source / drain region 172 in the same manner as described with reference to FIG. 1O. .

According to the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention described above, only the cell transistors and the HV MOSFETs have a structure in which an electrode composed of the second conductive layer 150 in the form of a spacer is applied to the gate. In the LV MOSFET, a structure in which no electrode in the form of a spacer is applied is obtained. In addition, the memory layer 114, which is a storage node necessary only in the cell array region, is selectively removed in the other regions except the cell array region before the gate structure is formed, thereby implementing a 2-bit NVM transistor in the cell array region, thereby providing a peripheral circuit. In the region, since the memory layer 114 is removed under the second conductive layer 150 in the HV MOSFET and the LV MOSFET, the possibility of deterioration of electrical performance of the peripheral circuit may be eliminated.

In the first to fourth embodiments of the present invention described above, only the case of using a bulk semiconductor substrate has been described. However, those skilled in the art will appreciate that the process integration according to the present invention is not only a bulk semiconductor substrate. It will be appreciated that it can be implemented using any semiconductor substrate, including silicon on insulator (SOI).

In the method of fabricating a semiconductor device according to the present invention, a cell transistor formed in a cell array region adopts a structure capable of multi-bit operation using localized bits while applying a spacer electrode to a gate, and in a peripheral circuit region. It is possible to form a transistor having a structure that is optimized to meet the different requirements required by the function of the transistor, and the transistors in the cell array area and the transistors in the peripheral circuit area that are designed separately according to their unique functions can be easily By simultaneously manufacturing by the manufacturing process, it is possible to efficiently achieve process integration of a cell transistor capable of multi-bit operation using localized bits.

According to the method of manufacturing a semiconductor device according to the present invention, a process step can be simplified as compared with integrating a memory cell of a conventional nonvolatile memory device into a peripheral circuit, and the transistor in the peripheral circuit region manufactured simultaneously with the cell transistor is notched. Since it can be formed to have a gate structure it can reduce the leakage current at the gate. In addition, it is possible to reduce the overlap capacitance between the source / drain and the gate, thereby improving the performance of the memory device.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

Claims (25)

Preparing a semiconductor substrate having a cell array region and a peripheral circuit region; A notch gate structure in the cell array region of the semiconductor substrate, a first channel region formed in the semiconductor substrate under the notch gate structure, a source / drain region formed on both sides of the first channel region, and the first channel region interposed therebetween A first gate insulating layer formed between the channel region and the notched gate structure, and a memory layer locally formed in an area adjacent to the source / drain region between the first channel region and the notched gate structure. Forming a cell transistor, And forming a plurality of peripheral circuit transistors including at least one transistor having a structure different from the cell transistor in the peripheral circuit region at the same time as the cell transistor formation. The method of claim 1, The peripheral circuit transistor includes a high voltage transistor and a low voltage transistor manufacturing method of a semiconductor device. The method of claim 2, Forming a high voltage transistor having the same structure as that of the cell transistor in the peripheral circuit region simultaneously with forming the cell transistor; Forming a low voltage transistor having a second gate insulating layer having a smaller thickness than the first gate insulating layer of the cell transistor and a second channel region having a shorter length than the first channel region in the peripheral circuit region at the same time as the cell transistor is formed. Method for manufacturing a semiconductor device comprising the step of. The method of claim 3, Forming a stacked structure including a first insulating film, a memory layer, and a second insulating film in a cell array region and a peripheral circuit region on the semiconductor substrate, respectively; Forming the first gate insulating layer in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region; Forming the second gate insulating layer in the low voltage transistor formation region of the peripheral circuit region; Simultaneously forming a gate of a cell transistor, a gate of a high voltage transistor, and a gate of a low voltage transistor in the cell array region and the peripheral circuit region, respectively; Removing the remaining part of the stacked structure such that a portion of the stacked structure remains only between each of the semiconductor substrate and the gate of the cell transistor, the gate of a high voltage transistor, and the gate of a low voltage transistor; Performing an ion implantation into the semiconductor substrate under the gate of the low voltage transistor to form an extension region defining a length of the second channel region; Performing ion implantation into the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining a length of the first channel region; And simultaneously forming source / drain regions in the cell array region and the peripheral circuit region, respectively. The method of claim 4, wherein The forming of the gate of the cell transistor, the gate of the high voltage transistor, and the gate of the low voltage transistor may include forming a first conductive layer on the first gate insulating film and the second gate insulating film, respectively; Forming a spaced second conductive layer covering both sidewalls of the first conductive layer with a third insulating film interposed therebetween; The separation distance from the semiconductor substrate to the second conductive layer is greater than the separation distance from the semiconductor substrate to the first conductive layer. The method of claim 2, Forming a high voltage transistor and a low voltage transistor having a different structure from the cell transistor in the peripheral circuit region at the same time as the cell transistor is formed, Forming a low voltage transistor having a second gate insulating layer having a smaller thickness than the first gate insulating layer of the cell transistor and a second channel region having a shorter length than the first channel region in the peripheral circuit region at the same time as the cell transistor is formed. Method for manufacturing a semiconductor device comprising the step of. The method of claim 6, Forming a stacked structure including a first insulating film, a memory layer, and a second insulating film in a cell array region and a peripheral circuit region on the semiconductor substrate, respectively; Forming the first gate insulating layer in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region; Forming the second gate insulating layer in the low voltage transistor formation region of the peripheral circuit region; Simultaneously forming a gate of a cell transistor, a gate of a high voltage transistor, and a gate of a low voltage transistor in the cell array region and the peripheral circuit region, respectively; Removing the remaining part of the stacked structure such that a portion of the stacked structure remains only between each of the semiconductor substrate and the gate of the cell transistor, the gate of a high voltage transistor, and the gate of a low voltage transistor; Selectively removing only the memory layer of a portion of the stacked structure remaining under the gate of the high voltage transistor and the gate of a low voltage transistor in the peripheral circuit region; Implanting ions into the semiconductor substrate under the gate of the low voltage transistor to form an extension region defining a length of the second channel region; Performing ion implantation into the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining a length of the first channel region; And simultaneously forming source / drain regions in the cell array region and the peripheral circuit region, respectively. The method of claim 7, wherein The forming of the gate of the cell transistor, the gate of the high voltage transistor, and the gate of the low voltage transistor may include forming a first conductive layer on the first gate insulating film and the second gate insulating film, respectively; Forming a spaced second conductive layer covering both sidewalls of the first conductive layer with a third insulating film interposed therebetween; The separation distance from the semiconductor substrate to the second conductive layer is greater than the separation distance from the semiconductor substrate to the first conductive layer. The method of claim 7, wherein And selectively removing only the memory layer of a part of the stacked structure in the peripheral circuit area, and then filling a region where the removed memory layer was with an insulating liner. The method of claim 6, Forming a stacked structure including a first insulating film, a memory layer, and a second insulating film in a cell array region and a peripheral circuit region on the semiconductor substrate, respectively; Forming the first gate insulating layer in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region; Forming the second gate insulating layer in the low voltage transistor formation region of the peripheral circuit region; A second conductive layer covering both sidewalls of the first conductive layer in a state in which a third insulating film is interposed between the first conductive layer formed on the first gate insulating film and the first conductive layer in the cell array region; Forming a gate of a cell transistor consisting of: Forming a gate of a high voltage transistor including a third conductive layer formed over the first gate insulating layer and a fourth conductive layer in a spacer form covering both sidewalls of the third conductive layer in the peripheral circuit region; Forming a gate of a low voltage transistor comprising a fifth conductive layer formed on the second gate insulating layer and a sixth conductive layer in a spacer form covering both sidewalls of the fifth conductive layer in the peripheral circuit region; Removing a portion of the stacked structure such that the memory layer remains only between the semiconductor substrate and the second conductive layer in the cell array region; Implanting ions into the semiconductor substrate under the gate of the low voltage transistor to form an extension region defining a length of the second channel region; Performing ion implantation into the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining a length of the first channel region; And simultaneously forming source / drain regions in the cell array region and the peripheral circuit region, respectively. The method of claim 10, And the gate of the cell transistor, the gate of the high voltage transistor, and the gate of the low voltage transistor are simultaneously formed. The method of claim 10, The separation distance from the semiconductor substrate to the second conductive layer is greater than the separation distance from the semiconductor substrate to the first conductive layer,  The separation distance from the semiconductor substrate to the fourth conductive layer is greater than the separation distance from the semiconductor substrate to the third conductive layer,  The separation distance from the semiconductor substrate to the sixth conductive layer is greater than the separation distance from the semiconductor substrate to the fifth conductive layer. The method of claim 10, Selectively removing only the memory layer of the stacked structure in the peripheral circuit area; And filling the region where the removed memory layer was in the peripheral circuit region with an insulating liner. The method of claim 10, And the fourth conductive layer in the gate of the high voltage transistor is formed in direct contact with both sidewalls of the third conductive layer. The method of claim 10, And a fourth insulating film interposed between both sidewalls of the third conductive layer and the fourth conductive layer in the gate of the high voltage transistor. The method of claim 10, And the sixth conductive layer in the gate of the low voltage transistor is formed in direct contact with both sidewalls of the fifth conductive layer. The method of claim 10, And a fourth insulating film interposed between both sidewalls of the fifth conductive layer and the sixth conductive layer in the gate of the low voltage transistor. The method of claim 6, Forming a stacked structure consisting of a first insulating film, a memory layer, and a second insulating film selectively only in the cell array region on the semiconductor substrate; Forming the first gate insulating layer in the high voltage transistor formation region of the cell transistor formation region and the peripheral circuit region; Forming the second gate insulating layer in the low voltage transistor formation region of the peripheral circuit region; A second conductive layer covering both sidewalls of the first conductive layer in a state in which a third insulating film is interposed between the first conductive layer formed on the first gate insulating film and the first conductive layer in the cell array region; Forming a gate of a cell transistor consisting of: Forming a gate of a high voltage transistor including a third conductive layer formed over the first gate insulating layer and a fourth conductive layer in a spacer form covering both sidewalls of the third conductive layer in the peripheral circuit region; Forming a gate of a low voltage transistor comprising a fifth conductive layer formed on the second gate insulating layer and a sixth conductive layer in a spacer form covering both sidewalls of the fifth conductive layer in the peripheral circuit region; Removing a portion of the stack structure such that the memory layer remains only between the semiconductor substrate and the second conductive layer in the cell array region; Implanting ions into the semiconductor substrate under the gate of the low voltage transistor to form an extension region defining a length of the second channel region; Performing ion implantation into the gate of the cell transistor and the semiconductor substrate under the high voltage transistor to form an extension region defining a length of the first channel region; And simultaneously forming source / drain regions in the cell array region and the peripheral circuit region, respectively. The method of claim 18, And the gate of the cell transistor, the gate of the high voltage transistor, and the gate of the low voltage transistor are simultaneously formed. The method of claim 18, The separation distance from the semiconductor substrate to the second conductive layer is greater than the separation distance from the semiconductor substrate to the first conductive layer,  The separation distance from the semiconductor substrate to the fourth conductive layer is greater than the separation distance from the semiconductor substrate to the third conductive layer,  The separation distance from the semiconductor substrate to the sixth conductive layer is greater than the separation distance from the semiconductor substrate to the fifth conductive layer. The method of claim 18, Selectively removing only the memory layer of the stacked structure in the peripheral circuit area; And filling the region where the removed memory layer was in the peripheral circuit region with an insulating liner. The method of claim 18, And the fourth conductive layer in the gate of the high voltage transistor is formed in direct contact with both sidewalls of the third conductive layer. The method of claim 18, And a fourth insulating film interposed between both sidewalls of the third conductive layer and the fourth conductive layer in the gate of the high voltage transistor. The method of claim 18, And the sixth conductive layer in the gate of the low voltage transistor is formed in direct contact with both sidewalls of the fifth conductive layer. The method of claim 18, And a fourth insulating film interposed between both sidewalls of the fifth conductive layer and the sixth conductive layer in the gate of the low voltage transistor.

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