KR100588677B1 - Method for exposing wafer for energy uniformity manufacturing a semiconductor device - Google Patents

Method for exposing wafer for energy uniformity manufacturing a semiconductor device Download PDF

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KR100588677B1
KR100588677B1 KR1020030101131A KR20030101131A KR100588677B1 KR 100588677 B1 KR100588677 B1 KR 100588677B1 KR 1020030101131 A KR1020030101131 A KR 1020030101131A KR 20030101131 A KR20030101131 A KR 20030101131A KR 100588677 B1 KR100588677 B1 KR 100588677B1
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wafer
energy
semiconductor device
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manufacturing
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KR1020030101131A
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KR20050069177A (en
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이계훈
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동부일렉트로닉스 주식회사
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Abstract

본 발명은 리소그라피 공정에서 노광시 웨이퍼 영역별로 다른 에너지를 줌으로서 단차나 균일성이 떨어진 영역에 적정한 에너지를 가하여 패턴크기를 조절할 수 있는 노광 방법에 관한 것이다. 즉, 본 발명은 리소그라피의 패터닝 에너지를 영역별로 다르게 조절하여 웨이퍼 전면이 균일한 전기적 특성을 가지도록 함으로서, 소자의 수율을 높일 수 있으며, 또한 비메모리를 제조하는 공장에서는 다양한 소자에 따른 웨이퍼내의 전기적 특성차이를 소자마다 각각 다른 에너지로 조절하는 레서피로 만들 수 있고 공정지수를 관리하기 편하며, 전기적 특성 데이터를 피드백할 수 있게 하여 지속적으로 균일한 특성을 갖는 소자의 생산을 가능하도록 한다.The present invention relates to an exposure method that can adjust the pattern size by applying an appropriate energy to a region having a step difference or uniformity by giving different energy for each wafer region during exposure in a lithography process. That is, according to the present invention, the patterning energy of the lithography is adjusted differently for each region so that the front surface of the wafer has uniform electrical characteristics, thereby increasing the yield of the device, and in the non-memory manufacturing factory, the electrical power in the wafer according to various devices is increased. It is possible to make the characteristic difference into a recipe that controls each element with different energy, to manage the process index, and to feed back the electrical characteristic data so that it is possible to produce a device with consistently uniform characteristics.

Description

반도체 소자 제조시 에너지 균일화를 위한 노광방법{METHOD FOR EXPOSING WAFER FOR ENERGY UNIFORMITY MANUFACTURING A SEMICONDUCTOR DEVICE}TECHNICAL FOR EXPOSING WAFER FOR ENERGY UNIFORMITY MANUFACTURING A SEMICONDUCTOR DEVICE

도 1은 종래 에너지 균일화가 이루어지지 않은 웨이퍼 상 단차 예시도,1 is an exemplary view of a step on a wafer in which conventional energy uniformity is not achieved;

도 2는 종래 웨이퍼의 영역별 STI 깊이, PMD 증착 두께, 게이트 선폭차이 예시도표,Figure 2 is an exemplary diagram of the STI depth, PMD deposition thickness, gate line width difference for each region of the conventional wafer,

도 3은 종래 게이트에 흐르는 드라이브 전류의 분포도,3 is a distribution diagram of a drive current flowing through a conventional gate;

도 4는 본 발명의 실시 예에 따른 에너지 균일화가 구현된 반도체 소자 게이트에 흐르는 드라이브 전류의 분포도.4 is a distribution diagram of a drive current flowing in a semiconductor device gate in which energy uniformization is implemented according to an embodiment of the present invention.

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 리소그라피(Lithography) 공정에서 노광(Exposure)시 웨이퍼 영역별로 다른 에너지를 줌으로서 단차나 균일성이 떨어진 영역에 적정한 에너지를 가하여 패턴크기를 조절할 수 있는 노광 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and in particular, to expose a different energy for each wafer region during exposure in a lithography process, thereby exposing an appropriate energy to a region having a step difference or uniformity to adjust a pattern size. It is about a method.

현재의 반도체 소자 제조에 있어서는 적층 및 식각 공정을 한 후 중심영역과 가장자리 영역의 균일로 인한 소자의 수율(Yield)이 낮아지는 문제점을 가지고 있 다. 이때 가장자리의 단차가 높거나 낮은 경우 후 공정에 영향을 주어 레이어(Layer)가 올라갈수록 그 단차는 심해지게 되는데, 그 중에서도 게이트는 단차에 의한 게이트 선폭의 차이로 드라이브 전류(Drive current)에 막대한 영향을 주어 소자의 불량을 유발시키는 원인이 되어왔다.In the current semiconductor device manufacturing, the yield of the device due to the uniformity of the center region and the edge region after the lamination and etching process has a problem that is lowered. At this time, if the edge step height is high or low, it affects the post-process, and as the layer goes up, the step gets more severe. Among them, the gate has a huge influence on the drive current due to the difference in the gate line width due to the step difference. It has been a cause of device failure.

도 1은 종래의 적층된 소자의 단면도를 도시한 것으로, 중심부와 가장자리와의 게이트가 선폭의 차이를 나타냄으로서 가장자리의 소자가 불량이 나타난 것을 보여 주고 있으며, 게이트(Gate) 뿐만 아니라 메탈 콘텍(Metal contact), 메탈 비아(Metal via)도 마찬가지의 모습을 볼 수 있다.FIG. 1 is a cross-sectional view of a conventional stacked device, and shows that the device at the edge is defective because the gate between the center and the edge shows a difference in line width, and not only the gate but also the metal contact. The same can be seen for contacts and metal vias.

도 2는 웨이퍼 중심부와 가장자리의 STI(Shallow Trench Isolation) 깊이 및 PMD(Pre Metal Deposition) 증착 두께, 게이트 선폭의 차이를 도시한 것으로, 상기 도 2에서 보여지는 바와 같은 단차에 의해 중심부와 가장자리의 파라메틱 전류(Parametic current), 저항 등과 같은 전기적 특성이 불량하여 소자의 수율이 낮아지게되는 원인이 되어 왔다.FIG. 2 illustrates the difference between the shallow trench isolation (STI) depth, the pre-metal deposition (PMD) deposition thickness, and the gate line width of the wafer center and edges. Poor electrical characteristics such as parametric current, resistance, etc. have been a cause of low device yield.

또한 종래 반도체 소자의 전기적 특성 중 게이트에 흐르는 드라이브 전류(Drive current)의 분포를 나타낸 도 3에서 보여지는 바와 같이 가장자리로 갈수록 전류가 증가하여 소자불량을 유발시키는 문제점이 있었다.In addition, as shown in FIG. 3, which shows a distribution of drive current flowing through a gate among electrical characteristics of a conventional semiconductor device, current increases toward the edge, causing device defects.

따라서, 본 발명의 목적은 리소그라피 공정에서 노광시 웨이퍼 영역별로 다른 에너지를 줌으로서 단차나 균일성이 떨어진 영역에 적정한 에너지를 가하여 패턴크기를 조절할 수 있는 에너지 균일화 노광 방법을 제공함에 있다. Accordingly, an object of the present invention is to provide an energy uniform exposure method that can adjust a pattern size by applying appropriate energy to a region having a step difference or uniformity by giving different energy for each wafer region during exposure in a lithography process.                         

상술한 목적을 달성하기 위한 본 발명은 반도체 소자 제조시 에너지 균일화를 위한 노광방법으로서, (a)반도체 소자 제조를 위한 리소그라피 공정 시 웨이퍼상에 포토레지스트를 도포하는 단계와, (b)포토레지스트가 도포된 웨이퍼 영역별 파라메틱 전기적 특성값을 검사하는 단계와, (c)웨이퍼 전면이 균일한 전기적 특성을 갖도록 상기 웨이퍼 영역별로 전기적 특성값에 대응된 빛에너지로 노광을 진행시키는 단계,를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is an exposure method for energy uniformity in manufacturing a semiconductor device, (a) applying a photoresist on a wafer during the lithography process for manufacturing a semiconductor device, and (b) Inspecting the parametric electrical property values for each of the coated wafer regions, and (c) subjecting the wafer surface to light energy corresponding to the electrical characteristic values for each wafer region so as to have uniform electrical characteristics. It is characterized by.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 4는 본 발명의 실시 예에 따라 리소그라피의 패터닝 에너지를 영역별로 다르게 조절하여 웨이퍼 전면이 균일한 전기 특성을 가지도록 반도체 기판 예시도이다. FIG. 4 is an exemplary diagram of a semiconductor substrate such that the front surface of the wafer has uniform electrical characteristics by adjusting patterning energy of lithography differently according to an embodiment of the present invention.

본 발명에서는 반도체 소자 제조를 위한 적층과 식각 공정을 진행함에 따라 나타나는 중심부와 가장자리의 단차의 차이 또는 막의 불균일에 의해 소자의 전기적 특성이 중심부와 가장자리의 차이로 인해 높은 수율을 기대할 수 없었던 종래 문제점을 해결하고자, 반도체 공정 중 리소그라피 공정에서 에너지를 영역별로 다르게 줌으로써 마지막 공적이 끝나고 나서 전기적 특성이 웨이퍼 전면에 균일하게 나타나도록 하였다. In the present invention, due to the difference in the difference between the center and the edge or the film unevenness that occurs as the stacking and etching process for manufacturing a semiconductor device, the conventional characteristics that the electrical properties of the device could not be expected due to the difference between the center and the edge. In order to solve this problem, the energy of the lithography process during the semiconductor process was changed in different regions so that the electrical characteristics appeared uniformly on the front surface of the wafer after the last achievement.

즉, 상기 도 4에서 보여지는 바와 같이 본 발명에서는 드라이브 전류 타겟값을 기준으로 드라이브 전류 낮은 중심부에는 에너지를 증가시키고 가장자리에서는 드라이브 전류가 높기 때문에 리소그라피 공정의 패터닝시 에너지를 감소시켜 패터닝 후 선폭을 증가시키는 효과로 웨이퍼 전 영역의 드라이브 전류가 일정하도록 한다. 이에 따라 웨이퍼 전 영역의 드라이브 전류가 일정하게 되어 소자의 수율을 향상시킬 수 있게 되며, 패터닝과 식각이 이루어지는 모든 공정에서 진행할 수 있다. 또한 위의 방법을 사용하게 되는 경우 단위 공정의 공정지수도 높일 수 있게 된다.That is, as shown in FIG. 4, in the present invention, energy is increased at the center of the drive current low based on the drive current target value, and drive current is high at the edge, thereby reducing the energy during patterning of the lithography process, thereby increasing the line width after patterning. As a result, the drive current of the entire wafer region is constant. As a result, the drive current of the entire wafer area becomes constant, thereby improving the yield of the device, and proceeding in all processes in which patterning and etching are performed. In addition, when the above method is used, the process index of the unit process can be increased.

상기한 바와 같이 본 발명에서는 리소그라피의 패터닝 에너지를 영역별로 다르게 조절하여 웨이퍼 전면이 균일한 전기 특성을 가지도록 함으로서 소자의 수율을 높일 수 있게 된다. As described above, in the present invention, the patterning energy of the lithography is adjusted differently for each region so that the front surface of the wafer has uniform electrical characteristics, thereby increasing the yield of the device.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명은 리소그라피의 패터닝 에너지를 영역별로 다르게 조절하여 웨이퍼 전면이 균일한 전기적 특성을 가지도록 함으로서, 소자의 수율을 높일 수 있는 이점이 있으며, 또한 비메모리를 제조하는 공장에서는 다양한 소자에 따른 웨이퍼내의 전기적 특성차이를 소자마다 각각 다른 에너지로 조절하는 레서피로 만들 수 있고 공정지수를 관리하기 편하며, 전기적 특성 데이터를 피드백할 수 있게 하여 지속적으로 균일한 특성을 갖는 소자의 생산을 가능하도록 하는 이점이 있다.As described above, the present invention has the advantage of increasing the yield of the device by controlling the patterning energy of the lithography differently for each region to have a uniform electrical characteristics, and also in a factory for manufacturing non-memory It is possible to make a recipe that controls the difference of electrical characteristics in the wafer according to various devices with different energy for each device, to manage the process index, and to feed back the electrical characteristic data to produce devices with consistent characteristics. There is an advantage to enable this.

Claims (3)

삭제delete 반도체 소자 제조시 에너지 균일화를 위한 노광방법으로서, An exposure method for energy uniformity in manufacturing a semiconductor device, (a)반도체 소자 제조를 위한 리소그라피 공정 시 웨이퍼상에 포토레지스트를 도포하는 단계와,(a) applying a photoresist on a wafer in a lithography process for manufacturing a semiconductor device, (b)포토레지스트가 도포된 웨이퍼 영역별 파라메틱 전기적 특성값을 검사한 후, 상기 리소그라피 공정을 위한 노광장비로 피드백 인가시키는 단계와,(b) inspecting the parametric electrical property values for each of the wafer regions to which the photoresist is applied, and then applying feedback to an exposure apparatus for the lithography process; (c)상기 노광장비에서 상기 피드백 측정되는 웨이퍼 영역별 전기적 특성값을 참조하여 웨이퍼 전면이 균일한 전기적 특성을 갖도록 상기 웨이퍼 영역별로 전기적 특성값에 대응된 빛에너지로 노광을 진행시키는 단계(c) performing exposure with light energy corresponding to the electrical characteristic value for each wafer region so that the entire surface of the wafer has uniform electrical characteristics with reference to the electrical characteristic value for each wafer region measured by the feedback in the exposure apparatus; 를 포함하는 반도체 소자 제조시 에너지 균일화를 위한 노광방법.Exposure method for energy uniformity in manufacturing a semiconductor device comprising a. 제2항에 있어서,The method of claim 2, 상기 (c)단계에서의 노광진행은, 웨이퍼 영역별 전기적 특성값을 피드백 입력받는 스텝퍼 또는 스캐너에 의해 진행되는 것을 특징으로 하는 반도체 소자 제조시 에너지 균일화를 위한 노광방법.The exposure process of step (c) is carried out by a stepper or a scanner receiving a feedback input of the electrical characteristic value for each wafer region, the exposure method for energy uniformity in manufacturing a semiconductor device.
KR1020030101131A 2003-12-31 2003-12-31 Method for exposing wafer for energy uniformity manufacturing a semiconductor device KR100588677B1 (en)

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KR100588914B1 (en) * 2004-12-22 2006-06-09 동부일렉트로닉스 주식회사 Method for uniform electric characteristics of transistor in wafer

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