KR100587051B1 - Semiconductor memory device - Google Patents

Abstract

The semiconductor memory device of the present invention comprises a first and second cell array block comprising a plurality of memory cells and a plurality of word lines and bit line pairs for selecting the cells, and between the first and second cell array blocks. A bit line sense amplifier for sensing and amplifying selected cell data carried on the bit line pair, precharge means for precharging the bit line pair to a precharge voltage during a standby operation of the bit line sense amplifier; A bit connected to a first cell array block and the bit line sense amplifier, and a bit line pair between the bit line sense amplifier and the second cell array block, respectively, and a bit connected to a selected cell of the first and second cell array blocks. A bit line separation means for connecting only a line to the bit line sense amplifier and disabling the remaining three unselected bit lines. By including the configuration, power consumption can be reduced and operation speed can be improved.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

1 is a circuit diagram of a conventional folded bit line sense amplifier

2 is an operation timing diagram of a conventional folded bit line sense amplifier.

3 is a circuit diagram of a bit line sense amplifier according to the present invention.

4 is an operation timing diagram of a bit line sense amplifier according to the present invention.

5 is a voltage waveform diagram of a bit line sense amplifier according to the present invention.

Explanation of symbols on the main parts of the drawings

1a, 1b, 10a, 10b: bit line isolation transistor section

2: precharge circuit 3: bit line sense amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, the present invention relates to a bit line connected to a cell by controlling operation of a bit line isolation transistor that connects a pair of bit lines BL and / BL and a sense amp. The present invention relates to a semiconductor memory device in which only the isolation transistor is turned on to reduce power consumption and improve operation speed.

In general, a bit line sense amplifier is designed to detect and amplify data having a small potential stored in a cell array and then transfer the data to a next circuit.

FIG. 1 is a circuit diagram showing a conventional folded bit line sense amplifier, a sense amplifier 3 for sensing and amplifying data carried on bit line pairs BL and / BL during active operation, and the sense amplifier 3. The bit line isolation transistors 1a and 1b for switching the bit line pairs BL and / BL connected at both ends thereof by the bit line separation signals BISH and BISL, and the standby operation of the sense amplifier 3, respectively. And a precharge circuit section 2 for precharging the bit line pairs BL and / BL to a precharge voltage Vblp.

The operation by the above configuration will be described with reference to the voltage waveform diagram shown in FIG.

First, when a cell array block (not shown) above the bit line sense amplifier unit 3 is selected, the bit line separation signal BISH is in a 'logic high (VPP)' state so that the bit line isolation transistor ( M1 and M2 are turned on, while bit line isolation signal BISL is in a logic low (GND) state to turn off bit line isolation transistors M3 and M4. At this time, the precharge circuit unit 2 does not operate because the precharge signal BLP is in a disabled state GND in an active operation in which the bit line sense amplifier 3 operates.

Thereafter, the word line WL is enabled with the high voltage Vpp, the sense amplifier pull-up bias signal RTO is changed from the precharge voltage Vblp to the power supply voltage Vdd, and the sense amplifier pull-down bias signal / S is free. By transitioning from the charge voltage Vblp to the ground voltage GND, the bit line sense amplifier unit 3 detects a minute voltage difference on the bit line pairs BL and / BL and differentially amplifies the signal ( SBit and / SBit are output as bit line pairs BL and / BL, respectively.

In the conventional semiconductor memo device having the above configuration, the control signals BISH and BISL of the bit line isolation transistor units 1a and 1b are commonly connected to two portions of the bit line BL and the bit line bar / BL. Since the bit line sense amplifier 3 also drives a bit line that is not connected to a cell, power consumption is high.

In addition, since the bit line pairs BL and / BL are not equalized to the inverted phase 1 / 2Vdd which is the precharge voltage Vblp during the precharge operation, a large load is applied to the precharge voltage generator.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to control bit line pair transistors connecting the bit line pairs BL and / BL and the sense amplifiers to the bit line side connected to the cell. To provide a semiconductor memory device by turning on only the isolation transistor of the power consumption to reduce the operation speed.

In addition, another object of the present invention is to open a bit line isolation transistor on the side of the bit line bar (BL) that is not connected to the cell after sensing the bit line BL connected to the cell to some extent. The present invention provides a semiconductor memory device which improves the operation speed by loading opposite data to the / BL).

In order to achieve the above object, the semiconductor memory device of the present invention,

First and second cell array blocks comprising a plurality of memory cells and a plurality of word and bit line pairs for selecting the cells;

A bit line sense amplifier connected between the first and second cell array blocks and configured to sense and amplify selected cell data carried on the bit line pair;

Precharge means for precharging a pair of bit lines to a precharge voltage during a standby operation of the bit line sense amplifier;

A bit line pair connected between the first cell array block and the bit line sense amplifier and the bit line sense amplifier and the second cell array block, respectively, and connected to a selected cell of the first and second cell array blocks. Only a bit line is connected to the bit line sense amplifier, and the remaining three bit lines that are not selected include bit line separation means for disabling.

In the semiconductor memory device of the present invention, each of the bit line separation means is constituted by an NMOS transistor.

In the semiconductor memory device of the present invention, the bit line separation means connected to the selected cell applies a voltage above a threshold voltage of an NMOS transistor, and the remaining three bit line separation means applies a voltage below a threshold voltage of an NMOS transistor. It is characterized by.

In the semiconductor memory device of the present invention, the bit line separating means connects the bit line of the side connected to the cell with the bit line sense amplifier and then connects the bit line of the side not connected to the cell before the precharge command. And the bit line sense amplifier.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

3 is a circuit configuration diagram of a semiconductor memory device according to the present invention, which is connected between first and second cell array blocks (not shown), and detects and amplifies data carried on bit line pairs BL and / BL. A precharge circuit unit 2 for precharging the bit line pairs BL and / BL to a precharge voltage Vblp during a standby operation of the bit line sense amplifier 3 and the bit line sense amplifier 3. And a bit line isolation transistor unit for switching the bit line pairs BL and / BL connected to both ends of the bit line sense amplifier 3 by four bit line separation signals BISHR, BISHL, BISLH, and BISLL, respectively. 1a, 1b). In this case, the bit line isolation transistor units 1a and 1b connect only the bit lines connected to the selected cells of the first and second cell array blocks with the bit line sense amplifier 3, and the remaining three bit lines are not selected. Disable it.

The operation by the above configuration will be described with reference to the voltage waveform diagram shown in FIG.

First, when a cell array block (hereinafter, referred to as a 'first cell array block') above the bit line sense amplifier unit 3 is selected, the bit line separation signals BISLL and BISLR are ground voltage GND. The bit line isolation transistors M3 and M4 are turned off, and the bit line isolation signals BISHR and BISHL are connected to the memory cell, and the bit line isolation signals on the side connected to the memory cell have a high voltage Vpp. The other side changes from the power supply voltage Vdd to the ground voltage GND. If the line connected to the selected cell of the first cell array block is the bit line BL, the bit line isolation signal BISHL is transferred to the high voltage Vpp to turn on the bit line isolation transistor M1 and to isolate the bit line. The signal BISHR transitions to the ground voltage GND to turn off the bit line isolation transistor M2.

As such, by turning on only the bit line of the bit line pair connected to the cell, power consumption generated by the bit line sense amplifier 3 can be reduced by up to 50%.

If the data is evenly distributed according to the state where 0 or 1 data is distributed in the cell, the power can be reduced by up to 50%. If all data is written, there is no effect of reducing the power.

In addition, one of the two outputs of the bit line sense amplifier 3, which is not connected to the bit line, has a small capacitance and is quickly transitioned. This serves to increase the voltage Vgs between the gate sources of the driving transistors of the bit line sense amplifier 3, so that the bit lines also transition faster than before.

5 shows the output waveform (a) of the bit line sense amplifier according to the present invention in comparison with the output waveform (b) of the conventional sense amplifier. As shown, it can be seen that the output signal of the bit line sense amplifier is faster than the conventional one.

The word line WL is enabled with a high voltage (Vpp) and the sense amplifier pull-up bias signal (RTO) is from the precharge voltage (Vblp) to the supply voltage (Vdd), and the sense amplifier pull-down bias signal (/ S) is the precharge voltage. By transitioning from Vblp to the ground voltage GND, the bit line sense amplifier unit 3 detects a minute voltage difference on the bit line pairs BL and / BL and differentially amplifies the signal SBit, / SBit) is output as bit line pairs BL and / BL, respectively.

The precharge circuit unit 2 does not operate because the precharge signal BLP is in a disabled state GND in an active operation in which the bit line sense amplifier 3 operates.

According to another embodiment of the present invention, the following operation is implemented to remove the load applied to the precharge voltage Vblp.

As described above, the bit line separation signal BISHL on the bit line BL side to which the cell is connected is 'logic high', and the bit line on the bit line bar (/ BL) side to which the cell is not connected. The separation signal BISHR is in the 'logic low' state. When the bit line separation signal BISHR is in the 'logic high' state after the sensing operation, opposite data of the bit line BL data is applied to the bit line bar / BL. Will be loaded.

By doing so, the bit line BL and the bit line bar / BL are equalized at a later time during the precharge operation and automatically become a half voltage (1 / 2Vdd) so that the actual load is not applied to the precharge voltage generator.

As described above, according to the semiconductor memory device of the present invention, a first cell array block and a bit line sense amplifier, and a bit cell pair connected between a bit line sense amplifier and a second cell array block are connected to a selected cell. By connecting only the bit lines to the bit line sense amplifiers and disabling the remaining three unselected bit lines, power consumption can be reduced and operation speed can be improved.

According to the present invention, after sensing the bit line BL connected to the cell to some extent, the bit line isolation transistor on the side of the bit line bar (BL) that is not connected to the cell is opened to oppose the bit line bar (/ BL). By loading data, the operation speed can be improved.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (4)

In a semiconductor memory device, First and second cell array blocks comprising a plurality of memory cells and a plurality of word and bit line pairs for selecting the cells; A bit line sense amplifier connected between the first and second cell array blocks and configured to sense and amplify selected cell data carried on the bit line pair; Precharge means for precharging a pair of bit lines to a precharge voltage during a standby operation of the bit line sense amplifier; A bit line pair connected between the first cell array block and the bit line sense amplifier and the bit line sense amplifier and the second cell array block, respectively, and connected to a selected cell of the first and second cell array blocks. And bit line separating means for connecting only a bit line to the bit line sense amplifier and disabling the remaining three unselected bit lines. The method of claim 1, And said bit line separating means are each composed of NMOS transistors. The method of claim 2, The bit line separation means connected to the selected cell applies a voltage equal to or greater than a threshold voltage of an NMOS transistor, And the remaining three bit line separating means apply a voltage below a threshold voltage of the NMOS transistor. The method of claim 1, The bit line separating means, And connecting the bit line of the side connected to the cell with the bit line sense amplifier, and then connecting the bit line of the side not connected to the cell with the bit line sense amplifier before a precharge command.

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