KR100578225B1 - Chip class marking circuit and chip class discriminating method - Google Patents

Abstract

The present invention implements a chip type display circuit in a semiconductor device so as to record as a cut of a fuse and to detect a recorded value using an input / output pin of the device.

The chip type display circuit of the present invention comprises: a fuse box for recording the type of the product as a fuse blown, for receiving a type inquiry signal, and outputting a type identification value as to whether the type is inquired; An identification mode signal generation unit for generating an identification mode signal indicating that the process is for identifying the type of product; And an external output terminal for outputting the type identification value to an external input / output pin.

By using the chip type display circuit according to the present invention, information related to the type or characteristics of the chip is directly displayed on the chip itself, so that the necessary information for each chip separated from the wafer substrate can be easily recognized and mixed. Can be classified.

Fuse circuit, chip type record, chip type identification, parameter record, information display circuit

Description

Chip type display circuit and chip type recording / identification method {CHIP CLASS MARKING CIRCUIT AND CHIP CLASS DISCRIMINATING METHOD}             

1 is a block diagram of a chip type display circuit according to the present invention;

2 is a detailed circuit diagram of the fuse box of FIG.

3 is a detailed circuit diagram of the chip type output module of FIG.

4 is a timing diagram of signals generated in a chip type display circuit according to the present invention;

Fig. 5 is a block diagram showing the structure of a chip type display circuit of the present invention on the bank structure of a semiconductor memory element.

* Explanation of symbols for the main parts of the drawings

100: fuse box 200: identification mode signal generator

300: chip type output module 400: external output module

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type display circuit capable of writing chip information, such as the type of semiconductor device product produced and a specific parameter value, directly into the device. In particular, the present invention relates to a chip type display circuit capable of recording in the form of a cut of a fuse and detecting a recorded value using an input / output pin of the device.

It is common to test each device fabricated at the wafer level during the fabrication process of the semiconductor device to package only those that are above certain quality standards and discard the rest. However, in some cases, products that are below the above-mentioned quality standards, and those that can be used for a specific purpose exist when it is necessary to separately package them. In this case, different kinds of chips with different quality standards are produced on the same wafer.

However, in the packaging process, it is more general to package all the devices produced on the same wafer in the same form, which is advantageous in terms of cost. Therefore, when various types of chips are produced according to the quality standards as described above, if a general packaging process is applied, the types of chips according to the quality standards after packaging are not known, and a lot of time is spent to classify them. There was this.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a chip type display circuit for facilitating classification according to types after packaging.

In addition, another object of the present invention is to provide a chip type display circuit capable of recording the type of the chip produced in the fuse in the semiconductor element.

In addition, another object of the present invention is to provide a chip type display circuit capable of obtaining type information about a chip through a signal output pad provided in a semiconductor device.

The chip type display circuit of the present invention for achieving the above object is to record the type of the product as whether the fuse is disconnected, the fuse for receiving the type inquiry signal, and outputs the type identification value whether it corresponds to the type inquired box; An identification mode signal generation unit for generating an identification mode signal indicating that the process is for identifying the type of product; And an external output terminal for outputting the type identification value to an external input / output pin.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

For example, recording / identification of a parameter value having a small difference to classify as a kind may be a correct expression of 'chip characteristic information recognition', but for the sake of consistency of description, it is expressed as 'chip type identification' in this specification.

(Example 1)

The chip type display circuit of this embodiment as shown in FIG. 1 records the type of the product as whether the fuse is cut off, receives a type inquiry signal through the address input path Add <0: 4>, and receives an inquiry. A fuse box 100 for outputting a chip type detection value chipinfo as to whether or not a type is present; An identification mode signal generator 200 for generating an identification mode signal Tm_chipcode indicating that the product is a process for identifying a type of a product; A chip type output module 300 for outputting the chip type detection value chipinfo to a global input / output line; And an external output module 400 for outputting data carried on the global input / output line to an external input / output pin.

The external output module detects / amplifies data on a global input / output line and transfers the data to an external data input / output pin, which is the same as a general semiconductor device.

The identification mode signal generation unit 200 generates an identification mode signal Tm_chipcode indicating a test mode for determining the chip type by referring to the display mrsp6 of the register set inside the semiconductor device.

The fuse box records chip type information, receives a type inquiry signal through an address bus of a semiconductor device, and outputs a chip type detection value (chipinfo) as to whether the type inquired matches the type recorded. The circuit is shown in FIG.

As shown in FIG. 2, the fuse box 100 includes a first reset MOS transistor P1 to which a power supply voltage is applied to a source and an external reset signal is input to a gate; A fuse 124 provided twice as many as the number of digits of the input address signal and connected to a drain of the reset MOS transistor; And a number of digits of the input address signal, a ground voltage is applied to the source, a drain is connected to the fuse, and a single digit transistor pair 124 in which a bit value and an inverted value of the input address are respectively input to the gate. A fuse recording unit 120 including a;

A second reset MOS transistor (P2) having the same source and gate connection as the first reset MOS transistor (P1); One or more corrected MOS transistor pairs 144 having a ground voltage applied to a source, a drain connected to a drain of the second reset MOS transistor P2, and having a one-digit bit value and an inverted value of an input address respectively input to a gate. ); And a precharge logic corrector 140 including an inverter 148 for inverting the logic state of the drain of the reset MOS transistor P2;

The chip type detection value chipinfo is generated as an AND operation result of the output signal (A node signal) of the fuse recording unit 120 and the output signal (B node signal) of the precharge logic correction unit 140. It consists of an end gate (160).

Two fuse switch units are allocated to one address signal bit, the assigned address bit value is input to one fuse switch unit FS, and the inverted value of the assigned address bit is input to the remaining fuse switch unit FSB. do. In the above structure, the recording of the type identification number is made by cutting one of the two fuse switch units FS and FSB assigned to each digit of the type identification number. The recording is performed by cutting the fuse of the fuse switch unit that is turned on when the type identification number to be written is input through the address bus.

Depending on the structure of the memory device to which the idea of the present invention is applied, only the second digit Lax2 is implemented as described above, and the other digits are paired by two digits somewhat differently from the above description. In addition, an implementation of allocating four fuse switch units may be achieved. In the above implementation, one fuse switch unit is allocated for each of two bit values '00', '01', '10', and '11', and recording the type identification number is one of four fuse switch units. By cutting the fuse.

The reset signal pcg1 is input to the fuse box in the form of a 'low' enable pulse before each address signal is input. The reset signal pcg1 in the 'low' state turns on the first / second reset MOS transistors P1 and P2 to bring the node A to a 'high' potential. When an inquiry signal identical to the recorded type identification number is input via the address bus, the fuses of all the fuse switch units that have been turned on are blown, and the A node has a 'high' potential. When the inquiry signal other than the recorded type identification number is input through the address bus, at least one fuse switch unit is turned on so that the A node has a 'low' potential.

On the other hand, since the node B has an inverted value of the second reset MOS transistor drain potential, the node B has a low potential in the enable period of the reset signal pcg1. As a morph transistor turns on, it has a high potential.

Node A and node B have opposite logic values in most sections, but both have high values in the section in which a chip type inquiry signal identical to the type identification number recorded in the fuse is input. Therefore, the chip type detection value chipinfo outputted by the AND gate 160 has a 'high' value in a section in which a chip type inquiry signal identical to the value recorded in the fuse is input.

4 illustrates the timing of various signals when a chip type identification test is performed by applying an appropriate signal to a semiconductor element chip displaying the chip type using the chip type display circuit of this embodiment. The chip type identification test is performed by sequentially inputting the expected chip type identification number into the address bus of the semiconductor element while informing the chip type display circuit of the chip type identification test. If the chip type identification number input to the address bus and the chip type identification number recorded in the internal fuse box at some point coincide, the designated output pin (dout signal) outputs a predetermined logic state value. You will know the chip type.

3 illustrates an embodiment of a chip type output module. The illustrated chip type output module loads the logic state of the chip type detection value chipinfo on the global input / output line gio when the standard signal iostp and the mode signal Tm_chipinfo are 'high'.

In FIG. 4, a kind inquiry signal is received from an address bus number 13 to a number 16 according to a reference clock clk. The read command and the precharge command are activated between signals of each kind. A read command is generated to activate an input / output related circuit so that a result value can be output to a predetermined data input / output pin. The precharge signal pcg1 is a pulse type that is 'low' enabled upon generation of a precharge command. Has

The node A of the fuse box of FIG. 2 becomes 'high' according to the low enable of the precharge signal, and in a time interval in which an input signal (signal through an address line) having the same value as that recorded in the fuse box is input. It has a 'high' state and has a 'low' state in a time interval when an input signal having a value different from the value recorded in the fuse box is input.

On the other hand, the B node becomes 'low' according to the 'low' enable of the precharge signal, and has a 'high' state in the time interval when the input signal is input through the address line regardless of the value written in the fuse box. .

Since the chip type detection value chipinfo has an AND operation result value of the A node and B node logic states, the chip type detection value chipinfo becomes 'low' according to the 'low' enable of the precharge signal, and is written to the fuse box. It has a 'high' state in a time interval in which an input signal having the same value as the type identification number is input, and has a 'low' state in a time interval in which an input signal having a value different from the kind identification number recorded in the fuse box is input. Therefore, the final output value dout output through the designated input / output pin has a 'high' state in a time interval in which an input signal having the same value as the type identification number recorded in the fuse box is input.

Fig. 5 shows an example of the arrangement of the bank structure in the semiconductor element and the fuse box of this embodiment. As shown in the figure, different parameter characteristics such as tRCDRD, tWR, and tRP are recorded in the fuse boxes implemented in each bank, and the result value indicating the degree of the characteristic is output through the input / output pins connected to each fuse box. It may be.

In the semiconductor device having the chip type display circuit according to the present embodiment, the chip type is recorded in the chip, and the processes of classifying the chips based on the chip type are as follows.

Performing a measurement on a main parameter of the semiconductor device in a state before packaging in which the main component is completed (S110); Using the parameter value measured in step S110 as a type identification number, cutting the fuse using a type identification number of a product in a fuse box in which a redundancy address is recorded (S120); Inputting a series of numbers one by one into the address bus of the product on which the type identification number is recorded, and detecting a logic value of a specific output pin potential (S140); In operation S150, the devices having the same chip type are classified according to the detected logic value. In step S140, when the specific output pin potential transitions to a predetermined logic state, the number input to the address bus is determined as a product type identification number.

Although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto, and the technical spirit of the present invention and the claims to be described below by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents.

By implementing the chip type display circuit according to the present invention, it is possible to directly display information related to the type and characteristics of the chip on the chip itself.

In addition, it is possible to easily classify chips even in a mixed state by recognizing necessary information about each chip separated from the wafer substrate.

Claims (6)

Formed as a semiconductor chip internal component, A fuse box for recording the chip type as whether the fuse is cut, and receiving a type query signal and outputting a chip type detection value as to whether the type query signal corresponds to the type indicated by the type query signal; An identification mode signal generator for generating an identification mode signal indicating that the process is for identifying a chip type; And And a chip type display circuit for outputting the chip type detection value to an external output terminal. The chip type display circuit of claim 1, wherein the type query signal is input through an address input path. The method of claim 2, wherein the fuse box, Performing the reset to generate the chip type detection value of the first logic state, If the kind inquiry signal and the chip type identification number recorded therein are the same, the chip type detection value of the first logic state is maintained. And a chip type detection value for generating the chip type detection value of the second logical partner when the type query signal and the chip type identification number recorded therein are different. The method of claim 2, wherein the fuse box, A reset MOS transistor to which a power supply voltage is applied to a source and a reset signal is input to a gate; A fuse provided with twice the number of signal types of the type inquiry and having one end connected to a drain of the reset MOS transistor; A fuse MOS transistor pair provided with a signal number of the type query, a ground voltage applied to a source, a drain connected to the other end of the fuse, and a single digit bit value and an inverted value of the input address inputted to a gate; And An inverter that receives the drain voltage of the reset MOS transistor and outputs the chip type detection value Chip type display circuit comprising a. Cutting fuses with chip type identification numbers in a fuse box of a type for recording a redundancy address (S120); And Inputting a series of numbers one by one on the address bus of the product having the identification number recorded thereon, and detecting a logic value of a specific output pin potential (S140). Chip type recording / identification method comprising a. The method of claim 5, wherein the step S140, And the number input to the address bus is determined as a corresponding chip type identification number when the specific output pin potential transitions to a predetermined logic state.

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