JP3098499B2 - Semiconductor device and method of recording manufacturing information on semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of recording manufacturing information on a semiconductor device, and more particularly, to a position on a wafer when semiconductor chips constituting the semiconductor device are arranged on the wafer, and a method for recording the semiconductor device. The present invention relates to a semiconductor device capable of recording information indicating a test result and the like, and a method of recording the information on the semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device selection process in a semiconductor device manufacturing process, due to recent miniaturization of a semiconductor device, an increase in defects in a burn-in test such as a short circuit between wires or a short circuit between wires and electrodes has become a problem. . In addition, as a test for a semiconductor device at the time of manufacturing, a wafer test performed on a semiconductor wafer (hereinafter, also simply referred to as a wafer) and a burn-in test after packaging and assembling as a single semiconductor device are performed. In these tests, the measurement states do not completely match each other, so that even if the wafer test passes, it is not often impossible in the test in the sorting process after assembly. However, such defective products can be eliminated at the wafer test stage if the test conditions during the wafer test can be optimized.

By the way, from a semiconductor device excluded as a defective product in a sorting process, information on a chip position of a semiconductor chip (also simply referred to as a chip) constituting the semiconductor device on a wafer and a test result at a wafer test is obtained. If possible, the cause of the failure in the burn-in test can be determined from the information, and the test conditions in the wafer test can be optimized. For example, if it is known from the chip position information that many burn-in test failures occur at the outer peripheral portion of the wafer, the cross-sectional shapes of the outer peripheral portion and the central portion of the wafer can be compared to provide clues to the cause of the failure. it can.

For example, in Japanese Patent Application Laid-Open No. 59-57442, the chip coordinates on a wafer are described as symbols on each chip, and the chip coordinates are read by a sensor and stored in a memory means on the chip together with the chip test results. A technique for selecting chips to be used for assembling based on the contents stored in memory means is disclosed. However, in this conventional technique, since the chip coordinates are directly written on the chip as a symbol, the symbol on the chip cannot be read in a process after the chip is sealed in the package, and there is a problem that it is useless after the sealing.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to identify the position of a chip on a wafer by a semiconductor device after assembly. Another object of the present invention is to provide a semiconductor device and a method of recording manufacturing information on the semiconductor device, which enable information regarding a result of a wafer test to be electrically obtained from the semiconductor device after assembly.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a plurality of fuses and a high level or a low level for each fuse depending on whether each of the fuses is cut or not. A determination circuit for generating a binary signal, an internal circuit for generating the binary signal, different from the determination circuit, a first external terminal for outputting the binary signal generated by the internal circuit, and a test A second external terminal for inputting a mode signal, a binary signal generated by the discrimination circuit and another binary signal generated by the internal circuit, and a test input from the second external terminal A test circuit that selects and outputs one of the binary signal generated by the determination circuit based on a mode signal and the other binary signal, and outputs an output signal of the test circuit to the first external circuit. Terminal Through characterized by comprising an output circuit for outputting to the outside.

The present invention also provides a plurality of fuses, a discriminating circuit for generating a binary signal of a high level or a low level for each fuse depending on whether or not each of the fuses is cut, and The binary signal generated by the determination circuit and another binary signal are input, and one of the binary signal generated by the determination circuit and the other binary signal is selected based on a test mode signal. A method of recording manufacturing information in a semiconductor device, comprising: a test circuit for outputting a test signal; and an output circuit for outputting an output signal of the test circuit to the outside through an external terminal. A position on the wafer is represented by a binary number, the plurality of fuses are associated with each bit of the binary number, and whether the bit is 1 or 0 is determined by whether the fuse is cut or not. The stands, characterized by cutting the fuse to represent the binary number representing the position on the semiconductor wafer.

The present invention also provides a plurality of fuses, a discriminating circuit for generating a binary signal of a high level or a low level for each fuse depending on whether each of the fuses is cut, and The binary signal generated by the determination circuit and another binary signal are input, and one of the binary signal generated by the determination circuit and the other binary signal is selected based on a test mode signal. A method of recording manufacturing information in a semiconductor device, comprising: a test circuit that outputs a test signal to a semiconductor device; and an output circuit that outputs an output signal of the test circuit to an external device through an external terminal. The plurality of fuses are associated with each bit of a binary number, and whether a bit is 1 or 0 is represented by whether or not the fuse is blown. Characterized by cutting the said fuse to represent a binary number representing the test results.

Therefore, in the semiconductor device of the present invention, if the fuse is blown to represent a binary number indicating the position on the semiconductor wafer based on the method of recording manufacturing information on the semiconductor device of the present invention, the position of the semiconductor chip on the wafer is reduced. Can be recorded on the semiconductor chip, and the test result can be recorded on the semiconductor chip by cutting the fuse to represent a binary number representing the test result. The binary information represented by the fuse can be extracted to the outside through the output circuit by supplying a test mode signal to the test circuit and selecting the binary signal generated by the determination circuit. Based on this, the position of the semiconductor chip on the wafer or the test result can be grasped.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a main part circuit diagram showing an example of a semiconductor device according to the present invention, and FIG. 2 is an explanatory diagram showing an arrangement of semiconductor chips on a wafer. Hereinafter, an example of a semiconductor device according to the present invention will be described with reference to these drawings, and at the same time, an embodiment of a method of recording manufacturing information on a semiconductor device according to the present invention will be described.

The semiconductor device 2 of this embodiment constitutes a DRAM (Dynamic Random Access Memory) as an example. As shown in FIG. 1, a plurality of fuses 4, a determination circuit 6, a test circuit 8, And output circuit 10
It is comprised including. The plurality of fuses 4 are for recording chip coordinates on a wafer and the like, and can be blown by irradiating a laser beam. Then, the discriminating circuit 6 provided for each fuse 4 generates a binary signal of a high level or a low level depending on whether the fuse 4 is cut or not. Here, the semiconductor device 2 is, for example, a DRAM having a configuration capable of outputting 8-bit data to the outside, and includes eight sets of fuses 4, a determination circuit 6, a test circuit 8, an output circuit 10, and an external terminal 12. Shall be.

The test circuit 8 generates the 8
The binary signal generated by the discriminating circuit 6 based on the test mode signal 8A is input with a binary signal for bits and a binary signal 8B for another 8 bits representing storage data from a memory element unit (not shown). Signal and other binary signal 8 from the memory element section
B and one of them is selected and output. The output circuit 10 outputs the output signal of the test circuit 8 to the outside through the external terminal 12.

More specifically, a fixed voltage Vcc is applied to one end 14 of each fuse 4, and the other end 16 is connected to an input terminal 18 of the determination circuit 6. Note that the voltage Vcc is a positive voltage. Each discriminating circuit 6 includes a P-type first field-effect transistor 20 as an example, and the gate 22 of the first field-effect transistor 20 is connected to the input terminal 18.
The other end 16 of the channel of the first field-effect transistor 20 is applied with a constant voltage, for example, Ｖ Vcc, to one end 24 of the channel of the first field-effect transistor 20. Is connected to the first output terminal 28 of the determination circuit 6.

The discrimination circuit 6 is, for example, an N-type second
One end 32 of the channel of the second field-effect transistor 30 is connected to the first output terminal 28 of the discriminating circuit 6, and the other end 34 of the channel
Is connected to the ground. The discrimination circuit 6 further includes an inverter 36, an input terminal 38 of the inverter 36 is connected to the first output terminal 28 of the discrimination circuit 6, and an output terminal 40 of the inverter 36 is connected to a second output terminal 42 of the discrimination circuit 6.
It is connected to the. The discriminating circuit 6 outputs a binary signal of a first logical polarity from the first output terminal 28, and a second logical polarity of the opposite logical polarity to the first logical polarity from the second output terminal 42. Is output.

In the present embodiment, the binary signal from the memory element section is a binary signal having a first logical polarity and a binary signal having a second logical polarity opposite to the first logical polarity. The test circuit 8 includes first and second output terminals 28 and 42 of the determination circuit 6 based on the test mode signal 8A.
And a binary signal having first and second logical polarities, and a binary signal having first and second logical polarities forming a binary signal from the memory element section. . Further, the output circuit 10 outputs a signal based on the polarity selection signal 44.
The first and second logic polarities 2 output by the test circuit 8
Output one of the value signals.

The test circuit 8 has an output terminal 46 for outputting a signal from the discriminating circuit 6 and an output terminal 47 for outputting a signal from the memory element section. , 47 are both connected to the input terminal of the output circuit 10. Then, based on the test mode signal, the test circuit 8 outputs the signal from the determination circuit 6 from the output terminal 46 by setting the output terminal 47 to a high impedance state when outputting the signal from the determination circuit 6. Conversely, when outputting a signal from the memory element portion, the output terminal 46 is set to a high impedance state, and a signal from the memory element portion is output from the output terminal 47.

Next, the semiconductor device 2 thus configured
On the other hand, a procedure for recording chip coordinates on a wafer and a result of a wafer test based on a method for recording manufacturing information on a semiconductor device according to the present invention will be described. First, when recording the chip coordinates, the coordinates of the semiconductor chips constituting the semiconductor device 2 on the semiconductor wafer are represented by binary numbers. FIG.
In the example, the X coordinate axis 48 is set in the horizontal direction, and the Y coordinate axis 50 is set in the vertical direction. Then, the wafer 52
Each rectangle arranged above represents each chip, and the number described in the upper right part of each chip represents the coordinates of the chip. This number consists of two digits, the first of which is the X coordinate value,
The next digit represents the Y coordinate value. Therefore, in the figure, for example, the number “23” written on the leftmost semiconductor chip 54 in the third row from the top is the X of this semiconductor chip 54.
The coordinate value is 2 and the Y coordinate value is 3. In the first step described above, these numbers are represented in binary. FIG. 2 is an explanatory diagram to the last, and a larger number of semiconductor chips are arranged on the actual wafer 52.

Next, a plurality of fuses 4 are associated with each bit of the binary number representing the coordinates, and whether a bit is 1 or 0 is represented by whether the fuse 4 is cut or not. Then, the fuse 4 is cut by irradiating a laser beam so as to represent the binary number representing the position on the semiconductor wafer. In this embodiment, the fuse 4 corresponding to a bit having a value of 1 is blown. For example, in the case of the semiconductor chip 54, the binary number representing the coordinates is “0001 0111”, so the LSB and the second, third,
The fuse 4 corresponding to each of the bits will be cut. The cutting of the fuse 4 can be performed, for example, in a laser repair process at the time of a wafer test.

On the other hand, when recording the result of the wafer test on the semiconductor device 2, first, the result of the wear test on the semiconductor device 2 is represented by a binary number. For example, when recording the test result of the hold time of the capacitor constituting the memory element, the result that the hold time is equal to or longer than 6 seconds is represented by “1”, and the result that the hold time is equal to or longer than 5 seconds is equal to “1”. Assuming that the result that is represented by “2” and that the hold time is 4 seconds or more and passed is represented by “3”, these results are represented by binary numbers “0000 0001”,
They will be represented as “0000 0010” and “0000 0011”.

Next, a plurality of fuses 4 are associated with each bit of the binary number representing the test result, and whether the bit is 1 or 0 is indicated by whether the fuse 4 is cut or not. Then, the fuse 4 is cut by irradiating a laser beam so as to represent the binary number representing the test result. For example, the binary number representing the test result is “0000 0011”
In this case, the fuse 4 corresponding to the LSB and the second bit from the LSB is cut.

When the information is read from the semiconductor device 2 on which the information is recorded by cutting the fuse 4 as described above, the following operation is performed. First, the power of the semiconductor device 2 is turned on, and at the same time, a Pon signal that maintains a high level for a certain period after the power is turned on is supplied to the gate 30 </ b> A of the second field-effect transistor 30. As a result, the second field-effect transistor 30 is turned on, and all the low-level signals are output from the first output terminals 28 of the respective determination circuits 6. After that, the Pon signal becomes low level and the second field-effect transistor 30 is turned off, and then the test mode signal 8A is supplied to the test circuit 8 from an external terminal (not shown) to supply the first and second output terminals of the discrimination circuit 6. The signals from 28 and 42 are selected by the test circuit 8 and output.

Here, when the fuse 4 is not blown, the first field effect transistor 20 is turned off, so that the first output terminal 28 outputs a low level signal indicating that the bit value is 0. The signal is output from the second output terminal 42 at a high level. On the other hand, fuse 4
Is turned off, the first field-effect transistor 20 is turned on, and a high-level signal indicating that the bit value is 1 is output from the first output terminal 28 to the second output terminal. 42 outputs a low-level signal.

These signals are input from the test circuit 8 to the output circuit 10 and output from the output circuit 10 to the outside of the semiconductor device 2 through the external terminals 12. Therefore, depending on what kind of signal is output to the external terminal 12, information on the chip coordinates represented by the fuse 4 or the test result can be obtained. In the output circuit 10, a non-inverted signal output from the first output terminal 28 by the determination circuit 6 or a second output terminal according to the polarity selection signal 44 supplied from an external terminal (not shown). Either of the inverted signals output from 42 can be output from the external terminal 12.

As described above, the semiconductor device 2 of the present embodiment is
Then, based on the method of recording manufacturing information on a semiconductor device of the present invention, the position of a semiconductor chip on a wafer 52 is recorded on a semiconductor chip by cutting a fuse 4 so as to represent a binary number representing the position on a semiconductor wafer. Further, the test result can be recorded on the semiconductor chip by cutting the fuse 4 so as to represent a binary number representing the test result. The binary information represented by the fuse 4 is
By supplying the test mode signal 8A to the test circuit 8 and selecting the binary signal generated by the discriminating circuit 6, it can be extracted to the outside through the output circuit 10, and the semiconductor chip wafer can be extracted based on the extracted binary number information. 52
You can grasp the position above or the test result.

Then, by obtaining chip coordinate information on the wafer from the semiconductor device excluded as a defective product in the sorting process, it is possible to know the tendency of occurrence of a defect due to a difference in the position on the wafer, and to obtain the transistor characteristics and the contact resistance. ,
Efficient clues can be obtained by examining trends in the wafer surface of various manufacturing parameters such as layer resistance, wiring and contact dimensions, film thickness, and cross-sectional shape, in order to determine the cause of failure. The production yield can be improved. Further, for a defective product detected after assembly, a test result at the time of a wafer test is read from the chip, and the test conditions of the wafer test can be optimized. For example, if the hold time of the semiconductor device is 3 seconds in the test after assembly, it is excluded as a defective product and the hold time recorded on the chip is 4 seconds. With a second increase, this kind of defective product can be eliminated during the wafer test.

In this embodiment, after the Pon signal becomes low level, the test mode signal 8A outputs
Although the test circuit 8 selects the signal from the discriminating circuit 6, the power can be turned on while the test circuit 8 selects the signal from the discriminating circuit 6 from the beginning. In this case, a low-level (or high-level) signal is output from all the external terminals until the Pon signal goes to a low level, and then, when the Pon signal goes to a low level, the fuse is blown. A signal based on the presence or absence is output. Therefore, it is possible to clearly understand from which timing the signal from the external terminal becomes a signal indicating the blown state of the fuse.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing the second embodiment. In the figure, the same elements as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here. FIG. 3 shows only one set of the fuse 4, the determination circuit 6, the test circuit 8, the output circuit 10, and the external terminal 12 for simplicity. The semiconductor device 56 of the second embodiment shown in FIG. 3 is different from the semiconductor device 2 in that a constant voltage (1) is applied to one end 24 of the channel of the first field-effect transistor 20 through a switch circuit 58. / 2Vcc) is applied. The switch circuit 58 is supplied with the test mode signal 8A, and is turned on / off by the test mode signal 8A. Therefore, in the semiconductor device 56, when the information by the fuse 4 is not output to the outside of the semiconductor device 56,
The switch circuit 58 can be turned off by the test mode signal 8A. As a result, no current flows through the second field-effect transistor 20, so that power consumption can be reduced. Since the semiconductor device 56 is the same as the semiconductor device 2 except for this point, the same effect as the semiconductor device 2 can be obtained.

[0028]

As described above, in the semiconductor device of the present invention, if the fuse is blown to represent a binary number indicating a position on a semiconductor wafer based on the method of recording manufacturing information on the semiconductor device of the present invention, the semiconductor The position of the chip on the wafer can be recorded on the semiconductor chip,
If the fuse is blown to indicate a binary number indicating the test result, the test result can be recorded on the semiconductor chip. The binary information represented by the fuse can be extracted to the outside through the output circuit by supplying a test mode signal to the test circuit and selecting the binary signal generated by the discrimination circuit. Based on this, the position of the semiconductor chip on the wafer or the test result can be grasped.

Then, by obtaining chip coordinate information on the wafer from the semiconductor device excluded as a defective product in the sorting process, it is possible to know the tendency of occurrence of a defect due to a difference in the position on the wafer, and to obtain the transistor characteristics and the contact resistance. ,
Efficient clues can be obtained by examining trends in the wafer surface of various manufacturing parameters such as layer resistance, wiring and contact dimensions, film thickness, and cross-sectional shape, in order to determine the cause of failure. The production yield can be improved.

Further, for a defective product detected after assembly, a test result at the time of a wafer test is read from the chip, and the test conditions of the wafer test can be optimized. For example, if the hold time of the semiconductor device is 3 seconds in the test after assembly, it is excluded as a defective product and the hold time recorded on the chip is 4 seconds. With a second increase, this kind of defective product can be eliminated during the wafer test.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram showing an example of a semiconductor device according to the present invention.

FIG. 2 is an explanatory diagram showing an arrangement of semiconductor chips on a wafer.

FIG. 3 is a main part circuit diagram showing a second embodiment.

[Explanation of symbols]

2 ... semiconductor device, 4 ... fuse, 6 ... discriminating circuit,
8 ... test circuit, 10 ... output circuit, 12 ... external terminal, 14 ... one end, 16 ... other end, 18 ... input terminal,
20: first field effect transistor, 22: gate, 24 ... one end, 26 ... other end, 28 ... first output terminal, 30 ... second field effect transistor, 32 ...
One end, 34 ... the other end, 36 ... an inverter, 38 ... an input terminal, 40 ... an output terminal, 42 ... a second output terminal,
44 ... polarity selection signal, 46 ... output terminal, 48 ... X
Coordinate axis, 50: Y coordinate axis, 52: Wafer, 54:
... Semiconductor chip, 56 ... Semiconductor device, 58 ... Switch circuit.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/66 G01R 31/28

Claims (14)

(57) [Claims] 1. A plurality of fuses, a determination circuit for generating a binary signal of a high level or a low level for each fuse depending on whether or not each of the fuses is blown, and generating a binary signal Internal circuit different from the determination circuit
For outputting the binary signal generated by the internal circuit.
A first external terminal, a second external terminal for inputting a test mode signal, the binary signal generated by the determination circuit, and the internal circuit
The other external signal to be generated is input to the second external terminal.
A test circuit that selects and outputs one of the binary signal and the other binary signal generated by the discrimination circuit based on a test mode signal input from a slave, and an output signal of the test circuit And an output circuit for outputting the signal to the outside through the first external terminal. 2. A fixed voltage is applied to one end of the fuse, the determination circuit includes a first field-effect transistor, and a gate of the first field-effect transistor is connected to the other end of the fuse. 2. The device according to claim 1, wherein a constant voltage is applied to one end of a channel of the first field-effect transistor, and the other end of the channel is connected to a first output terminal of the discriminating circuit. Semiconductor device. 3. The method according to claim 1, wherein the constant voltage is applied to the one end of the channel of the first field effect transistor through a switch circuit, and the switch circuit is turned on / off by the test mode signal. Item 3. The semiconductor device according to item 2. 4. The semiconductor device according to claim 2, wherein said field effect transistor is a P-type field effect transistor, and said constant voltage is a positive voltage. 5. The discrimination circuit includes a second field-effect transistor, one end of the channel of the second field-effect transistor is connected to the first output terminal of the discrimination circuit, and the other end of the channel. 3. The semiconductor device according to claim 2, wherein the terminal is connected to a ground. 6. The discrimination circuit includes an inverter, an input terminal of the inverter is connected to the first output terminal of the discrimination circuit, and an output terminal of the inverter is connected to a second output terminal of the discrimination circuit. The discrimination circuit outputs a binary signal of a first logical polarity from the first output terminal, and outputs a binary signal of a second logical polarity opposite to the first logical polarity from a second output terminal. 3. The semiconductor device according to claim 2, wherein the semiconductor device outputs a signal. 7. The other binary signal includes a binary signal of the first logical polarity and a binary signal of a second logical polarity opposite to the first logical polarity, and the test circuit includes: First and second determination circuits based on the test mode signal.
To select and output one of a binary signal of first and second logical polarities from an output terminal of the first and second and a binary signal of first and second logical polarities forming the other binary signal. 7. The semiconductor device according to claim 6, wherein: 8. The output circuit according to claim 7, wherein the output circuit outputs one of the first and second logical polarity binary signals output from the test circuit based on a polarity selection signal. 13. The semiconductor device according to claim 1. 9. The semiconductor device according to claim 1, wherein said fuse can be blown by irradiating a laser beam. 10. The semiconductor device according to claim 1, comprising a storage device. 11. The semiconductor device according to claim 10, wherein said another binary signal is a signal representing information held by said storage device. 12. A plurality of fuses, a discriminating circuit for generating a binary signal of a high level or a low level for each fuse in accordance with whether each of the fuses is cut, and the discriminating circuit generates A test in which the binary signal and another binary signal obtained as inputs are input, and either the binary signal or the other binary signal generated by the discrimination circuit based on a test mode signal is selected and output. A method for recording manufacturing information on a semiconductor device, comprising: a circuit; and an output circuit for outputting an output signal of the test circuit to an external device through an external terminal, wherein a position of a semiconductor chip constituting the semiconductor device on a semiconductor wafer is provided. Is represented by a binary number. The plurality of fuses are associated with each bit of the binary number, and whether the bit is 1 or 0 is represented by whether the fuse is blown or not. And cutting the fuse to indicate the binary number indicating a position on the semiconductor wafer. 13. A plurality of fuses, a discriminating circuit for generating a binary signal that goes to a high level or a low level for each fuse depending on whether each of the fuses is cut, and the discriminating circuit generates A test in which the binary signal and another binary signal obtained as inputs are input, and either the binary signal or the other binary signal generated by the discrimination circuit based on a test mode signal is selected and output. A method of recording manufacturing information in a semiconductor device, comprising: a circuit; and an output circuit that outputs an output signal of the test circuit to an external device through an external terminal, wherein a result of a plurality of tests on the semiconductor device is expressed in a binary number. The plurality of fuses are associated with each bit of a binary number, and whether a bit is 1 or 0 is represented by whether the fuse is cut or not. Manufacturing method for recording information on the semiconductor device, characterized by cutting the fuse to the representative of the binary number representing the results. 14. The method for recording manufacturing information on a semiconductor device according to claim 12, wherein the fuse is blown by irradiating a laser beam.