KR100575102B1 - Analog-digital converter with pipeline folding scheme - Google Patents

Abstract

The present invention relates to an analog-to-digital converter. In particular, the invention relates to an analog-to-digital converter of a pipeline folding structure.

The analog-to-digital converter of the pipeline folding structure according to the present invention includes a first sample-and-hold unit for sampling and outputting an analog input voltage, a reference voltage generator for generating reference voltages, and an output of the first sample-and-hold unit. Amplifying and subtracting the values of the reference voltages, and outputting the first amplifier to remove the influence of the offset due to the asymmetry of the amplifier, a first folder for folding and outputting the output of the preceding amplifier, and sampling the output of the first folder. A digital output value is obtained by comparing and calculating a second sample-and-hold unit for outputting, a second folder for folding and outputting the output of the second sample-and-hold unit, and an output value of the output of the preceding amplifier and an output value of the second folder. The comparator is included.

The analog-to-digital converter of the pipeline folding structure according to the present invention has an advantage that a high resolution analog-to-digital converter can be realized, in particular, by eliminating offsets caused by mismatching of devices.

Folding, analog-to-digital converter, subraging.

Description

Analog-to-digital converter with pipeline folding scheme             

1 is an analog-to-digital converter of a pipeline folding structure according to the prior art.

2 is a block diagram of an analog-to-digital converter of a pipeline folding structure according to an embodiment of the present invention.

3 is a circuit diagram of a preceding amplifier circuit included in the preceding amplifier employed in the analog-to-digital converter of FIG. 2.

4 is a diagram illustrating waveforms of signals φ1, φ2, and φ3 of FIG. 3.

FIG. 5 is a circuit diagram of a folding circuit included in a first folder employed in the analog-digital converter of FIG. 2.

FIG. 6 is a diagram illustrating the waveform of the φ1D signal of FIG. 5 together with the waveform of the φ1 signal.

FIG. 7 is a circuit diagram of a sample-and-hold circuit included in a second sample-and-hold unit employed in the analog-digital converter of FIG. 2.

FIG. 8 is a circuit diagram of a folding circuit included in a second folder employed in the analog-digital converter of FIG. 2.

FIG. 9 is a view showing the waveform of the φ2D signal of FIG. 8 together with the waveform of the φ2 signal.

FIG. 10 is a circuit diagram of a sample-and-hold circuit included in a third sample-and-hold unit employed in the analog-digital converter of FIG. 2.

FIG. 11 is a circuit diagram of a subranging amplifier employed in the analog-to-digital converter of FIG. 2.

12 is a circuit diagram illustrating an interpolator.

The present invention relates to an analog-to-digital converter. In particular, the invention relates to an analog-to-digital converter of a pipeline folding structure.

Conventional analog-to-digital converters include a first quantizer for quantizing an analog voltage, a residual circuit for outputting a value obtained by subtracting the output of the first quantizer from an analog voltage, and a second quantization for quantizing the output of the remaining circuit. It is composed of groups. Coarse quantizers that pass through the first quantizer may be referred to as fine quantizers. The folding structure analog-to-digital converter is characterized by improving the performance, in particular the speed, of the analog-to-digital converter by replacing the rest of the circuit of the conventional analog-to-digital converter with a folder. The analog-to-digital converter of the pipeline folding structure is an analog-to-digital converter that improves the performance of the folding structure of the analog-to-digital converter by introducing a pipelined scheme in an analog-to-digital converter having a plurality of folders. The pipeline folding structure was published in February 2002 by 'Myung-Jun Choe' in 'IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.36, NO. 2, an An 8-b 100-MSample / s CMOS Pipelined Folding ADC.

1 is an analog-to-digital converter of a pipeline folding structure according to the prior art. The analog-to-digital converter of the pipeline folding structure according to the prior art includes a sample-and-hold unit 1, a reference voltage generator 2, a first folder 3, a first track-and-hold unit 4, A second folder 5, a second track-and-hold section 6, first to third quantizers 7, 8, 9 and a digital encoder 10;

The analog-to-digital converter of the pipeline folding structure according to the related art amplifies and processes the difference between the analog input voltage Vin and the reference voltage through the folders 3 and 5, and therefore, the folders 3 and 5 are stored in the folder 3 and 5. There is a problem in that the resolution that can be implemented is limited by the mismatch of existing devices. It also has track-and-hold portions 4 and 6 between the stages in order to apply the pipeline structure. That is, a structure in which a switch and a capacitor existing between the stages are connected in parallel. Therefore, the input and output signal levels of the previous stage and the next stage should be designed to be the same. If the signal levels are not the same, signal linearity may be degraded. In addition, the configuration of a folder having an odd number of folding factors (factor) has a problem that makes it difficult to decode the lower bits in the multi-stage configuration.

Accordingly, an object of the present invention is to provide an analog-to-digital converter having a high speed, high resolution pipeline folding structure.

As a technical means for achieving the above object, a first aspect of the present invention is a first sample and hold unit for sampling and outputting an analog input voltage, a reference voltage generator for generating reference voltages, the first sample and end Amplifying and outputting values obtained by subtracting each reference voltage to the output of the holding unit, the first amplifier removing the influence of the offset due to the asymmetry of the amplifier, a first folder for folding and outputting the output of the preceding amplifier, and the first folder A comparison operation between a second sample-and-hold unit for sampling and outputting an output, a second folder for folding and outputting an output of the second sample-and-hold unit, and an output value of the output of the preceding amplifier and an output value of the second folder It provides an analog-to-digital converter including a comparator to obtain a digital output value.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

2 is a block diagram of an analog-to-digital converter of a pipeline folding structure according to an embodiment of the present invention. In FIG. 2, the analog-to-digital converter includes a first sample-and-hold unit 11, a reference voltage generator 12, a preceding amplifier 13, a first folder 14, and a second sample-and-hold unit 15. ), A second folder 16, a third sample-and-hold unit 17, a sub ranging amplifier 18, a comparator 19 and a digital error corrector 20.

The first sample and hold unit 11 samples and outputs the differential analog input voltages Vin + and Vin−. The reference voltage generator 12 performs interpolation on the input reference voltages Vref + and Vref- to generate differential reference voltages Vr1 +, Vr1-, Vr2 +, Vr2-, ... Vrm +, Vrm-. Let's do it. The preceding amplifier 13 amplifies and outputs the sampled differential analog input voltages V1s + and V1s- by subtracting the respective differential reference voltages Vrk + and Vrk-; k is a natural number less than or equal to m. The first folder 14 and the second folder 16 fold and output the outputs of the preceding amplifier 13 and the second sample-and-hold section 15, respectively. The second sample-and-hold unit 15 and the third sample-and-hold unit 17 sample and output the outputs of the first folder 14 and the second folder 16, respectively. The subrange amplifier 18 amplifies and outputs the output of the third sample-and-hold unit 17. The comparator 19 receives the positive outputs Va1 +, Va2 +, ... Van + of the preceding amplifier 13, performs a comparison operation on each input, and outputs the sum value MSB of the number of '1's. do. In addition, after receiving a positive output of the second folder 16, a comparison operation is performed on each input, and a value MLSB obtained by adding up the number of '1' is output. In addition, the positive output of the subranging amplifier 18 is input, and a comparison operation is performed on each input, and then a value LSB obtained by adding up the number of '1' is output. Here, the comparison operation means an operation that outputs one of '1' and '0' when the input value is larger than the threshold value and outputs the remaining value of '1' and '0' in the reverse case. do. The digital error corrector 20 receives the output signal of the comparator and checks whether there is an error of a digital value, and performs a function of healing an error when an error occurs.

The analog-to-digital converter according to an embodiment of the present invention amplifies a value obtained by subtracting each reference voltage from the sampled differential analog input voltages V1s + and V1s- and passes them through a comparator 19 to form an upper bit MSB. . An output obtained by folding the outputs of the preceding amplifier 13 twice is passed through the comparator 19 to form an intermediate bit MLSB. After amplifying the output of the second folder 16, the comparator 19 is passed through to form the lower bit LSB. The upper bit MSB receives the middle bit MLSB and the lower bit LSB, corrects an error, and outputs a final N bit digital signal.

Each stage samples the front end signal through a series connected capacitor, allowing the application of a pipeline structure for high speed operation while being separated from each other DC. Therefore, the output voltage of each stage and the input voltage of the next stage can be designed differently, which increases flexibility in circuit design and secures a wider linear region.

Hereinafter, the preceding amplifier employed in the analog-to-digital converter of FIG. 2 will be described with reference to FIGS. 3 and 4.

3 is a circuit diagram of a preceding amplifier circuit included in the preceding amplifier employed in the analog-to-digital converter of FIG. 2. The preceding amplifier includes a plurality of preceding amplifier circuits. In FIG. 3, the preceding amplifier circuit includes an amplifier 21, an input unit 22, an output unit 23, and a reset unit 24.

The amplifier 21 amplifies the voltage at the differential input terminal of the amplifier and outputs it to the differential output terminal of the amplifier. The input unit 22 applies a common voltage to the differential input terminal of the amplifier 21 in a period where the signal φ1 is '1', and a positive analog input sampled at the differential input terminal of the amplifier 21 during the period when the signal φ2 is '1'. The subtracted voltage between the voltage V1s + and the positive reference voltage (Vrk +; k is a natural number less than or equal to n) and the sampled negative analog input voltage (V1s-) and negative reference voltage (Vrk-). Add the voltage that performed the subtraction operation in between. The output unit 23 stores the offset voltage due to the asymmetry of the amplifier 21 in the period where the signal φ1 is '1', and outputs the signal φ1 at the differential output of the amplifier 21 in the period where the signal φ2 is '1'. The value is obtained by subtracting the offset voltage stored in the period of '1'. The reset section 24 interconnects the differential output stages of the amplifier 21 in a period where the signal? 3 is '1'.

From another angle, the preceding amplification circuit includes an amplifier 21, seven switches SW1 to SW7, and four capacitors CIN1, CIN2, CO1, CO2 for canceling the offset.

The first switch SW1 is turned on when the? 1 signal is '1', and connects the sampled analog input voltage V1s + to the first terminal of the first capacitor CIN1. The second switch SW2 is turned ON when the signal φ2 is '1', thereby connecting the positive reference voltage Vrk + to the first terminal of the first capacitor CIN1. The third switch SW3 is turned ON when the signal φ2 is '1' to connect the negative reference voltage Vrk- to the first terminal of the second capacitor CIN2. The fourth switch SW4 turns ON when the? 1 signal is '1', and connects the sampled negative analog input voltage V1s- to the first terminal of the second capacitor CIN2. Second terminals of the first and second capacitors CIN1 and CIN2 are connected to the differential input terminal of the amplifier 21, respectively. The fifth switch SW5 is turned on when the φ1 signal is '1', thereby connecting the common voltage CM to the second terminal of the first capacitor and the second terminal of the second capacitor. The amplifier 21 amplifies and outputs a differential input. The amplifier 21 includes a current source Is, two NMOS transistors MN1 and MN2 and two loads RL1 and RL2. The gates of the first and second NMOS transistors MN1 and MN2 are connected to differential inputs respectively input to the amplifier 21, the source is connected to the first terminal of the current source Is, and the drain of the amplifier 21 is respectively. It is connected to the differential output stage. The second terminal of the current source is connected to ground, the first terminals of the first and second loads RL1 and RL2 are connected to the voltage power supply VDD, and the second terminal is connected to the differential output terminal of the amplifier 21, respectively. . The sixth switch SW6 turns ON when the φ3 signal is '1' to interconnect the differential output terminals of the amplifier 21. The first terminals of the third and fourth capacitors are respectively connected to the differential output terminal of the amplifier 21, and the second terminal is connected to the output terminal of the preceding amplifier circuit. The seventh switch SW7 is turned on when the φ1 signal is '1' to connect the common voltage CM to the second terminal of the third capacitor and the second terminal of the fourth capacitor.

4 is a diagram illustrating waveforms of signals φ1, φ2, and φ3 of FIG. 3. In Fig. 3, φ1 and φ2 alternately become '1', and there is no period in which both signals become '1' at the same time. φ3 is a signal that becomes '1' for a while in a period where φ1 is '1' and is '0' in other periods.

In the period when phi 1 is '1', the sampled positive analog input voltage V1s + is connected to the first terminal of the first capacitor CIN1, and the common voltage CM is connected to the second terminal. Therefore, the voltage CM-V1s + is applied between the second terminal and the first terminal of the first capacitor. In the same manner, a voltage CM-V1s-is applied between the second terminal and the first terminal of the second capacitor. Since the differential input terminals of the amplifier 21 are all connected to the common voltage CM, the differential output terminals of the amplifier 21 should theoretically have the same voltage. However, due to the asymmetry of the first and second NMOS transistors NM1 and NM2 and the first and second loads RL1 and RL2, an offset voltage ΔV occurs. As a result, the voltage of the first terminal of the fourth capacitor CO2 is higher than the offset voltage ΔV rather than the voltage of the third capacitor CO1, and eventually the voltage applied between the second terminal and the first terminal of the fourth capacitor CO2. Has a voltage lower than the voltage applied between the second terminal and the first terminal of the third capacitor by the offset voltage ΔV.

In a period when φ2 is '1', a positive reference voltage Vrk + is connected to the first terminal of the first capacitor CIN1, and a negative reference voltage Vrk- is connected to the first terminal of the second capacitor CIN2. Is connected. Thus, the voltages (Vrk +-V1s + + CM) and (Vrk--V1s- + CM) are applied to the differential input terminals of the amplifier 21, respectively. The amplifier 21 is ideally amplified and output by subtracting the other input from one of the differential input stages. However, due to the asymmetry of the amplifier as described above, a voltage higher by the offset voltage [Delta] V than the output of the ideal amplifier is formed at the first terminal of the fourth capacitor. However, as described above, the voltage applied between the second terminal and the first terminal of the fourth capacitor in the period when φ1 is '1' has a voltage as low as the offset voltage ΔV, so in the period when φ2 is '1'. A value obtained by offsetting the offset voltage ΔV is output to the second terminal of the fourth capacitor. Therefore, the differential output voltages Vak + and Vak- of the preceding amplifier circuit output in the period of phi 2 being '1' are not affected by the offset voltage ΔV.

In the period when φ3 is '1', the sixth switch SW6 becomes '1', which serves to quickly reset the output terminal of the amplifier 21.

Since the prior amplification circuit effectively cancels the offset generated in the linear amplification circuit itself, by increasing the amplification ratio of the linear amplification circuit, it is possible to optimize the influence of the offset generated in the subsequent folder.

Hereinafter, a first folder employed in the analog-to-digital converter of FIG. 2 will be described with reference to FIGS. 5 and 6.

FIG. 5 is a circuit diagram of a folding circuit included in a first folder employed in the analog-digital converter of FIG. 2. The first folder includes a plurality of folding circuits.

In FIG. 5, the folding circuit is a folding circuit having three differential inputs, that is, a folding circuit having a folding factor of three. Typically, the folding circuit has an odd number of differential inputs. The folding circuit has three current switches 25, 26, 27, two loads RL and one switch SW. Each current switch consists of two NMOS transistors (NM) and one current source (Iss), and converts the differential input voltage into a differential current and outputs it. The output terminals of the current switches 25, 26, 27 are connected to the differential output terminals of the folding circuit, but are alternately connected. That is, the positive output of the first current switch 25 is connected to the positive output terminal of the folding circuit and the negative output is connected to the negative output terminal of the folding circuit, but the positive output of the second current switch 26 is folded The negative output of the circuit is connected to the positive output of the folding circuit, the positive output of the third current switch 27 is connected to the positive output of the folding circuit and the negative output of the folding circuit It is connected to the negative output terminal.

FIG. 6 is a diagram illustrating the waveform of the φ1D signal of FIG. 5 together with the waveform of the φ1 signal. In FIG. 6, it can be seen that the φ1D signal is a signal having a longer period of '1' than the φ1 signal.

The output signal of the folding circuit is reset in the period where the? 1D signal is '1', and then the linear amplifier output signal is folded and output in the period where the? 2 is '1'. The reset time of the folder is slightly longer than the period in which φ1 is '1', thereby preventing the backflow of the signal by the previous signal stored in the next stage in the period when φ2 is '1' and allowing the output signal to settle faster.

Hereinafter, a second sample-and-hold unit employed in the analog-digital converter of FIG. 2 will be described with reference to FIG. 7.

FIG. 7 is a circuit diagram of a sample-and-hold circuit included in a second sample-and-hold unit employed in the analog-digital converter of FIG. 2. The second sample-and-hold portion includes a plurality of sample-and-hold circuits. Each sample-and-hold circuit includes a voltage obtained by subtracting the input voltage Vin from the second common voltage CM2 between the second terminal and the first terminal of the capacitor CIN in a period where φ2 is '1', that is, (CM2 −). After the Vin voltage is applied, the first common voltage CM1 is applied to the first terminal of the capacitor CIN during the period when φ1 is '1', so that the output terminal is connected to the output terminal during the period when φ1 is '1'. + CM2-Vin) voltage. By operating in this manner, the sample-and-hold circuit samples and outputs the output signal of the first folder.

Hereinafter, a second folder employed in the analog-to-digital converter of FIG. 2 will be described with reference to FIGS. 8 and 9.

FIG. 8 is a circuit diagram of a folding circuit included in a second folder employed in the analog-digital converter of FIG. 2. The second folder includes a plurality of folding circuits. FIG. 9 is a view showing the waveform of the φ2D signal of FIG. 8 together with the waveform of the φ2 signal. The folding circuit of the second folder has only a difference in timing compared to the folding circuit of the first folder, and there is no difference in the configuration of the folding circuit. That is, the folding circuit of the second folder resets the output signal of the folding circuit in the period when the? 2D signal is '1', and then folds the output signal of the second sample-and-hold part in the period when? 1 is '1'. Output

Hereinafter, a third sample-and-hold unit employed in the analog-to-digital converter of FIG. 2 will be described with reference to FIG. 10.

FIG. 10 is a circuit diagram of a sample-and-hold circuit included in a third sample-and-hold unit employed in the analog-digital converter of FIG. 2. The third sample and hold portion includes a plurality of sample and hold circuits. Each sample-and-hold circuit includes a voltage obtained by subtracting the input voltage Vin from the second common voltage CM2 between the second terminal and the first terminal of the capacitor CIN during a period of φ1 '1', that is, (CM2 −). After the Vin voltage is applied, the first common voltage CM1 is applied to the first terminal of the capacitor CIN in the period when φ2 is '1', thereby providing (CM1) to the output terminal in the period when φ2 is '1'. + CM2-Vin) voltage. By operating in this manner, the sample-and-hold circuit samples and outputs the output signal of the second folder.

Hereinafter, a subranging amplifier employed in the analog-to-digital converter of FIG. 2 will be described with reference to FIG. 11.

FIG. 11 is a circuit diagram of a subranging amplifier employed in the analog-to-digital converter of FIG. 2. In FIG. 11, the subranging amplifier includes five amplifiers 28 to 32 and an interpolator 33.

The third amplifier 30 receives as an input the output of the third sample-and-hold portion determined by the output value of the second folder. The second and fourth amplifiers 29 and 31 receive upper and lower levels of the input of the third amplifier 30, respectively. The first and fifth amplifiers 28 and 32 receive the upper level of the second amplifier 29 and the lower level of the input of the fourth amplifier 31, respectively. The interpolator 33 interpolates the output voltages of the first to fifth amplifiers 28 to 32 with a resistance and outputs the interpolators 33.

At this time, in the case of the amplifiers 28 and 32 at both ends of the sub-lasing amplifier, the output signals of the two amplifiers 28 and 32 are inverted from each other in order to have the same output condition as the other amplifiers 29, 30 and 31. Connecting with a resistor can lead to an improvement in resolution. In a differential architecture, the same effect can be achieved by reversing the differential outputs of the two amplifiers against each other.

Hereinafter, with reference to FIG. 12, an interpolator that can be used for the output stages of the preceding amplifier, the first folder, and the second folder employed in the analog-to-digital converter of FIG. 2 will be described. 12 is a circuit diagram illustrating an interpolator. The interpolator is composed of a plurality of resistors connected in series and interpolates and outputs an input signal. The interpolator can be used in connection with the outputs of the preceding amplifier, the first folder and the second folder.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various modifications are possible within the scope of the technical idea of the present invention.

The analog-to-digital converter of the pipeline folding structure according to the present invention has an advantage that a high resolution analog-to-digital converter can be realized by eliminating offset caused by the asymmetry of the amplifier.

In addition, the analog-to-digital converter of the pipeline folding structure according to the present invention has an advantage that it can be applied even when the signal level of each folder is not the same by connecting each folder with a sample-and-holding unit.

In addition, the analog-to-digital converter of the pipeline folding structure according to the present invention has a high resolution by providing a subranging amplifier.

Claims (9)

A first sample-and-hold unit for sampling and outputting an analog input voltage; A reference voltage generator for generating reference voltages; A preamplifier configured to amplify and output values obtained by subtracting each reference voltage to an output of the first sample and hold unit, and to sequentially process for different periods of time to remove the influence of offset due to asymmetry of the amplifier; A first folder for folding and outputting the output of the preceding amplifier; A second sample-and-hold unit for sampling and outputting the output of the first folder; A second folder for folding and outputting an output of the second sample and hold unit; And And a comparator for comparing the output of the preceding amplifier and the output of the second folder to obtain a digital output value. The method of claim 1, The preceding amplifier has a plurality of preceding amplifier circuits and each preceding amplifier circuit An amplifier for amplifying the voltage at the differential input stage and outputting the differential output stage; The common voltage is applied to the differential input terminal of the amplifier in the first period, and the subtracted voltage and the sampled negative voltage are performed between the positive analog input voltage and the positive reference voltage sampled at the differential input terminal of the amplifier in the second period. An input unit configured to apply a voltage obtained by performing a subtraction operation between the analog input voltage and the negative reference voltage; An output unit which stores an offset voltage due to asymmetry of the amplifier in the first period, and outputs a voltage obtained by subtracting the offset voltage stored in the first period from the differential output of the amplifier in the second period; And A reset section for interconnecting the differential output stages of said amplifier in a third period of time, And the first period and the second period are alternately repeated, there is no overlapping part, and the third period is a period corresponding to the front part of the first period. The method of claim 1, The preceding amplifier has a plurality of preceding amplifier circuits and each preceding amplifier circuit A first capacitor having a first terminal and a second terminal; A second capacitor having a first terminal and a second terminal; A third capacitor having a first terminal and a second terminal; A fourth capacitor having a first terminal and a second terminal; A first switch for connecting a sampled positive analog input voltage to the first terminal of the first capacitor only for a first period; A second switch for connecting a positive reference voltage to the first terminal of the first capacitor only for a second period of time; A second switch for connecting a negative reference voltage to the first terminal of the second capacitor only in the second period; A first switch for connecting a negative analog input voltage sampled only for the first period to a first terminal of the second capacitor; A fifth switch connecting the common voltage to the second terminal of the first capacitor and the second terminal of the first capacitor only in the first period; An amplifier having a differential input terminal connected to a second terminal of the first capacitor and a second terminal of the first capacitor, and a differential output terminal connected to a first terminal of the third capacitor and a first terminal of the fourth capacitor; A sixth switch interconnecting the differential output stages of the amplifier only for a third period of time; A seventh switch connecting the common voltage to the second terminal of the third capacitor and the second terminal of the fourth capacitor only for a first period, And the first period and the second period are alternately repeated, there is no overlapping part, and the third period is a period corresponding to the front part of the first period. The method of claim 3, wherein The amplifier comprises a first NMOS transistor, a second NMOS transistor, a current source, a first load and a second load, The gate, source and drain of the first NMOS transistor are respectively connected to the positive input terminal of the amplifier, the first terminal of the current source and the positive output terminal of the amplifier, The gate, source and drain of the second NMOS transistor are respectively connected to the negative input terminal of the amplifier, the first terminal of the current source and the negative output terminal of the amplifier, The second terminal of the current source is connected to ground; The first load is connected to the positive output of the voltage supply and the amplifier, And the second load is connected to the negative output of the voltage power supply and the amplifier. The method of claim 1, The first and second folders include a plurality of folding circuits and each folding circuit Including an odd number of current switches, a first load, a second load and a switch for converting an odd number of differential input voltage to an odd number of differential current, respectively, The output terminals of the odd number of current switches are alternately connected to the differential output terminals of the folding circuit, The first load is connected to a positive output terminal of the voltage power supply and the folding circuit, The second load is connected to a negative output terminal of the voltage power supply and the folding circuit, The switch is connected to a positive output terminal and a negative output terminal of the folding circuit. The method of claim 5, wherein The current switch includes a first NMOS transistor, a second NMOS transistor and a current source, A gate, a source and a drain of the first NMOS transistor are respectively connected to the positive input terminal of the current switch, the first terminal of the current source and the positive output terminal of the current switch, The gate, source and drain of the second NMOS transistor are respectively connected to the negative input terminal of the current switch, the first terminal of the current source and the negative output terminal of the current switch, And the second terminal of the current source is connected to ground. The method of claim 1, The analog-digital converter further includes a third sample-and-hold unit for sampling and outputting the output of the second folder and a subranging amplifier for amplifying and outputting the output of the third sample-and-hold unit, And the comparator additionally compares the output of the subranging amplifier to obtain a digital output value. The method of claim 7, wherein The subranging amplifier A plurality of amplifiers for amplifying and outputting a plurality of input signals, respectively; And And an interpolator for interpolating and outputting the output signal of the amplifier. The method according to any one of claims 1 to 8, At least one of the preceding amplifier, the first folder and the second folder further comprises an interpolator for interpolating and outputting an output signal.

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