KR100572312B1 - Digital-to-analog converter with improved output range at low voltage - Google Patents

Abstract

The present invention relates to a digital to analog converter (DAC), and more particularly to a CMOS digital to analog converter. The DAC according to the present invention can be largely divided into a DAC bias circuit and a DAC current source circuit that generate a bias voltage. In the CMOS current output type DAC as described above, the current source circuit is the most important block. In the present invention, the DAC current source circuit using the first current source circuit and the second current source circuit can be configured to increase the signal-to-noise ratio (SNR) at low voltage while improving the output range from the ground voltage to the supply voltage level (rail-to-rail). have.

Description

Digital analog converter with improved output range at low voltage {D / A CONVERTER FOR RAIL TO RAIL OUTPUT DYNAMIC RANGE IN LOW POWER SYSTEM}

1 shows an output voltage range of a DAC using only a conventional PMOS current source;

2 shows an output voltage range of a DAC using only a conventional NMOS current source;

3 shows an output voltage range of a DAC according to the present invention;

4 shows the regulated output voltage range of the DAC according to the present invention;

5 is a block diagram showing a DAC circuit according to the present invention;

6 is a circuit diagram showing a DAC bias circuit according to the present invention;

7 is a circuit diagram showing a DAC current source circuit according to the present invention; And

8 is a circuit diagram showing an example for adjusting the output range of the DAC current source circuit according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: bias circuit 200: DAC current source circuit

210: decoding logic 260: first current source circuit

270: second current source circuit 290: multiplexer

300: D / A Converter

The present invention relates to a digital to analog converter (DAC), and more particularly to a CMOS digital to analog converter.

In recent years, CMOS current output type has been increasingly used to implement high resolution, high speed digital to analog converter (DAC). This type of DAC was published in April 1991 by Yasuyuki Nakamura et al. In IEEE Journal of Solid-state Circuits, Vol. 26, No. 4, on page 637, entitled "A 10-b 70MS / s CMOS D / A Converter." This type of DAC is widely used due to the development of CMOS process technology, the system on chip tends to become stronger, and the power efficiency reaches almost 100%, without loss. This is because linearity can be satisfactorily satisfied. The DAC described above was published in February 1994 by Vorenkamp, P., et al., Titled "A 1 GSample / s, 10b Digital-to-Analog Converter" on pages 52-53 of the ISSCC Digest of Technical Papers.

In the CMOS current output type DAC, the current source is the most important block. In general, a PMOS current source or an NMOS current source is used for the CMOS current output type DAC. However, when only the PMOS current source or the NMOS current source is used as described above, the dynamic range of the output current is inevitably reduced.

1 is a view showing the output voltage range of the DAC using only the conventional PMOS current source, Figure 2 is a view showing the output voltage range of the DAC using only the conventional NMOS current source. Here, the hatched portion is the output range corresponding to each case.

As shown in FIG. 1, when only the PMOS current source is used, an operating region of a transistor used as a PMOS current source may be used as a current source only in a saturation region of the MOS. Therefore, in order to keep the PMOS current source transistor in a saturation region, the output voltage needs to secure a constant voltage V _{DS_P} from the power supply voltage V _DD . Therefore, once the drain-source voltage (V _{DS_P} ) is secured, the output range is reduced. That is, it is limited by the upper limit of the output voltage. In this case, if a large input is desired in a block attached to the DAC, an output range is limited. An example of a DAC using only a PMOS current source as described above is described in CH. Lin et al. Disclose in "A 10b 250 MSamples / s CMOS DAC 1mm2" published in ISSCC98 / SESSION14 / ANALOG TECHNIQUES / PAPER FP 14.1.

In addition, as shown in FIG. 2, when only an NMOS current source is used, a constant voltage V _{DS_N} must be secured from the ground voltage GND. Therefore, once the drain-source voltage (V _{DS_N} ) is secured, the output range is reduced. That is, it is restricted by the lower limit of the output voltage. Therefore, in this case, the output range may be increased by using an operational amplifier (OP-amp) to secure the output range. However, although the signal is large when the operational amplifier is used, there is a limitation in the operational amplifier, which is also limited in an application for full swing from the ground voltage GND to the power supply voltage V _DD level. . In addition, there is a problem of being limited to signal to noise ratio (SNR) before amplification. One example of using only an NMOS current source as described above is described in US Pat. No. 5,164,725 "DIGITAL TO ANALOG CONVERTER WITH CURRENT SOURCES PAIRED FOR CANCELING ERROR SOURCES".

In light of recent trends in the use of low voltage portable batteries, the output of the DACs has to be reduced. However, the conventional DAC has a problem in that the output range is further reduced because the voltage between the drain and the source of the current source must be secured. Therefore, when using the low voltage as described above, there is a need for a current source circuit of the D / A converter that can increase the output range from the ground voltage to the supply voltage level (rail-to-rail) while increasing the signal to noise ratio (SNR).

Accordingly, it is an object of the present invention to provide a current source circuit of a D / A converter which improves the output at low voltage while maintaining a desired signal-to-noise ratio.

According to a feature of the present invention for achieving the object of the present invention as described above, the digital-to-analog converter with improved output range at low voltage includes a bias circuit for generating the first to fourth bias voltage of the same level; A first current source circuit for generating a first output voltage in response to the first and second bias voltages and the first and second clock signals; A second current source circuit for generating a second output voltage in response to the third and fourth bias voltages and the third and fourth clock signals; When digital data to be converted is input, selecting a first clock signal, a second clock signal complementary to the first clock signal, a third clock signal, a fourth clock signal complementary to the third clock signal, and an output voltage Decoding logic for generating an output selection signal for the device; In response to the output selection signal, one of the input first and second output voltages is selected and outputted, and a voltage level of which is lower than the reference voltage is applied to the digital data using a voltage corresponding to half of a power supply voltage as a reference voltage. And a multiplexer for outputting the first output voltage when outputting the analog voltage, and outputting the second output voltage when outputting the analog voltage for the digital data higher than the reference voltage.

In a preferred embodiment, the first current source circuit accepts the first and second bias voltages at their respective gates, and two PMOSs in which current paths are connected in series with one end of the current path connected to a supply voltage. A first current source consisting of a transistor; A first switch transistor comprising a PMOS transistor having a gate receiving the first clock signal, a source connected to a current path of the first current source, and a drain; A second switch transistor comprising a PMOS transistor having a gate receiving the second clock signal, a source connected to the current path of the first current, and a drain; A first resistor formed between the first switch transistor and a ground voltage; A second resistor formed between the second switch transistor and a ground voltage; A first node connecting the first switch transistor and the first resistor; A second node connecting the second switch transistor and the second resistor; And a first voltage output terminal for outputting a voltage between the first and second nodes as a first output voltage.

In a preferred embodiment, the second current source circuit accepts the third and fourth bias voltages at its respective gates, and two NMOS current paths connected in series with one end of the current path connected to a ground voltage. A second current source consisting of a transistor; A third switch transistor comprising a NMOS transistor having a gate receiving the fourth clock signal, a source connected to a current path of the second current source, and a drain; A fourth switch transistor comprising an NMOS transistor having a gate receiving the third clock signal, a source connected to the current path of the second current, and a drain; A third resistor formed between the third switch transistor and the power supply voltage; A fourth resistor formed between the fourth switch transistor and the power supply voltage; A third node connecting the third switch transistor and the third resistor; A fourth node connecting the fourth switch transistor and the fourth resistor; And a second voltage output terminal for outputting a voltage between the third and fourth nodes as a second output voltage.

In a preferred embodiment, the output voltage range can be adjusted by connecting a resistor between the first and second resistors and the ground voltage, and between the third and fourth resistors and the power supply voltage, respectively. .

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 8.

3 is a view showing the output voltage range of the DAC according to the present invention. Here, the hatched portion is the range of the output voltage.

5 is a block diagram showing a DAC circuit according to the present invention.

First, referring to FIG. 5, the DAC 300 according to the present invention may be divided into a DAC bias circuit 100 and a DAC current source circuit 200 generating a bias voltage. The first current source circuit 260 and the second current source circuit 270 of the DAC current source circuit use a PMOS and an NMOS current source, respectively. The first output voltage Vout1 of the first current source circuit 260 is limited to the upper limit of the output voltage, but can be output to the ground voltage GND level at a low voltage output (see FIG. 1). The second output voltage Vout2 of the second current source circuit 270 is limited by the lower limit of the output voltage, but can be output up to the power voltage V _DD level at a high voltage output (see FIG. 2). Therefore, the DAC 300 according to the present invention selectively outputs one of the first and second output voltages Vout1 and Vout2 as described above, so that the output range is at the ground voltage level as shown in FIG. 3. The output can be enhanced to allow full swing on a rail-to-rail.

Looking at a more detailed configuration of the DAC circuit according to the present invention as described above are as follows.

6 is a circuit diagram showing a DAC bias circuit according to the present invention. 7 is a circuit diagram showing a DAC current source circuit according to the present invention.

Referring to FIG. 6, the DAC bias circuit according to the present invention outputs the first to fourth bias voltages VBP, VBC, VBM, and VBN of the same level. The resistor R1 of FIG. 6 is a resistor that generates a reference current, and the six NMOS transistors MN1 to MN6 form a cascode current mirror to deliver the same amount of current. Four PMOS transistors MP1 to MP4 supply the first and second bias voltages VBP and VBC by the reference current, and the NMOS transistors MN1 to MN6 have the same level of third and fourth voltages. The bias voltages VBM and VBN are supplied. Herein, the resistor R1 may use an external resistor or an internal resistor. If the resistor R1 is used as an external resistor, the resistors R2 to R5 used in FIG. 7 must also be used as external resistors for matching. Likewise, if the resistor R1 is used as the internal resistance, the resistors R2 to R5 used in FIG. 7 should also be used as the internal resistance.

Referring to FIG. 7, the DAC current source circuit 200 according to the present invention includes a first current source circuit 260, a second current source circuit 270, a decoding logic 210, and a multiplexer 290.

The first current source circuit 260 includes a first current source 230 composed of two PMOS transistors MP1 and MP2, a first switch circuit 235 composed of first and second switch transistors MP3 and MP4, and A first resistor R2 formed between the first switch transistor MP3 and the ground voltage GND, a second resistor R3 formed between the second switch transistor MP4 and the ground voltage GND, A first node N1 connecting the first switch transistor MP3 and the first resistor R2, a second node N2 connecting the second switch transistor MP4 and the second resistor R3, And a first voltage output terminal for outputting the voltage Vout1 between the first and second nodes N1 and N2 to the multiplexer 290. The first and second bias voltages VBP and VBC of the bias circuit 100 are applied to gates of the two PMOS transistors MP1 and MP2 of the first current source circuit 260, respectively. In this case, a current equal to the reference current of the bias circuit 100 flows to the two PMOS transistors MP1 and MP2. At this time, the decoding logic 210 receives the input of the DCA 300 and generates clocks CK1 and CKB1 for controlling the on and off of the switch transistors MP3 and MP4 of each current source. . The currents controlled by the clock in the first current source circuit 260 flow to the first and second resistors R2 and R3 so that the voltage Vout1 between the first and second nodes N1 and N2. Is output to the multiplexer 290. In particular, the current source 230 of the first current source circuit 260 is composed of PMOS transistors MP1 and MP2. Therefore, the first output voltage Vout1 of the first current source circuit 260 is limited by the upper limit of the output voltage by securing the drain-source voltage V _{DS_P} of the PMOS transistors MP1 and MP2 (FIG. 1).

The second current source circuit 270 may include a second current source 240 including two NMOS transistors MN1 and MN2, a second switch circuit 245 including third and fourth switch transistors MN3 and MN4, and a third fourth resistor (R5) provided between the switching transistor (MN3) and the power supply voltage (V _DD) a third resistor (R4) formed between the fourth switching transistor (MN4) and the supply voltage (V _DD), A third node N3 connecting the third switch transistor MN3 and the third resistor R4, and a fourth node N4 connecting the fourth switch transistor MN4 and the fourth resistor R5. And a second voltage output terminal for outputting the voltage Vout2 between the third and fourth nodes N3 and N4 to the multiplexer 290. Third and fourth bias voltages VBM and VBN of the bias circuit 100 are applied to gates of two NMOS transistors MN1 and MN2 of the second current source circuit 270, respectively. In this case, a current equal to the reference current of the bias circuit 100 flows to the two NMOS transistors MN1 and MN2. The second current source circuit 270 may respond to the clock signals CK2 and CKB2 of the decoding logic 210 in the same manner as the first current source circuit 260 in the third and fourth nodes N3 and N4. The voltage Vout2 between is output to the multiplexer 290. In particular, the second current source circuit 270 has a current source 240 composed of NMOS transistors MN1 and MN2. Accordingly, the second output voltage Vout2 of the second current source circuit 270 is limited by the lower limit of the output voltage by securing the drain-source voltage V _{DS_N} of the NMOS transistors MN1 and MN2 (FIG. 2).

The decoding logic 210 controls clock signals for controlling the switch transistors MP3, MP4, MN3, and MN4 of the first and second current sources 235 and 245 as described above when digital data to be converted is input. In addition to CK1, CK1B, CK2, and CK2B, an output selection signal for discriminating which of the first output voltage Vout1 and the second output voltage Vout2 is output is generated.

The multiplexer 290 outputs one of a first output voltage Vout1 and a second output voltage Vout2 as an output voltage Vout in response to the output selection signal. At this time, the reference voltage for selecting one of the two voltages Vout1 and Vout2 is a voltage (V _DD / 2) whose potential is half of the power supply voltage (V _DD ), which is lower than the reference voltage (V _DD / 2). The first output voltage Vout1 is output when an analog voltage for digital data is output, and the second output voltage Vout2 is output when an analog voltage for digital data higher than the reference voltage V _DD / 2 is output. ) As a result, the output (Vout) range of the DAC according to the present invention is full swing (rail-to-rail) from the ground voltage to the power supply voltage level as shown in FIG. Therefore, it is possible to solve the problem that the width of the output voltage is limited by securing the drain-source voltages V _{DS_P} and V _{DS_N} of the PMOS or NMOS current source at a low voltage, and the signal-to-noise ratio can be obtained at a desired level.

8 is a circuit diagram showing an example for adjusting the output range of the DAC current source circuit according to the present invention. And Figure 4 shows the DAC output range adjusted by the circuit. Here, the hatched portion is the range of the output voltage.

The output range of the DAC 300 according to the present invention may have a range from the ground voltage GND to the power supply voltage V _DD level as described above, or may arbitrarily adjust the output range by adding a resistor. In order to adjust the output range of the DAC circuit 300, as shown in FIG. 8, a fifth resistor R6 may be configured between the first and second resistors R2 and R3 and the ground voltage GND. The sixth resistor R7 may be configured between the third and fourth resistors R4 and R5 and the power supply voltage V _DD . Referring to FIG. 4, the fifth resistor R6 adjusts the lower limit of the DAC output range, and the sixth resistor R7 adjusts the lower limit of the DAC output range. Therefore, the output (Vout) range of the DAC 300 according to the present invention may be a full swing (rail-to-rail) from the ground voltage to the power supply voltage level as shown in FIG. It may be adjusted to a desired range.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, the output range of the D / A converter at low voltage is improved to allow full swing from ground voltage to supply voltage level while maintaining a desired signal-to-noise ratio. You can.

Claims (4)

In the current source circuit of a digital to analog converter, A bias circuit for generating first to fourth bias voltages of the same level; A first current source circuit for generating a first output voltage in response to the first and second bias voltages and the first and second clock signals; A second current source circuit for generating a second output voltage in response to the third and fourth bias voltages and the third and fourth clock signals; When digital data to be converted is input, selecting a first clock signal, a second clock signal complementary to the first clock signal, a third clock signal, a fourth clock signal complementary to the third clock signal, and an output voltage Decoding logic for generating an output selection signal for the device; And In response to the output selection signal, one of the input first and second output voltages is selected and outputted, and a voltage level of which is lower than the reference voltage is applied to the digital data using a voltage corresponding to half of a power supply voltage as a reference voltage. And a multiplexer for outputting the first output voltage when outputting the analog voltage and outputting the second output voltage when outputting the analog voltage for the digital data higher than the reference voltage. Digital analog converter with improved output range. The method of claim 1, The first current source circuit, A first current source comprising two PMOS transistors receiving the first and second bias voltages at respective gates, the current paths being connected in series, and one end of the current path being connected to a power supply voltage; A first switch transistor comprising a PMOS transistor having a gate receiving the first clock signal, a source connected to a current path of the first current source, and a drain; A second switch transistor comprising a PMOS transistor having a gate receiving the second clock signal, a source connected to the current path of the first current, and a drain; A first resistor formed between the first switch transistor and a ground voltage; A second resistor formed between the second switch transistor and the ground voltage; A first node connecting the first switch transistor and the first resistor; A second node connecting the second switch transistor and the second resistor; And And a first voltage output stage for outputting a voltage between the first and second nodes as a first output voltage. The method of claim 1, The second current source circuit, A second current source comprising two NMOS transistors receiving the third and fourth bias voltages at respective gates, the current paths being connected in series, and one end of the current path connected to the ground voltage; A third switch transistor comprising a NMOS transistor having a gate receiving the fourth clock signal, a source connected to a current path of the second current source, and a drain; A fourth switch transistor comprising an NMOS transistor having a gate receiving the third clock signal, a source connected to the current path of the second current, and a drain; A third resistor formed between the third switch transistor and the power supply voltage; A fourth resistor formed between the fourth switch transistor and the power supply voltage; A third node connecting the third switch transistor and the third resistor; A fourth node connecting the fourth switch transistor and the fourth resistor; And And a second voltage output stage for outputting a voltage between the third and fourth nodes as a second output voltage. The method of claim 1, The output voltage range can be adjusted by connecting a resistor between the first and second resistors and the ground voltage, and between the third and fourth resistors and the power supply voltage, respectively, to improve the output range at low voltages. Digital to analog converter.

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