KR100571132B1 - An image processing circuit, an image display apparatus, and an image processing method - Google Patents

Abstract

  The present invention converts the input interlaced image data into progressive image data in the I / P conversion processing unit, and is converted in time series in the image processing unit with respect to image data converted in a progressive manner by the I / P conversion processing unit. Alternatively, image processing including spatial data comparison is performed.

Description

Image processing circuit, image display device, and image processing method {IMAGE PROCESSING CIRCUIT, IMAGE DISPLAY DEVICE, AND AN IMAGE PROCESSING METHOD}

Fig. 1 shows one embodiment of the present invention and is a block diagram showing a schematic configuration of an image processing circuit.

2 is an explanatory diagram showing a schematic configuration of a liquid crystal display panel in an image display device.

3 is a circuit diagram showing a pixel configuration of the liquid crystal display panel.

4 is an explanatory diagram showing I / P conversion processing in the image processing circuit.

5 is an explanatory diagram showing time-series data comparison by progressive signals.

6 is an explanatory diagram showing an example of undesirable I / P conversion processing in the image processing circuit.

7 is an explanatory diagram showing another example of undesirable I / P conversion processing in the image processing circuit.

8 is a block diagram showing an example of the configuration of the image processing circuit.

9 is a block diagram showing another example of the configuration of the image processing circuit.

FIG. 10 is a block diagram showing an example of a specific configuration of the image processing circuit in FIG.

FIG. 11 is a block diagram showing another example of the specific configuration of the image processing circuit in FIG.

12 is a block diagram showing still another example of the configuration of the image processing circuit.

Fig. 13 is a block diagram showing still another example of the configuration of the image processing circuit.

14 is a graph showing the relationship between transmittance and chromaticity change when white balance processing is performed.

Fig. 15 is a block diagram showing a schematic configuration of an image processing apparatus using the image processing circuit of the present invention.

Fig. 16 is a block diagram showing the structure of a conventional image processing circuit.

Fig. 17 is an explanatory diagram showing time series data comparison by interlaced signals.

18 is an explanatory diagram showing an example of reference data of a line calculated in the I / P conversion processing in the image processing circuit.

Fig. 19 is an explanatory diagram showing another example of the reference data of the line calculated in the I / P conversion processing in the image processing circuit.

20 is an explanatory diagram showing another example of the reference data of a line calculated in the I / P conversion processing in the image processing circuit.

FIG. 21 is a block diagram showing another example different from the configuration of FIG. 12 of the image processing circuit. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit, an image display apparatus, and an image processing method for receiving an input of image data in an interlace format and performing image processing including time-series or spatial data comparison with respect to the image data.

Background Art Conventionally, image data input to an image display device is often supplied to a display unit after various image processings are performed in order to obtain a better display quality in the display unit. Such image processing includes image processing according to overshoot driving, white balance correction processing, color correction processing, and the like.

Overshoot driving is a driving method for improving the response speed in the cumulatively responding liquid crystal panel. As the image processing according to the overshoot driving, the gradation value in the image data of the previous field and the gradation value in the image data of the current field are compared and applied to the liquid crystal pixels in the current field in response to the comparison result. The process of converting the voltage, that is, the density value in the image data of the current field, is performed. In other words, in the image processing according to the overshoot driving, data comparison with respect to image data of continuous fields in time series is included.

The white balance correction process is an image process for independently adjusting grayscale data of R (red), G (green), and B (blue) in response to the dielectric constant of the liquid crystal panel. That is, in the liquid crystal panel, when the transmittance of the pixel is changed, the balance of the RGB luminance is changed by wavelength dispersion, so it is necessary to correct this balance change by white balance correction. In the color display by the liquid crystal panel, since sub-pixels of R, G, and B colors are arranged in one color pixel, the system in these sub-pixels is processed in the white balance correction process. A comparison of the measures is necessary. That is, in the white balance correction process, data comparison of spatially continuous pixels is included.

The color correction processing is an image processing performed to avoid a defect in which a color different from that assumed by the supplier of the image is displayed by the device characteristic of the image display apparatus. In the color correction process, the RGB signal of each pixel is corrected and output without destroying the white balance. In the color correction process as well, comparison of the gradation values in sub-pixels arranged corresponding to the respective colors of R, G, and B is necessary, and data comparison of spatially continuous pixels is included. Further, in the color correction process, time series data comparison may be included.

In this manner, in image processing, there is a process requiring time-series or spatial data comparison of input image data, and the image processing circuit which performs time-series processing has a configuration as shown in FIG. 16, for example.

In the image processing circuit shown in Fig. 16, when image data is input, the image data is first branched into two or more (in the figure, into two), one is directly input to the image processing unit 101, and the other. One is stored in the memory 102 and input into the image processing unit 101 one field later.

That is, in the image processing circuit, image data directly input to the image processing unit 101 becomes data representing the current field, and image data input to the image processing unit 101 through the memory 102 indicates the previous field. It becomes In the image processing unit 101, the input image data of the current field and the image data of the previous field are compared, and as a result of the comparison, the image data of the current field is converted and output to the display unit.

On the other hand, as the image data input in the image display apparatus, interlace image data (hereinafter referred to as interlace signal) can be input. As for the interlace signal, as shown in Fig. 17, a signal in which data exists every other scanning line is input in each field image. In addition, in the image data of two consecutive fields, a line in which data exists is one line in the vertical direction. It is arrange | positioned so that it may shift gradually.

However, in an image processing circuit in which an interlace signal is input, when image processing requiring time series data comparison as described above is to be performed, as shown in Fig. 17, two consecutive fields (previous field and current field) are shown. Inconsistency in the comparison line in the image data of?

That is, when the signal of the Nth line in the current field is to be compared with the signal of the previous field, originally, the signal of the Nth line must also be used in the previous field. However, in the interlaced signal, the image data of two consecutive fields is shifted by one line in the vertical direction in the line where the data exists, so that when the data exists in the Nth line of the current field, the Nth line of the previous field is used. No data exists.

Therefore, in the image processing circuit to which the interlace signal is input, data comparison on the same line is impossible, and data comparison is performed between lines shifted by one line in the vertical direction. As a result, it becomes a factor which causes remarkable deterioration of display quality and a malfunction in display in some cases.

In addition, even in the case where the image processing circuit performs spatial data comparison, in the recent image processing apparatus, high definition and sharp display is required, and image processing for drawing the display capability of the image display apparatus to the limit is required.

Here, in a device having a high contrast like a CRT (Cathode-Ray Tube) and not following a color change due to gradation, the fineness can be improved by improving the signal precision (for example, 8 bit). However, in a device with relatively low color reproducibility such as an LCD (Liquid Crystal Display), simply correcting the color of one pixel irrespective of the surroundings breaks the balance in the entire image.

Therefore, in order to prevent such a problem, in image processing including spatial data comparison, such as white balance correction processing and color correction processing, between adjacent pixels (including those present on adjacent scanning lines). The color comparison at s should be performed to correct for the balance of the image.

However, in this case, when the image data input to the image processing circuit is an interlace signal, when comparing data between adjacent lines, some of the image data to be compared may not exist in the same field. For this reason, there exists a problem that the precision of image processing becomes low.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to improve the processing precision in performing image processing including time series or spatial comparison with respect to image data input in an interlaced manner. There is provided an image processing circuit, an image display apparatus, and an image processing method.

In the image processing circuit of the first aspect of the present invention, in order to solve the above problems, image processing of interlaced image data is input and image processing including time-series or spatial data comparison with respect to the image data is performed. In the circuit, image processing is performed on I / P conversion means for converting input interlaced image data into progressive image data, and image data converted in a progressive manner by the I / P conversion means. And image processing means, wherein the I / P conversion means creates and interpolates new data in each field of the interlaced image data, and converts the entire image data when converting the interlaced image data into progressive image data. The line to which data is interpolated by I / P conversion without changing the number of fields At least, data is given by an operation using data of one or a plurality of lines before and after the sub-scanning direction.

According to the above configuration, in performing image processing on image data input in an interlaced manner, the interlaced image data is converted into progressive image data by the I / P conversion means before the image processing by the image processing means. do. In other words, the image processing means performs image processing on the progressive image data.

Here, when the image processing in the image processing means includes time series data comparison, it is necessary to compare data of different lines of two consecutive field image data as in the case of performing image processing using an interlaced signal. none. Therefore, image degradation caused by comparing data of different lines can be prevented.

 When the image processing in the image processing means includes spatial data comparison, if the input image data is an interlace signal, when comparing data between adjacent lines, a part of the image data to be compared is the same field. It may not exist inside. In this case, the precision of image processing becomes low.

In contrast, according to the configuration of the present invention, even in image processing including spatial data comparison, by arranging the I / P conversion means at the previous stage of the image processing means, a progressive signal without missing data in the entire line can be obtained. Can be used for image processing. Therefore, the precision of image processing can be improved.

In the I / P conversion, the simplest method is a method in which two consecutive interlaced signals are superimposed to form a progressive signal of one field, or a previous line or a back line of a line where no data exists in the interlaced signal. Interpolation is made by copying data from adjacent lines as they are.

However, in the above method, the data already existing in the interlaced signal first input is used as it is. Therefore, no new data is created by the I / P conversion process. Therefore, the purpose of improving the accuracy of image processing cannot be achieved or the effect is small.

Therefore, in the I / P conversion means, the number of fields of all the image data in the conversion from interlaced image data to progressive image data by creating and interpolating new data in each field of interlaced image data. By not changing the shape, the line to which data is interpolated by the I / P conversion process is configured such that the data is provided by an operation using data of one or a plurality of lines before and after the sub-scanning direction. The effect of improving the precision of the processing can be reliably obtained.

In the image processing circuit according to the second aspect of the present invention, in order to solve the above problem, interlace image data is input, and in the image processing circuit which performs image processing on the image data, I / P conversion means for converting image data into progressive image data and image data converted in a progressive manner by the I / P conversion means, as image processing, perform image processing according to overshoot driving. And an image processing means.

According to the above configuration, in performing image processing according to overshoot driving on image data input in an interlaced manner, the image data of the interlaced system is converted by the I / P conversion means before the image processing by the image processing means. Is converted into image data. In other words, the image processing means performs image processing on the progressive image data.

In this case, since image processing due to overshoot driving includes time-series data comparison, image processing is performed on progressive image data, so that image processing using an interlaced signal is performed continuously. It is not necessary to compare data of different lines of image data of two fields. Therefore, image degradation caused by comparing data of different lines can be prevented.

In the image processing circuit according to the third aspect of the present invention, in order to solve the above problems, interlace image data is input, and in the image processing circuit which performs image processing on the image data, Color correction for correcting device characteristics of display means as image processing for I / P conversion means for converting image data into progressive image data and image data converted in progressive manner by said I / P conversion means. And image processing means for performing the processing.

According to the above configuration, in performing color correction processing on the image data input by the interlacing method, the interlaced image data is converted into progressive image data by the I / P conversion means before the image processing by the image processing means. Is converted. In other words, the image processing means performs image processing on the progressive image data.

Here, since the color correction processing for correcting the device characteristics of the display means mainly includes spatial data comparison, if the input image data is an interlace signal, when comparing data between adjacent lines, Some are not in the same field. Therefore, the precision of image processing becomes low.

On the other hand, when image processing is performed on progressive image data, since there is no missing data in all lines, the accuracy of image processing can be improved.                         

Further, the color correction process may include time-series data comparison, in which case image degradation caused by comparing data of different lines can be prevented.

In the image processing circuit according to the fourth aspect of the present invention, in order to solve the above problem, interlace image data is input, and in the image processing circuit which performs image processing on the image data, I / P conversion means for converting image data into progressive image data, and image processing means for performing white balance correction processing as image processing on image data converted in a progressive manner by the I / P conversion means. It is characterized by having a.

According to the above configuration, in performing the white balance correction process on the image data input by the interlace method, the interlace method image data is converted by the I / P conversion means before the image process by the image processing means. Is converted to. In other words, the image processing means performs image processing on the progressive image data.

Here, since the white balance correction process includes spatial data comparison, when the input image data is an interlace signal, when comparing data between adjacent lines, a part of the image data to be compared does not exist in the same field. . Therefore, the precision of image processing becomes low.

On the other hand, when image processing is performed on progressive image data, since there is no missing data in all lines, the accuracy of image processing can be improved.

Still other objects, features, and advantages of the present invention will be fully understood by the following description. Further advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.

An embodiment of the present invention will be described with reference to FIGS. 1 to 15 and 18 to 21 as follows.

In this embodiment, a case where overshoot driving is performed in a liquid crystal display device provided with a TFT (Thin Film Transister) liquid crystal panel will be described by way of example.

As shown in Fig. 2, the TFT liquid crystal panel 1 has a plurality of source bus lines 2 ... parallel to the screen longitudinal direction and the screen transversely so as to be orthogonal to the source bus lines 2 .... A plurality of scanning lines 3... Parallel to the direction are provided. Further, in the TFT liquid crystal panel 1, pixels 7 (see Fig. 3) are arranged through TFTs 6 (see Fig. 3), which are switching elements, corresponding to the intersections of the source bus lines and the scanning lines. . The source bus lines 2 ... are connected to the source driver 4 at the panel end, and the scan lines 3 ... are connected to the gate driver 5 at the panel end.

In the display of the TFT liquid crystal panel 1, by sequentially outputting the scanning signals one by one from the gate driver 5, TFTs (6) connected to the respective scanning lines (3) are scanned lines ( It turns on every 3) sequentially, and the source driver 4 writes the gradation voltage according to the gradation data to each pixel 7 corresponding to each scanning line 3. As shown in FIG.

The simple structure of each pixel 7 has the configuration as shown in Fig. 3, and when the TFT 6 is ON (gate ON), the data gray level voltage supplied to the source electrode of the TFT 6 is the drain of the TFT 6; It is applied to one electrode (pixel electrode) which comprises the pixel 7 via an electrode. The other electrode constituting the pixel 7 is a common electrode 8 common to all the pixels. By the voltage applied to the pixel 7, the liquid crystal responds to the luminance desired to be displayed.

The liquid crystal molecules of each pixel 7 change the direction of the liquid crystal molecule longitudinal axis direction (director) when voltage is applied by the dielectric anisotropy, and change the polarization direction of the light passing through the liquid crystal by the optical anisotropy. As a result, the amount of light passing through the liquid crystal is controlled, and gray scale expression of light is performed. At this time, the voltage value applied to each pixel is set for each gradation, and for each pixel of the liquid crystal panel 1, the voltage of the gradation to be displayed is applied for each frame through the TFT 6 to perform image display. .

Charge applied to each pixel 7 is maintained even after the TFT 6 is turned off. That is, until the gray voltage is applied again to the next frame, the charge at the time of applying the gray voltage is maintained.

However, in the application of the voltage at the change of the gradation luminance, electric charge is maintained in each pixel 7, but the voltage changes due to the change in the liquid crystal dielectric constant. That is, in the case of changing the gradation luminance, the direction of the liquid crystal molecule director is directed in the direction of displaying the gradation luminance of the previous frame. When a voltage corresponding to the new gray scale data is applied thereto, the direction of the liquid crystal molecules is changed by dielectric anisotropy, and the gray scale luminance is changed by the change of the optical characteristics.

In the case of nematic liquid crystals, the response speeds of liquid crystal molecules vary depending on the display mode, but are orders of several several milliseconds to several tens of ms and respond even after the TFT 6 is turned off. Here, since the liquid crystal molecules change their directions by the dielectric anisotropy, the dielectric constant of the liquid crystal inevitably changes and the capacitance between the electrodes changes.

When the dielectric constant of liquid crystal molecules between electrodes changes due to the change in the direction of the liquid crystal molecules, the voltage value due to the provided charges also changes within one frame. That is, even if the liquid crystal molecules themselves have a characteristic of responding within one frame, if a normal gray voltage is applied at the time of gray level change, the voltage changes within one frame. As a result, a gray scale luminance to be displayed cannot be obtained, and a cycle of about 3 frames is required. The change in the voltage caused by the change in the dielectric constant can be corrected by the driving which applies the voltage which adds the change of the dielectric constant of the liquid crystal, that is, the overshoot driving.

When the voltage value applied during the gradation change is applied by applying a voltage equal to the capacitance ratio of the gradation, the gradation voltage to be displayed after the liquid crystal responds (actually, the voltage value changes due to the response speed of the liquid crystal) do).

In the following, for the sake of simplicity, an example of overshoot driving in the case where it is assumed that the liquid crystal molecules hardly respond at the gate ON and the response of the liquid crystal molecules is completed within the frame period is described.

When gradation is 256, 0, 1, 2, ..., n, ..., m, ..., 255 gradation voltages during gradation are respectively V0, V1, V2, ..., Vn,. Let .., Vm, ..., V255 be. In addition, the capacitance between the electrodes of the pixel 7 in each gray level is set to C0, C1, C2, ..., Cn, ..., Cm, ..., C255.

If n gray is displayed in any pixel, the voltage between electrodes is Vn and the capacitance between electrodes is Cn. At this time, when m gradation is displayed in the next frame, the charge Q to be provided is

Q = Cm × Vm. . . (One)

to be. However, in this case, since the TFT 6 is turned off before the capacitance changes from Cn to Cm, the charge Q 'actually provided between the electrodes when the voltage Vm is applied is

Q '= Cn x Vm. . . (2)

(Assuming that the liquid crystal molecules hardly respond at the gate ON).

That is, the voltage V 'to be applied to the pixel 7 in order to have the charge Q necessary for the display of the m gray scale after the display of the n gray scale is

Q = Cn × V ′ = Cn × (Cm / Cn × Vm). . . (3) from this,

V '= Cm / Cn x Vm. . . (4)

Becomes

By applying this voltage V ', it is possible to reach the desired gradation within one frame even in all gradation changes. Therefore, overshoot driving is very effective for the improvement of the fast moving performance of liquid crystal.

In addition, from the above formula (4), it can be seen that in order to obtain this voltage V ', the gradation data of the current field must be compared with the gradation data of the previous field. As a comparison circuit for performing the comparison, a configuration using a lookup table, a configuration by an arithmetic processing circuit, or a circuit configuration in which the two are mixed are considered. In addition, the image data compared in the comparison circuit may be a signal displayed by the R (red), G (green), or B (blue) colorimeter, or the comparison degree in the signals represented by Y (luminance) and C (chromaticity). Is considered.

Next, the configuration of the image processing circuit according to the present embodiment is shown in FIG. The image processing circuit receives image data by an interlace signal, performs image processing on the image data, and performs an I / P (interlace / progressive) conversion processing unit (I / P conversion means) 11 and an image processing unit (image processing). Means (12). In addition, a P / I (progressive / interlaced) conversion processing unit 13 may be provided as necessary.

In the image processing circuit, before the image processing in the image processing unit 12 is performed on the input interlace signal, the I / P conversion processing unit 11 converts the interlaced signal into a progressive signal. As shown in Fig. 4, the I / P conversion is a process of interpolating data to a line where no data exists in an interlaced signal, and converting the data into a progressive signal without missing data in all lines.

In the image processing unit 12 to which the progressive signal is input, when performing image processing including time-series data comparison, data of different lines of two consecutive field image data as in the case of performing image processing using an interlaced signal The deterioration of the image caused by comparing can be prevented. This will be described below with reference to FIG. 5.

That is, in the interlaced signal, in the two consecutive fields (current field and previous field), for example, when data exists in the N, N + 2 and N + 4 lines of the current field, N + 1 and N + 3. There is no data on the line. On the other hand, in the previous field, on the contrary, data exists in N + 1 and N + 3 lines, and no data exists in N, N + 2 and N + 4 lines. For this reason, data comparison with respect to the same line cannot be performed in the current field and the previous field of the interlace signal. However, in the progressive signal, as shown in Fig. 5, since data exists in all lines of the current field and the previous field by data interpolation, it is possible to compare data with respect to the same line.

In addition, in the image processing unit 12, even when image processing including spatial data comparison is performed, it is preferable to perform image processing using more data based on the data interpolated by the I / P conversion process. It is possible. Therefore, the accuracy of image processing is improved.

However, various methods exist as the I / P conversion processing, and in the I / P conversion processing performed by the I / P conversion processing unit 11, not all of these methods are effective.

For example, the simplest method in the I / P conversion is a method of superimposing two consecutive interlaced signals (previous field and current field) as one field progressive signal (current field), as shown in FIG. Alternatively, as shown in Fig. 7, the interpolation is a method of copying and interpolating data of adjacent lines of a previous line or a next line of a line in which no data exists in an interlace signal. However, in the above method, the data already existing in the first interlaced signal is used as it is, and new data is not created by the I / P conversion process.

As the image processing performed in the I / P conversion processing unit 11, when the method shown in Figs. 6 and 7 is used, the purpose of improving the accuracy of the image processing cannot be achieved or the effect is small. This will be described below.

When the method shown in Fig. 6 is applied to the I / P conversion processing unit 11, it is possible to perform data comparison on the same line for two consecutive continuous field signals compared by the image processing unit 12. However, when the data to be compared here is considered to be an interlaced signal before conversion, comparison is performed on data that is substantially separated by two fields. That is, in this case, the comparison is performed on data having a distance on the time axis, which is a factor of deterioration in image quality.

In addition, when the method of Fig. 7 is applied in the I / P conversion processing unit 11, in the image processing unit 12, two fields of progressive signals are compared with each other on the same line. In reality, however, one piece of data to be compared by the image processing unit 12 is interpolation data obtained by copying data of adjacent lines before and after a line on which no data exists on the interlace signal. Therefore, substantially as in the case shown in Fig. 17, the data shifted by one line in the current field and the previous field are compared, which causes deterioration in image quality.

Therefore, in the I / P conversion processing unit 11 according to the present embodiment, the applied I / P conversion processing is converted from the interlaced signal to the progressive signal by creating and interpolating new data in each field of the interlaced signal. Does not change the number of fields. In addition, spatially, a line to which data is interpolated by the I / P conversion process is given data by an operation using data of a line before and after the sub-scanning direction (which may be one or more lines). In the data of the field displayed in the interlaced signal, each line in which data exists or each line in which no data exists is a line along the main scanning direction, that is, a scanning line. As for the line to which data is interpolated, interpolation data is computed using the data of the line before and behind a subscanning direction.
Here, the main scanning direction means the direction of the plurality of scan lines 3, that is, the transverse direction, and the sub scanning direction means the direction perpendicular to the main scanning direction, that is, the longitudinal direction.

In the example shown in Fig. 18, in order to interpolate data in N lines of the current field, data of two lines before and after the image data of the interlaced signal before I / P conversion (i.e., N-3, N-1, N). The interpolation data can be obtained by calculation using (+1, N + 3 line data).

However, the present invention is not limited to this, and if the calculation is performed using data of one or more lines in each of the front and rear directions of the line to which data is interpolated, the number of lines used for interpolation calculation of data is not limited. In addition, the number of lines used for interpolation of data may not necessarily correspond in the front-back direction of the line to which data is interpolated.

In addition, the I / P conversion processing unit 11 stores data of a field before the current field in a memory (in some methods, data up to several fields), and stores data of a plurality of fields consecutive in time series. In comparison, it is also possible to perform an I / P conversion process with higher precision than the movement compensation. Of course, the I / P conversion process may be performed only by spatial comparison (data comparison in the same field) without using a memory.

 In the I / P conversion processing unit 11, in addition to the spatial data comparison as described in FIG. 18, data comparison of a plurality of continuous fields is also performed, and I / P is higher in accuracy than that of the movement compensation. 19 and 20 show specific examples when the P conversion process is performed.

In the example shown in Fig. 19, N-3, N-1, N + in the image data of the interlaced signal before I / P conversion of the current field are similarly interpolated in order to interpolate data on the N lines of the current field. Interpolation data are obtained by calculation using data of 1, N + 3 lines and data of N-2, N, N + 2 lines of the previous field.

In the example of FIG. 19, in data interpolation during I / P conversion processing, data of the current field is used for spatial data comparison, and data of the previous field is also used for time series data comparison. However, as shown in Fig. 20, for the time series data comparison, the data of the backfield may also be used.

In the example shown in Fig. 20, in order to interpolate the data in the N lines of the current field, N-3, N-1, N + 1, in the image data of the interlace signal before I / P conversion of the current field. Interpolation data are obtained by calculation using data of N + 3 lines, data of N-2, N and N + 2 lines of the previous field, and data of N-2 and N + 2 lines of the later field.

In this way, when performing data comparison of a plurality of continuous fields in time series and performing I / P conversion processing including motion compensation, data of both the previous field and the after field must not be used for the current field to be interpolated. You don't have to. That is, as in the example of FIG. 19, time-series I / P conversion may be performed only by comparing data between the previous field and the current field.

19 and 20 show an example in which data for one field is used before and after the time axis direction of the current field with respect to the current field to be interpolated with data. However, the present invention is not limited to this, and data of a plurality of fields in each of front and rear of the time axis direction may be used.

In the calculation of interpolation data, data in the front and rear lines in the sub-scan direction of the line to which the data is interpolated, and data in the front and back fields in the time axis direction are used, but in actual calculations, these data may be extracted and used. It is possible. For example, as shown in Fig. 20, in the interpolation operation of the data of the N lines of the current field, the data of the lines N-2 and N + 2 of the rear field are used for the interpolation operation, but the data of the N lines of the rear field are used. It is also possible to extract and use.

The data processed by the image processing unit 12 may send out the progressive signal output from the image processing unit 12 to the image display apparatus as long as the image display apparatus can display the corresponding progressive signal.

However, the controller of the current video display device often only corresponds to an interlace signal. In this case, the progressive signal output from the image processing unit 12 is converted into an interlaced signal by the P / I conversion processing unit 13 and sent to the video display device.

Next, a specific example of the image processing circuit will be described below with reference to FIG. The image processing circuit shown in Fig. 8 includes a first I / P conversion processing unit (current field I / P conversion unit) 21, a second I / P conversion processing unit (previous field I / P conversion unit) 22, And an image processing unit 12. If necessary, the P / I conversion processing unit 13 may be provided.

The first I / P conversion processing unit 21 and the second I / P conversion processing unit 22 perform an I / P conversion process on the interlaced signal input as image data, convert the result into a progressive signal, and output the converted signal. The first I / P conversion processing unit 21 performs I / P conversion processing on the interlace signal of the current field, and the second I / P conversion processing unit 22 performs I / P conversion processing on the interlace signal of the previous field.

Here, in order to input the interlace signal of the previous field to the second I / P conversion processor 22, a field memory (not shown) is disposed in front of the second I / P conversion processor 22. FIG. The image data input to the image processing circuit is first divided into two. One is directly input to the first I / P conversion processing unit 21 to become image data of the current field. The other is stored in the memory once at the front end of the second I / P conversion processing section 22, and after one field delay is used as the image data of the previous field.

In the image processing circuit shown in Fig. 8, the first and second I / P conversion processing units 21 and 22 respectively perform I / P conversion processing on image data of the current field and the previous field, respectively. Do it. For this reason, it is possible to employ different I / P conversion processing methods in the first and second I / P conversion processing units 21 and 22, respectively.

As described above, the I / P conversion processing method includes a method of using a memory (method of performing time series comparison) and a method of not using a memory (method of not performing time series comparison). Therefore, in the image processing circuit, the following four configurations divided into the case of using a memory and the case of not using each of the first and second I / P conversion processing units 21 and 22 are considered.

(1) A configuration employing a method in which no memory is used for both the first and second I / P conversion processing units (21, 22).

② A configuration employing a method of using a memory for both the first and second I / P conversion processing units 21 and 22.

(3) A method in which a memory is used for the first I / P conversion processing unit 21 and a method in which no memory is used for the second I / P conversion processing unit 22 is adopted.

(4) A configuration in which the first I / P conversion processing unit 21 employs a method that does not use a memory, and the second I / P conversion processing unit 22 employs a method that uses a memory.

In the above structure, since neither of the first and second I / P conversion processing units 21 and 22 uses a memory, a low cost circuit can be expected. However, in each of the first and second I / P conversion processing units 21 and 22, the I / P conversion precision is low, and the image quality after the image processing in the image processing unit 12 is also the lowest.

On the contrary, in the above structure, since the I / P conversion precision becomes high in each of the first and second I / P conversion processing units 21 and 22, the image quality after the image processing in the image processing unit 12 is also increased. The highest. However, the use of a memory for both the first and second I / P conversion processing units 21 and 22 causes an increase in the cost of the circuit.

Next, the configuration of (3) or (4) is such that the memory is used only for one of the first and second I / P conversion processing units 21 and 22. Here, in the case where the image processing unit 12 performs image processing in particular by overshoot driving, the data comparison performed in the image processing unit 12 is mainly performed using the data of the current field, so that the information of the current field is accurate. Significant effect is obtained.

Therefore, in the overshoot drive circuit, the first I / P conversion processing unit 21 for the current field performs a high-precision I / P conversion process using a memory, and the second I / P conversion for the previous field. The processing unit 22 is the most preferable configuration because the configuration of 3, which omits the memory to reduce the cost, is obtained at a relatively low cost with high image quality improvement effect.

The structure of (4) is the same as the structure of (3) from the viewpoint of the circuit scale (similar to the cost effect), but does not improve the image quality effect when employed in the overshoot drive circuit.

As described above, the greatest improvement in image quality is the configuration in which the memory is used for both the first and second I / P conversion processing units 21 and 22. There is a problem of an increase in the cost of the circuit. Therefore, the memory is used for both the first and second I / P conversion processing units 21 and 22 to maximize the effect of improving the image quality, and at the same time, the first and second I / P conversion processing units 21 and 22 are used. It is also possible to share the memory to reduce the cost of the circuit. An image processing circuit having such a configuration will be described below with reference to FIG.

The image processing circuit of the configuration shown in Fig. 9 includes a first I / P conversion processing unit (current field I / P conversion unit) 21 'and a second I / P conversion processing unit (previous field I / P conversion unit) 22'. ) Is configured to perform I / P conversion processing using image data of a plurality of fields stored in the memory. Further, image data of a plurality of fields used in the I / P conversion process is stored in the shared memory (memory used for the I / P conversion process) 23.

The I / P conversion processing performed by the first I / P conversion processing unit 21 ', the second I / P conversion processing unit 22', and the shared memory 23 will be described below with reference to FIG. . 10 illustrates a case where I / P conversion processing is performed using image data of four fields together with the first I / P conversion processing unit 21 'and the second I / P conversion processing unit 22'. do.

In this case, when the image data of the N field is input, the first I / P conversion processing unit 21 'for the current field uses the data of the (N-3) to N field to perform the I / P conversion process. In the second I / P conversion processing section 22 'for the previous field, I / P conversion processing is performed using data in the (N-4) to (N-1) fields.

Therefore, in this case, the shared memory 23 must store image data of five fields from the (N-4) field to the N field. Therefore, the shared memory 23 has five field memories 23a to 23e. ). That is, in the configuration of FIG. 10, when each of the first I / P conversion processing unit 21 'and the second I / P conversion processing unit 22' performs I / P conversion processing using image data of m fields. The number of field memories can be m + 1 instead of 2 m. Therefore, the cost reduction by the memory reduction can be obtained.

In addition, in the configuration of Fig. 10, the image data is first inputted to the shared memory 23, but after inputted to the first I / P conversion processing section 21 'or the second I / P conversion processing section 22', The configuration may be written in the shared memory 23. When the next N + 1 field is input, the data is rewritten to the field memory in which the data of the N-4 field is stored.

11 is also considered as a modification of the configuration of FIG. In the configuration of Fig. 11, the first I / P conversion processing section 21 'performs I / P conversion processing using four fields of image data, while the second I / P conversion processing section 22' performs three fields. I / P conversion processing is performed using the image data.

In this case, when the image data of the N field is inputted, the first I / P conversion processing unit 21 'for the current field uses the data of the (N-3) to N field for I / P conversion processing. The second I / P conversion processing unit 22 'for the previous field is used to perform I / P conversion processing using the data of the (N-3) to (N-1) fields. However, in this case, the first I / P conversion processing unit 21 'and the second I / P conversion processing unit 22' always use all the data in the (N-3) to (N-1) fields for I / P conversion. There is no need to perform the P conversion process.

In other words, the first I / P conversion processing unit 21 'for the current field uses the data of the m field (m = 4 in the example of the first I / P conversion processing unit 21') to perform I / P conversion processing. Is performed, appropriate I / P conversion processing using data in the (m-1) field may not be possible by I / P conversion in the second I / P conversion processing section 22 '. In other words, the current IP conversion processing unit is a custom chip, and in particular, there are up to 8 types of IP conversions performed by field comparison. However, not all types of 1 to 8 fields are necessarily useful. For example, even if a conversion circuit for performing IP conversion with reference to 8 (= m) field is useful, the conversion circuit for performing IP conversion with reference to 7 (= m-1) field may not be useful.

In such a case, the same effect can be expected even if I / P conversion using data of a field of 1 or more (m-1) or less is used.

In this case, therefore, the shared memory 23 needs to store image data of four fields from the (N-3) field to the N field, so that the shared memory 23 has four field memories 23a to 23. 23d). That is, in the configuration of Fig. 11, by making the number of fields of data used for the I / P conversion processing of the second I / P conversion processing section 22 'one less than the first I / P conversion processing section 21', The memory of one field can be further reduced than the configuration of FIG.

In addition, as another modification of the configuration of FIG. 11, a configuration for sharing the I / P conversion processing unit is also considered. The configuration in this case is shown in FIG. In the configuration of FIG. 12, the second I / P conversion processing section 22 'is omitted in comparison with the configuration in FIG. 11, and the first I / P conversion processing section (current field I / P conversion section, previous field I / P conversion) is omitted. 21) is configured to output progressive signals of the previous field and the current field.

In the first I / P conversion processing unit 21 '', when performing I / P conversion processing using image data of a plurality of fields, the image data of the plurality of fields is the first I / P conversion processing unit 21. ") Need not be input at the same time, but is input sequentially from old data.

That is, as in the configuration of Fig. 11, when the I / P conversion process is performed using image data of 4 fields in the current field, and the I / P conversion process is performed using image data of 3 fields in the previous field, FIG. In the configuration of 12, first, when the interlace signal from the N-3 field to the N-1 field is inputted from the memory 23 to the first I / P conversion processing unit 21 ", the progressive signal of the previous field is calculated. Thereafter, the N-field interlace signal is inputted, and the progressive signal of the current field can be calculated and output.

In the configuration shown in Fig. 12, not only the cost saving effect by sharing the memory but also the circuit configuration of the image processing circuit by the sharing of the I / P conversion processing unit can be simplified. In this case, however, a time lag occurs in the image data of the current field and the previous field output from the first I / P conversion processing unit 21 ", so that a configuration for synchronizing them is required. A configuration as shown in FIG. 13 is considered as a configuration that does not induce a time delay in the image data of the previous field and also realizes sharing of the I / P conversion processing section.

In the configuration of Fig. 13, the image data input to the image processing circuit is first inputted to the I / P conversion processing section (current field I / P conversion section, previous field I / P conversion section) 24, and the interlace signal is separated from the interlace signal. Converted into a progressive signal. The progressive signal is branched after output from the I / P conversion processing section 24. One signal is directly input to the image processing unit 12 as data of the current field, but the other signal is once stored in the memory (data delay memory) 25 and the image processing unit is one field after the current field as data of the current field. It is input to (12).

In addition, in the configuration of Fig. 13, when the I / P conversion processing section 24 performs I / P conversion processing using m field image data, the I / P conversion processing section 24 uses the m field field memory. (Not shown) is provided. In addition, since the field memory of one field is used as the memory 25 for storing data of the previous field, the total number of field memories is m + 1. Therefore, the effect of cost reduction by reducing the memory becomes the same as that of FIG. However, in the configuration of FIG. 12, since the I / P conversion processing section 24 can be shared between the current field and the previous field, the circuit configuration of the image processing circuit is more simplified than the configuration of FIG.

As shown in Fig. 21, instead of the first I / P conversion processing section 21 'in Fig. 12, a dedicated (i.e., time-series comparison) studied to simultaneously output image data of the current field and the previous field. Dedicated) I / P conversion processing section 26 may be used. In the I / P conversion processing section 26, unlike the first I / P conversion processing section 21 'in Fig. 12, no time delay occurs in the image data of the current field and the previous field to be output. This eliminates the need for a configuration (i.e., the memory 25) as shown in Fig. 13 for synchronizing the image data of the current field and the previous field output from the I / P conversion processing section 26, thereby eliminating the need for the image processing circuit. The circuit configuration is further simplified.

In the above description, the image processing unit 12 performs an overshoot drive including time series data comparison. However, the image processing circuit of the present invention is not limited to this, and the white balance correction process including the spatial data comparison is performed. Can be applied to an image processing circuit which performs color correction processing.

In the liquid crystal panel, when the transmittance (gradation) of the display pixel is changed, the balance of the RGB luminance is changed by wavelength dispersion. Therefore, with respect to the change in transmittance, the white chromaticity coordinate shows the same change as the solid line in FIG. In addition, in FIG. 14, the vertical axis | shaft and the horizontal axis | shaft show chromaticity coordinates, and show the thing which connected the several plot with the line | wire while changing the transmittance | permeability from 10% to 100%. In Fig. 14, it can be seen that the chromaticity rises to the upper right side as the transmittance increases. That is, it can be seen that the display becomes yellow as the color becomes brighter.

However, it is preferable that the chromaticity coordinate does not change even if the transmittance is changed. Therefore, the white balance correction process is a process of adjusting the RGB luminance balance independently so as to control the RGB gradation voltage corresponding to the transmittance so as not to change the chromaticity coordinate.

In the case of performing the white balance correction processing (WB correction processing), even when the transmittance (gradation) of the display pixel is changed as shown by the broken line in Fig. 14, the change in chromaticity coordinates hardly occurs.

In the color display by the liquid crystal panel, since subpixels of each of the R, G, and B colors are arranged in one color pixel, comparison of the gradation values in these subpixels is necessary in the white balance correction process. However, in the liquid crystal panel, if the color of a single color pixel is corrected irrespective of the surrounding color pixels, the balance in the entire image can be broken. Therefore, in order to display a higher definition and clearer display, it is necessary to perform color comparison between adjacent color pixels (including those present on adjacent scanning lines) and perform white balance correction in consideration of image balance. .

  In this way, even when the image processing circuit performs white balance correction processing by spatial data comparison, when the image data input to the image processing circuit is an interlace signal, when comparing data between adjacent lines, the comparison is performed. Some of the image data to be used may not exist in the same field. In this case, the precision of image processing becomes low.

In contrast, in the image processing circuit of the present invention, by performing I / P conversion processing before the image processing unit performs the white balance correction process, the image processing unit can use a progressive signal without missing data. As a result, the precision of the white balance correction process can be improved.

In addition, in a typical image display apparatus, the color reproduction range of the image display is often different from the color reproduction range assumed by the transmitter of the image due to device characteristics. When the image is displayed by such an image display device, a color different from the color assumed by the transmitter is displayed.

The color correction process is a process for solving the above problem, and in the color correction process, an RGB signal having corrected device characteristics can be output without destroying the white balance with reference to the RGB signal of each pixel. Of course, since the color reproduction range of the image display apparatus does not change even when the color correction process is performed, only the correction is made within the color reproduction range of the image display apparatus. That is, although there is no effect on colors other than the reproduction range of an image display apparatus, it is possible to reproduce colors close to the color assumed by the sender for the colors within that range.

In the color correction process as well, comparison of the gradation values in sub-pixels arranged corresponding to each of the R, G, and B colors is necessary, and data comparison of spatially continuous pixels is included (in the color correction process, time series Data comparisons may be included). However, even in the color correction processing described above, if the color of one simple color pixel is corrected irrespective of the surrounding color pixels, the balance in the entire image can be broken down. Therefore, in order to perform high definition and clear display, color comparison between adjacent color pixels (including those present on adjacent scanning lines) must be performed and color correction in consideration of the balance of the image must be performed.

For this reason, when the image data input to the image processing circuit is an interlace signal, when comparing data between adjacent lines, some of the image data to be compared may not exist in the same field. In this case, the precision of image processing becomes low.

Therefore, by applying the present invention also in the color correction process, by performing the I / P conversion process before performing the color correction process in the image processing unit, it is possible to use a progressive signal without missing data in the image processing unit. . As a result, the accuracy of the color correction process can be improved.

Next, the effect of the image processing apparatus equipped with the image processing circuit which applied this invention in front of a liquid crystal display (LCD) controller was investigated using the commercially available liquid crystal display device. The configuration of the image processing apparatus is shown in FIG. In the configuration of Fig. 15, the input circuit 31, the I / P conversion circuit 32, the white balance processing circuit 33, the overshoot driving circuit (OS driving circuit) 34, and the P / I conversion circuit 35 LCD controller 36 is provided. In this case, the I / P conversion circuit 32 corresponds to the I / P conversion means, and the white balance processing circuit 33 and the overshoot driving circuit 34 correspond to the image processing means.

In order to confirm the display performance of the liquid crystal display device, the I / P conversion circuit 32, the white balance processing circuit 33, the overshoot driving circuit 34, and the P / I conversion circuit in the configuration of FIG. As a result of comparing the display characteristics of the conventional configuration using the image processing apparatus omitting (35) and the configuration of the present invention using the image processing apparatus of the configuration shown in Fig. 15, the response speed is fast, A liquid crystal display device excellent in moving pictures and having a small color change due to gradation was obtained.

In order to solve the above problems, the image processing circuit of the first aspect of the present invention is an image processing circuit in which interlaced image data is input and performs image processing including time-series or spatial data comparison with respect to the image data. An I / P conversion means for converting input interlaced image data into progressive image data, and an image for performing image processing on the image data converted in a progressive manner by the I / P conversion means. And a processing means, wherein said I / P conversion means creates and interpolates new data in each field of interlaced image data, thereby converting the entire image upon conversion from interlaced image data to progressive image data. Line to which data is interpolated by I / P conversion without changing the number of fields of data Is characterized in that data is provided at least by a calculation using data of one or a plurality of lines before and after the sub-scanning direction.

In the image processing circuit of the first configuration, the image processing means performs image processing including time series data comparison, and the I / P conversion means interpolates data by I / P conversion processing. Interpolation is performed on a line by operation using data of one or more lines before and after the sub-scan direction of the line to which data is interpolated, and data of one or more fields before and after the field including the line from which data is interpolated. It may be a configuration for providing data.

According to the above configuration, the line to which data is interpolated by the I / P conversion process is further included before and after the field including data of one or more lines before and after the sub-scan direction of the line, and the line to which the data is interpolated. Provided by an operation using data in one or more fields of. For this reason, in the I / P conversion process, not only spatial comparison (data comparison in the same field) but also highly accurate I by comparing the data of a plurality of continuous fields in time series and performing movement correction. / P conversion can be performed. Thus, more improved precision of image processing can be obtained.

In the calculation of interpolation data, when using data of one or a plurality of fields before and after a field including a line to which data is interpolated, it is necessary to use both the data of the previous field and the data of the after field. You can use only the data in the previous field.

In order to solve the above problem, the image processing circuit of the second aspect of the present invention is provided with an interlaced image data, and an image processing circuit which performs image processing on the image data. 1 / P conversion means for converting image data into progressive image data, and an image process for performing image processing according to overshoot driving as image processing to image data converted in a progressive manner by the I / P conversion means. A processing means is provided.

In order to solve the above problem, the image processing circuit of the third configuration of the present invention is provided with an interlaced image data, and an image processing circuit which performs image processing on the image data. 1 / P conversion means for converting image data into progressive image data, and color correction for correcting device characteristics of display means as image processing for image data converted in a progressive manner by the I / P conversion means. And image processing means for performing the processing.

In order to solve the above problem, the image processing circuit according to the fourth aspect of the present invention is provided with an interlaced image data, and an image processing circuit for performing image processing on the image data. I / P conversion means for converting image data into progressive image data, and image processing means for performing white balance correction processing as image processing for image data converted in a progressive manner by said I / P conversion means. It is characterized by being provided.

In the image processing circuits of the first to third configurations, the image processing means performs image processing including time series data comparison, and the I / P conversion means performs I / P conversion on image data of the current field. The current field I / P converter which performs processing and the previous field I / P converter which performs I / P conversion with respect to the image data of the previous field may be provided separately.

According to the above configuration, I / P conversion processing is separately performed on the image data of the current field, which is the latest image data input to the image processing circuit, and the image data of the previous field, which is image data one field before the image data of the current field. . Thereby, image data of two consecutive fields (i.e., image data of the current field and the previous field) used in the time series data comparison by the image processing means can be obtained.

In the image processing circuit, the I / P conversion means is configured to perform I / P conversion processing including time series data comparison in both the current field I / P converter and the previous field I / P converter. Can be.

According to the above configuration, an I / P conversion process with high accuracy of motion compensation can be performed in both the current field I / P converter and the previous field I / P converter, and the image in the image processing means using the result is used. Processing accuracy is also high.

Further, in the image processing circuit, the I / P conversion means performs I / P conversion processing that does not include time series data comparison in both the current field I / P converter and the previous field I / P converter. Can be.

According to the above configuration, since both the current field I / P conversion unit and the previous field I / P conversion unit do not include time series data comparison in the I / P conversion processing, In comparison, the memory used for data comparison becomes unnecessary. Therefore, the cost of the circuit can be reduced.

Further, in the image processing circuit, the I / P conversion unit performs l / P conversion processing including time series data comparison in the current field I / P conversion unit, and time-series data in the previous field I / P conversion unit. It may be a configuration for performing I / P conversion processing without including a comparison.

With the above configuration, since one of the current field I / P conversion unit and the previous field I / P conversion unit performs I / P conversion processing including data comparison, the cost is lower than in the case of including data comparison in both. In addition, it is expected that the image processing accuracy will be improved as compared with the case where both data comparisons are not included.

In particular, in overshoot driving, since the image processing in the image processing means has a greater influence on the precision of the image data of the current field than the image data of the previous field, the time-series data comparison in the current field I / P converter is performed. Performing I / P conversion processing including the above becomes effective for improving the accuracy of the image processing.

 In the image processing circuit, it is preferable that the I / P converting means share a memory used for the I / P converting process in the current field I / P converting section and the previous field I / P converting section.

According to the above configuration, when the I / P conversion processing including time series data comparison is performed in both the current field I / P converter and the previous field I / P converter, the current field I / P converter and the previous field I / P are performed. There is a need for a memory for storing the image data first inputted by the P converter until use for data comparison. At this time, since some of the data used for the I / P conversion processing of the current field I / P conversion unit and the previous field I / P conversion unit are common, the cost of the circuit can be reduced by sharing the memory for storing the data. Can be.

Further, in the image processing circuit, the I / P conversion means performs I / P conversion processing using data of m fields in the current field I / P conversion section, and at least one (m) in the previous field I / P conversion section. -1) It is preferable to perform I / P conversion processing using data of the following fields.

According to the above configuration, the data used for the I / P conversion processing of the previous field I / P converter is completely included in the data used in the I / P conversion processing of the current field I / P converter. As a result, the use of memory used for time series data comparison can be minimized, and the circuit cost can be reduced.

However, a preferable I / P conversion process using data of the (m-1) field may not be effective under any situation of I / P conversion. In that case, the same effect can be expected even when I / P conversion using data of a field of one or more (m-1) or less is used.

Further, in the image processing circuit, the image processing means performs image processing including time series data comparison, and the progressive signal converted by the I / P conversion means is subjected to image processing before input to the image processing means. The image data of the current field directly inputted to the means, and the image data of the previous field, which is once stored in the data delay memory and inputted to the image processing means one field later with respect to the image data of the current field, may be divided.

According to the above arrangement, since the I / P conversion processing for the image data of the current field and the I / P conversion processing for the image data of the previous field are performed by the same I / P conversion means, the cost of sharing the memory In addition to the saving effect, the circuit configuration of the image processing circuit is simplified.

Further, in the image processing circuit, the image processing means performs image processing including time series data comparison, and the I / P conversion means uses image data of the current field using one or a plurality of fields of data. And image data of the previous field and simultaneously output the image data of the previous field and the current field to which the interpolation data is added to the image processing means of the next stage.

According to the above arrangement, the I / P conversion processing for the image data of the current field and the I / P conversion processing for the image of the previous field are performed by the same I / P conversion means, and further, by the I / P conversion means. The image data of the created previous (interpolated data) and the current field is output simultaneously to the image processing means at the later stage. That is, no time delay occurs in the input of the image data of the previous field and the current field used for the image processing in the image processing means.

Therefore, since the memory for data delay for synchronizing the input of the image data of the previous field and the current field is not required for the image processing means, the circuit configuration diagram of the image processing circuit is added in addition to the effect of reducing the cost of the memory. It can be simplified.

The specific examples in the detailed description of the invention are intended to clarify the technical details of the present invention to the last, and are not to be construed as limited to such specific examples only, but within the spirit of the present invention and the claims set forth below. You can do this in a variety of ways.

The present invention provides an image processing circuit, an image display apparatus, and an image processing capable of improving processing accuracy in performing image processing including time-series or spatial comparison with respect to image data input in an interlaced manner. It may provide a method.

Claims (45)

An image processing circuit which inputs interlace image data and performs image processing including time-series or spatial data comparison with respect to the image data. I / P conversion means for converting input interlaced image data into progressive image data; And Image processing means for performing image processing including time-series data comparison on image data converted in a progressive manner by the I / P conversion means; The I / P converting means includes a current field I / P converting unit that performs I / P conversion processing on image data of a current field, and a previous field I / P performing I / P conversion processing on image data of a previous field. I have a conversion part separately, The current field I / P converting unit and the previous field I / P converting unit generate and interpolate new data in each field of the interlaced image data using the image data of a plurality of fields stored in a shared memory, thereby At the time of conversion from image data to progressive image data, the number of fields of all the image data is not changed, and the line to which data is interpolated by the I / P conversion process is at least one before or after the sub-scan direction. An image processing circuit, wherein data is provided by an operation using data of a plurality of lines. The data of one or a plurality of lines before and after the sub-scanning direction of the line to which data is interpolated, with respect to the line to which data is interpolated by I / P conversion processing, An image processing circuit for providing interpolation data by calculation using data of one or a plurality of fields before and after a field including a line to which data is interpolated. In an image processing circuit for inputting interlaced image data and performing image processing on the image data, I / P conversion means for converting the input interlace image data into progressive image data; And And image processing means for performing image processing according to overshoot driving as image processing on image data converted in a progressive manner by said I / P conversion means. In an image processing circuit for inputting interlaced image data and performing image processing on the image data, A current field I / P conversion section for performing I / P conversion processing on the image data of the current field and a previous field I / P conversion section performing I / P conversion processing on the image data of the previous field; An I / P conversion for converting the input interlaced image data into progressive image data using the image data of a plurality of fields stored in a shared memory, wherein the current field I / P converter and the previous field I / P converter Way; And Image processing means for performing image processing including time series data comparison and color correction processing for correcting device characteristics of display means as image processing on image data converted in a progressive manner by the I / P conversion means. An image processing circuit. An image processing circuit which inputs interlace image data and performs image processing on the image data; A current field I / P conversion section for performing I / P conversion processing on the image data of the current field and a previous field I / P conversion section performing I / P conversion processing on the image data of the previous field; The current field I / P conversion unit and the previous field I / P conversion unit convert the interlaced image data input using image data of a plurality of fields stored in a shared memory into progressive image data. Way; And And image processing means for performing image processing including time series data comparison and white balance correction processing on image data converted in a progressive manner by the I / P conversion means. delete 4. The image processing apparatus according to claim 3, wherein said image processing means performs image processing including time series data comparison, The I / P converting means includes: a current field I / P converting section which performs I / P converting processing on image data of a current field; And a previous field I / P conversion section that performs I / P conversion processing on the image data of the previous field. delete The image processing circuit according to claim 1, wherein the I / P conversion means performs I / P conversion processing including time series data comparison in both the current field I / P converter and the previous field I / P converter. . 8. The image processing circuit according to claim 7, wherein said I / P conversion means performs I / P conversion processing including time series data comparison in both the current field I / P converter and the previous field I / P converter. . 6. The I / P conversion unit according to claim 4 or 5, wherein the I / P conversion unit performs I / P conversion processing including time series data comparison in both the current field I / P conversion unit and the previous field I / P conversion unit. Image processing circuit. The image processing according to claim 1, wherein the I / P conversion means performs I / P conversion processing that does not include time series data comparison in both the current field I / P converter and the previous field I / P converter. Circuit. 8. The image processing according to claim 7, wherein the I / P conversion means performs I / P conversion processing that does not include time series data comparison in both the current field I / P converter and the previous field I / P converter. Circuit. 6. The I / P converting means according to claim 4 or 5, wherein the I / P converting means performs I / P converting processing that does not include time series data comparison in both the current field I / P converting unit and the previous field I / P converting unit. An image processing circuit. 2. The I / P conversion unit of claim 1, wherein the I / P conversion unit performs an I / P conversion process including time series data comparison in the current field I / P conversion unit, and performs time series data comparison in the previous field I / P conversion unit. An image processing circuit which performs I / P conversion processing not included. 8. The I / P conversion unit of claim 7, wherein the I / P conversion unit performs an I / P conversion process including time series data comparison in the current field I / P conversion unit, and performs time series data comparison in the previous field I / P conversion unit. An image processing circuit which performs I / P conversion processing not included. 6. The I / P converting means according to claim 4 or 5, wherein the I / P converting means performs an I / P converting process including time series data comparison in the current field I / P converting section, and performs a time series in the previous field I / P converting section. An image processing circuit which performs I / P conversion processing that does not include a normal data comparison. 10. The image processing circuit according to claim 9, wherein the I / P converting means shares a memory used for the I / P converting process in the current field I / P converting section and the previous field I / P converting section. The image processing circuit according to claim 10, wherein the I / P converting means shares a memory used for the I / P converting process in the current field I / P converting section and the previous field I / P converting section. The image processing circuit according to claim 11, wherein the I / P converting means shares a memory used for the I / P converting process in the current field I / P converting section and the previous field I / P converting section. 19. The I / P conversion unit according to claim 18, wherein the I / P conversion unit performs I / P conversion processing using data for m fields in the current field I / P conversion unit, and at least one (m−) in the previous field I / P conversion unit. 1) An image processing circuit which performs I / P conversion processing using data for the following fields. 20. The I / P conversion unit according to claim 19, wherein the I / P conversion unit performs I / P conversion processing using data for m fields in the current field I / P conversion unit, and at least one (m−) in the previous field I / P conversion unit. 1) An image processing circuit which performs I / P conversion processing using data for the following fields. 21. The I / P conversion unit according to claim 20, wherein the I / P conversion unit performs I / P conversion processing using data for m fields in the current field I / P conversion unit, and at least one (m−) in the previous field I / P conversion unit. 1) An image processing circuit which performs I / P conversion processing using data for the following fields. 2. The image processing apparatus according to claim 1, wherein the image processing means performs image processing including time series data comparison, The progressive signal converted by the I / P converting means is stored in the image data of the current field directly input to the image processing means and the data delay memory once before being input to the image processing means. An image processing circuit branched to image data of a previous field input to the image processing means after being delayed by one field. 4. The image processing apparatus according to claim 3, wherein said image processing means performs image processing including time series data comparison, The progressive signal converted by the I / P conversion means includes: image data of a current field which is directly input to the image processing means before input to the image processing means; And an image processing circuit which is once stored in the data delay memory and branched to the image data of the previous field inputted to the image processing means after being delayed by one field with respect to the image data of the current field. 5. The image processing apparatus according to claim 4, wherein the image processing means performs image processing including time series data comparison, The progressive signal converted by the I / P conversion means includes: image data of a current field which is directly input to the image processing means before input to the image processing means; And an image processing circuit which is once stored in the data delay memory and is branched to the image data of the previous field inputted to the picture processing means after being delayed by one field with respect to the image data of the current field. 2. The image processing apparatus according to claim 1, wherein the image processing means performs image processing including time series data comparison, The I / P converting means creates image data of the current field and image data of the previous field by using data for one or a plurality of fields, and rearwards the image data of the previous field and the current field to which interpolation data is added. And an image processing circuit which outputs simultaneously to the image processing means. 4. The image processing apparatus according to claim 3, wherein said image processing means performs image processing including time series data comparison, The I / P converting means creates image data of the current field and image data of the previous field by using data for one or a plurality of fields, and rearwards the image data of the previous field and the current field to which interpolation data is added. And an image processing circuit which outputs simultaneously to the image processing means. 5. The image processing apparatus according to claim 4, wherein the image processing means performs image processing including time series data comparison, The I / P converting means generates image data of the current field and image data of the previous field by using data for one or a plurality of fields, and converts image data of the previous field and the current field to which interpolation data is added. An image processing circuit which outputs simultaneously to the image processing means at a later stage. 4. The method according to claim 3, wherein the I / P converting means generates new data in each field of the interlaced image data and interpolates, thereby converting the entire image data upon conversion from the interlaced image data to the progressive image data. The image processing circuit, in which data is interpolated by the I / P conversion process without changing the number of fields, is provided with data at least by calculation using data of one or a plurality of lines before and after the sub-scanning direction. . 5. The method according to claim 4, wherein the I / P converting means generates new data in each field of the interlaced image data and interpolates the entire image data upon conversion from the interlaced image data to the progressive image data. The image processing circuit, in which data is interpolated by the I / P conversion process without changing the number of fields, is provided with data at least by calculation using data of one or a plurality of lines before and after the sub-scanning direction. . 6. The method according to claim 5, wherein the I / P converting means generates new data in each field of the interlaced image data and interpolates, thereby converting all the image data upon conversion from the interlaced image data to the progressive image data. The image processing circuit, in which data is interpolated by the I / P conversion process without changing the number of fields, is provided with data at least by calculation using data of one or a plurality of lines before and after the sub-scanning direction. . 31. The apparatus according to claim 30, wherein the I / P conversion means comprises: one or more lines of data before and after the sub-scanning direction of the line to which data is interpolated, with respect to the line to which data is interpolated by the I / P conversion process; And interpolation data by an operation using data of one or a plurality of fields before and after a field including a line to which data is interpolated. 32. The apparatus according to claim 31, wherein the I / P conversion means comprises: one or more lines of data before and after the sub-scanning direction of the line to which data is interpolated with respect to the line to which data is interpolated by the I / P conversion process; And interpolation data by an operation using data of one or a plurality of fields before and after a field including a line to which data is interpolated. 33. The apparatus according to claim 32, wherein the I / P conversion means comprises: one or a plurality of lines of data before and after the sub-scanning direction of the line to which data is interpolated with respect to the line to which data is interpolated by the I / P conversion process; And an interpolation data provided by an operation using data of one or a plurality of fields before and after a field including a line to which data is interpolated. An image display apparatus comprising the image processing circuit according to claim 1. 37. The apparatus according to claim 36, wherein the I / P conversion means comprises: one or a plurality of lines of data before and after the sub-scanning direction of the line to which data is interpolated with respect to the line to which data is interpolated by the I / P conversion process; And interpolation data by an operation using data of one or a plurality of fields before and after a field including a line to which data is interpolated. An image display apparatus comprising the image processing circuit according to claim 3. An image display apparatus comprising the image processing circuit according to claim 4. An image display apparatus comprising the image processing circuit according to claim 5. An image processing method for performing image processing including time-series or spatial data comparison with respect to interlaced image data, An I / P conversion step of converting interlaced image data into progressive image data; And An image processing step of performing image processing including time-series data comparison on image data converted in a progressive manner by the I / P conversion step; The I / P conversion step includes a current field I / P conversion unit that performs I / P conversion on the image data of the current field, and a previous field I / P that performs I / P conversion on the image data of the previous field. A conversion unit is provided separately, and the current field I / P conversion unit and the previous field I / P conversion unit create new data in each field of the interlaced image data using image data of a plurality of fields stored in a shared memory. By interpolating the data, the number of fields of all the image data is not changed at the time of conversion from the interlaced image data to the progressive image data, and the lines to which data is interpolated by the I / P conversion process are at least not included. An image processing method in which data is provided by calculation using data of one or a plurality of lines before and after the scanning direction. The data of one or more lines according to claim 41, wherein the I / P conversion step includes one or more lines of data before and after the sub-scanning direction of the line to which data is interpolated with respect to the line to which data is interpolated by the I / P conversion process, and An interpolation data is provided by a calculation using data of one or a plurality of fields before and after a field including a line to which data is interpolated. An image processing method of performing image processing on interlaced image data, An I / P conversion step of converting interlaced image data into progressive image data; And And an image processing step of performing image processing according to overshoot driving as image processing on image data converted in a progressive manner by the I / P conversion step. An image processing method of performing image processing on interlaced image data, A current field I / P conversion section for performing I / P conversion processing on the image data of the current field and a previous field I / P conversion section performing I / P conversion processing on the image data of the previous field; An I / P conversion step of converting the interlaced image data into progressive image data using image data of a plurality of fields stored in the shared memory, in the current field I / P converter and the previous field I / P converter; And An image processing step of performing image processing including time series data comparison and color correction processing for correcting device characteristics of display means as image processing on image data converted in a progressive manner by the I / P conversion process. An image processing method. An image processing method of performing image processing on interlaced image data, A current field I / P conversion section for performing I / P conversion processing on the image data of the current field and a previous field I / P conversion section performing I / P conversion processing on the image data of the previous field; An I / P conversion step of converting the interlaced image data into progressive image data using image data of a plurality of fields stored in the shared memory, in the current field I / P converter and the previous field I / P converter; And And an image processing step of performing image processing including time series data comparison and white balance correction processing on the image data converted in a progressive manner by the I / P conversion step.

Images