KR100570203B1 - Gate electrode formation method - Google Patents
Gate electrode formation method Download PDFInfo
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- KR100570203B1 KR100570203B1 KR1019980062507A KR19980062507A KR100570203B1 KR 100570203 B1 KR100570203 B1 KR 100570203B1 KR 1019980062507 A KR1019980062507 A KR 1019980062507A KR 19980062507 A KR19980062507 A KR 19980062507A KR 100570203 B1 KR100570203 B1 KR 100570203B1
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- polysilicon layer
- lower polysilicon
- layer
- gate electrode
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 229920005591 polysilicon Polymers 0.000 claims abstract description 63
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 238000004140 cleaning Methods 0.000 claims description 11
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000000779 depleting effect Effects 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 5
- 238000010030 laminating Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 229910021642 ultra pure water Inorganic materials 0.000 description 2
- 239000012498 ultrapure water Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 206010067484 Adverse reaction Diseases 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000006838 adverse reaction Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
본 발명은 소자분리막에 관한 것으로서, 특히, 반도체기판상에 소자분리막을 형성한 후 게이트산화막 및 하부폴리실리콘층을 순차적으로 적층하고, 상기 하부폴리실리콘층 상에 형성되어 있는 자연산화막을 불산계 케미칼로 제거한 후 하부폴리실리콘층의 표면을 친수성으로 만들고, 하부실리콘층에 As가 포함된 이온을 주입하여 상부표면을 비정질화하고, 하부폴리실리콘층 상에 텅스텐실리사이드층 및 상부폴리실리콘층을 순차적으로 적층한 후 식각으로 게이트전극을 형성하여, 텅스텐실리사이드층을 적층한면서 발생되는 결함을 방지할 뿐만 아니라 후속 열공정에서 하부폴리실리콘층에 포함된 인이 텅스텐실리사이드층으로 이동하는 것을 방지하여 하부폴리실리콘층이 공핍층화되는 것을 방지하도록 하는 매우 유용하고 효과적인 발명이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation film, and in particular, after forming a device isolation film on a semiconductor substrate, a gate oxide film and a lower polysilicon layer are sequentially stacked, and a natural oxide film formed on the lower polysilicon layer is fluorinated-based chemical. After removal, the surface of the lower polysilicon layer is made hydrophilic, and the upper surface is amorphous by implanting ions containing As into the lower silicon layer, and the tungsten silicide layer and the upper polysilicon layer are sequentially formed on the lower polysilicon layer. By forming a gate electrode by etching after lamination, it is possible to prevent defects caused by stacking the tungsten silicide layer and to prevent the phosphorus contained in the lower polysilicon layer from moving to the tungsten silicide layer in a subsequent thermal process. It is a very useful and effective invention to prevent the silicon layer from depleting.
Description
본 발명은 게이트전극을 형성하는 방법에 관한 것으로서, 특히, 반도체기판에 STI공정으로 소자분리막을 형성하고, 그 위에 게이트산화막 및 하부폴리실리콘층을 형성한 후 하부폴리실리콘층 상에 불산계 케미칼로 자연산화막을 제거하고 표면을 친수성이 되도록 한 후, 하부실리콘층에 As가 포함된 이온을 주입하여 상부표면을 비정질화하여, 텅스텐실리사이드층을 적층할때 발생되는 결함을 방지하도록 하는 게이트전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode. In particular, a device isolation film is formed on a semiconductor substrate by an STI process, a gate oxide film and a lower polysilicon layer are formed thereon, and then a fluorine-based chemical is formed on the lower polysilicon layer. After removing the natural oxide film and making the surface hydrophilic, implanting ions containing As into the lower silicon layer to make the upper surface amorphous, thereby preventing defects occurring when the tungsten silicide layer is laminated. It is about.
일반적으로, 반도체기판 상에 트랜지스터와 커패시터등을 형성하기 위하여 반도체기판에는 전기적으로 통전이 가능한 활성영역(Active Region)과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역(Isolation region)을 형성하게 된다. In general, in order to form transistors and capacitors on a semiconductor substrate, an isolation region is formed in the semiconductor substrate to prevent electrical conduction with an electrically energized active region and to separate devices from each other. Will form.
이와 같이, 반도체기판에 일정한 깊이를 갖는 트렌치(Trench)를 형성하고서 이 트렌치에 산화막을 증착키고서 화학기계적연마(Chemical Mechanical Polishing)공정으로 이 산화막의 불필요한 부분을 식각하므로 소자분리영역을 반도체기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다. As such, a trench having a predetermined depth is formed in the semiconductor substrate, an oxide film is deposited on the trench, and an unnecessary portion of the oxide film is etched by a chemical mechanical polishing process. The Shallow Trench Isolation (STI) process for forming has been widely used in recent years.
한편, 최근에는 STI공정으로 소자분리막을 형성한 후 게이트전극을 형성하는 트랜지스터 제조방법을 주로 사용하고 있으며, 이러한 게이트전극을 형성하는 공정을 살펴 보면, 반도체기판에 트렌치(Trench)를 형성한 후 갭필링산화막(Gap Filling Oxide)을 이 트렌치내에 채우도록 한다.Recently, a transistor manufacturing method for forming a gate electrode after forming an isolation layer by an STI process is mainly used. Referring to the process for forming the gate electrode, a gap is formed after forming a trench in a semiconductor substrate. Gap Filling Oxide is filled into this trench.
그리고, 트렌치내에 갭필링산화막을 채운 상태에서 식각을 하여 소자분리막을 형성하고, 그 위에 게이트유전체로 사용되는 게이트산화막을 적층하도록 한다.Then, the trench is etched while the gap filling oxide film is filled in the trench to form an isolation layer, and the gate oxide film used as the gate dielectric is stacked thereon.
그리고, 그 위에 게이트전극의 제1차전극으로 사용되는 도핑된 폴리실리콘층을 증착하고, 세정공정을 거친 후 제2차전극으로 사용되는 텅스텐실리사이드층을 적층한 후 감광막을 식각하여 게이트전극을 형성한 후 통상적인 후속공정을 진행하 도록 한다.Then, a doped polysilicon layer used as the primary electrode of the gate electrode is deposited thereon, a tungsten silicide layer used as the secondary electrode is deposited after the cleaning process, and the photosensitive film is etched to form a gate electrode. Then proceed with the usual follow-up process.
그런데, 상기한 바와 같이, 텅스텐실리사이드층을 증착하기 전에 하부폴리실리콘층 상에 형성되어 있는 자연산화막(Native Oxide)을 제거하기 위하여 세정공정을 통상적으로 실시하는 것으로서, 이때, 습식방식으로 불산계케미칼을 사용하여 처리하는 경우 표면에 이상반응의 소오스(Source)가 형성되어 후속 텅스텐실리사이드와 반응하여 원형의 결함(Deffect)을 유발시킨다.However, as described above, a cleaning process is generally performed to remove the native oxide formed on the lower polysilicon layer before depositing the tungsten silicide layer, and in this case, hydrofluoric chemicals In the case of treatment with a source of an adverse reaction (Source) is formed on the surface and reacts with subsequent tungsten silicide to cause a circular defect (D effect).
만약, 이러한 결함을 제거하기 위하여 AnHydrous HF를 처리하는 경우 이중 일부가 하부의 하부폴리실리콘층을 통하여 게이트산화막을 에칭하여 결국 산화막의 두께를 감소시키고, 구멍을 형성하여 게이트전극에 치명적인 결함을 유발시킬 뿐만아니라 하부의 하부폴리실리콘층에 인(Posphorous)이 후속열공정에서 텅스텐실리사이드층으로 확산하여 하부폴리실리콘층내에 Depletion을 유발하여 결국 전기적인 게이트산화막의 두께를 변화시키므로 반도체소자의 전기적인 특성을 악하시키는 문제점을 지니고 있었다. If AnHydrous HF is treated to remove these defects, some of them may etch the gate oxide film through the lower polysilicon layer at the bottom, thereby reducing the thickness of the oxide film and forming holes to cause a fatal defect in the gate electrode. In addition, the phosphorous in the lower polysilicon layer below diffuses into the tungsten silicide layer in the subsequent thermal process, causing depletion in the lower polysilicon layer, thereby changing the thickness of the electrically gate oxide film, thereby improving the electrical characteristics of the semiconductor device. Had evil problems.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판에 STI공정으로 소자분리막을 형성하고, 그 위에 게이트산화막 및 하부폴리실리콘층을 형성한 후 후속공정에서 하부폴리실리콘층 상에 불산계케미칼로 자연산화막을 제거하고, 오존수를 사용하여 표면을 친수성으로 만들고 하부폴리실리콘층에 As가 포함된 이온을 주입하여 텅스텐실리사이드층을 적층하면서 발생되는 결함을 방지하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and a device isolation film is formed on a semiconductor substrate by an STI process, a gate oxide film and a lower polysilicon layer are formed thereon, and a hydrofluoric acid-based chemical layer is formed on the lower polysilicon layer in a subsequent process. The purpose is to remove the natural oxide film, to make the surface hydrophilic by using ozone water, and to inject ions containing As into the lower polysilicon layer to prevent defects that occur when the tungsten silicide layer is laminated.
이러한 목적은 반도체기판 상에 소자분리막을 형성한 후 게이트산화막 및 하부폴리실리콘층을 순차적으로 적층하도록 하는 단계와; 상기 하부폴리실리콘층 상에 형성되어 있는 자연산화막을 불산계 케미칼로 제거한 후 하부폴리실리콘층의 표면을 친수성으로 만드는 단계와; 상기 하부폴리실리콘층에 상부 표면을 비정질화하도록 하는 As이온을 주입하는 단계와; 상기 단계 후에 하부폴리실리콘층 상에 텅스텐실리사이드층 및 상부폴리실리콘층을 순차적으로 적층하여 식각으로 게이트전극을 형성하는 단계를 포함한 게이트전극 결함발생억제방법을 제공함으로써 달성된다. The object of the present invention is to form a device isolation film on a semiconductor substrate and then sequentially stack the gate oxide film and the lower polysilicon layer; Removing the natural oxide film formed on the lower polysilicon layer with hydrofluoric acid-based chemicals and then making the surface of the lower polysilicon layer hydrophilic; Implanting As ions into the lower polysilicon layer to amorphize an upper surface thereof; After the step is achieved by providing a gate electrode defect generation suppression method comprising the step of sequentially forming a tungsten silicide layer and an upper polysilicon layer on the lower polysilicon layer to form a gate electrode by etching.
그리고, 하부폴리실리콘층의 상부면을 친수성으로 만들기 위하여 오존수를 사용하도록 한다. 상기 오존수로 세정한 후에는 초순수에서 세정공정없이 웨이퍼(Wafer)를 건조하도록 하는 단계를 더 포함하게 된다.Then, ozone water is used to make the upper surface of the lower polysilicon layer hydrophilic. After washing with the ozone water, the method may further include drying the wafer without washing in ultrapure water.
또한, 상기 하부폴리실리콘층은 560℃이하의 온도에서 비정질폴리실리콘을 증착하도록 하고, 상기 하부폴리실리콘층을 적층한 후 고온의 SC-1세정으로 노출된 하부폴리실리콘층을 산화 및 에칭(Etching)하는 단계를 더 포함하도록 한다.In addition, the lower polysilicon layer is to deposit amorphous polysilicon at a temperature of 560 ℃ or less, and after laminating the lower polysilicon layer oxidized and etching the lower polysilicon layer exposed by high temperature SC-1 cleaning (Etching) The method may further include a step.
상기 하부폴리실리콘층의 상부면을 친수성으로 만들기 위하여 저농도의 SC-1세정공정을 수행할 수도 있다.In order to make the upper surface of the lower polysilicon layer hydrophilic, a low concentration SC-1 cleaning process may be performed.
이하, 첨부한 도면에 의거하여 본 발명의 일실시예에 대하여 상세히 살펴보도록 한다. Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5은 일반적인 반도체장치의 트랜지스터에서 게이트전극을 형성하는 방법을 순차적으로 보인 도면이다. 1 to 5 are diagrams sequentially illustrating a method of forming a gate electrode in a transistor of a general semiconductor device.
도 1 및 도 2는 반도체기판(10)상에 소자분리막(20)을 형성한 후 게이트산화막(30) 및 하부폴리실리콘층(40)을 순차적으로 적층하는 상태를 도시한 것으로, 상기 하부폴리실리콘층(40) 상에 형성되어 있는 자연산화막(Native Oxide)을 불산계 케미칼로 제거한 후에는 표면이 소수성으로 변하여 더욱 오염이 심해지므로 하부폴리실리콘층(40)의 표면을 친수성으로 만들도록 한다.1 and 2 illustrate a state in which the gate oxide layer 30 and the lower polysilicon layer 40 are sequentially stacked after the device isolation layer 20 is formed on the semiconductor substrate 10. After removing the native oxide formed on the layer 40 with hydrofluoric acid-based chemicals, the surface becomes hydrophobic and becomes more contaminated, thereby making the surface of the lower polysilicon layer 40 hydrophilic.
그리고, 상기 하부폴리실리콘층(40)의 상부면을 친수성으로 만들기 위하여 오존수를 사용하는 것이 바람직하다.In addition, it is preferable to use ozonated water to make the upper surface of the lower polysilicon layer 40 hydrophilic.
또한, 상기 오존수로 세정한 후 초순수에서 세정공정없이 웨이퍼를 건조하도록 하는 단계를 더 포함할 수도 있다.The method may further include drying the wafer without the cleaning process in ultrapure water after cleaning with the ozone water.
상기 하부폴리실리콘층(40)의 상부 표면을 변화시켜 비정질화하면 결함 발생이 억제되므로 하부폴리실리콘층(40)에 As가 포함된 이온을 주입하여 그 표면을 비정질화시켜 결함발생이 감소되며, 더구나 As가 포함된 이온을 주입함으로 후속공적으로 상기 하부폴리실리콘층(40)의 상부에 증착되는 텅스텐실리사이드층(50)으로 하부폴리실리콘층(40)에 포함된 인이 이동하는 것이 방지된다.If the amorphous surface is changed by changing the upper surface of the lower polysilicon layer 40, defects are suppressed, so that defects are reduced by injecting ions containing As into the lower polysilicon layer 40 and making the surface amorphous, In addition, the implantation of ions containing As prevents the phosphorus contained in the lower polysilicon layer 40 from being subsequently deposited on the tungsten silicide layer 50 deposited on the lower polysilicon layer 40.
즉, 하부폴리실리콘층(40)의 상부에 텅스텐실리사이드가 증착되면서 하부폴리실리콘층(40)에 포함되어 있던 인이 확산하여 텅스텐실리사이드로 이동하면서 하부폴리실리콘층(40)에 공핍영역이 발생하고 이에 따라 전기적으로 게이트 산화막의 두께가 변한 것처럼 소자 특성이 변하게 되는 현상이 방지된다. 특히 이와 같이 As를 포함하는 이온을 주입하는 공정은 세정공정의 실시 유무에 관계없이도 결함방지와 공핍층 형성 방지에 충분한 효과를 얻을 수 있다. That is, as tungsten silicide is deposited on the lower polysilicon layer 40, phosphorus included in the lower polysilicon layer 40 diffuses to move to tungsten silicide, and a depletion region is generated in the lower polysilicon layer 40. This prevents the phenomenon in which the device characteristics change as the thickness of the gate oxide film is electrically changed. In particular, the step of implanting ions containing As can be sufficiently effective in preventing defects and preventing depletion layer formation regardless of whether or not the cleaning process is performed.
상기 하부폴리실리콘층(40)은 560℃이하의 온도에서 비정질폴리실리콘(Amorphorous Poly-Silicon)을 증착하도록 한다.The lower polysilicon layer 40 is used to deposit amorphous polysilicon (Amorphorous Poly-Silicon) at a temperature of 560 ℃ or less.
그리고, 상기 하부폴리실리콘층(40)을 적층한 후 고온의 SC-1(NH4OH +H2O2 + H2O의 혼합용액)세정으로 노출된 하부폴리실리콘층(40)을 산화 및 에칭하는 단계를 더 포함할 수 있으며, 표면의 산화막을 불산계 케미칼을 이용하여 제거한 후에 상기 하부폴리실리콘층(40)의 상부면을 친수성으로 만들기 위하여 저농도의 SC-1세정공정을 수행하도록 한다.After laminating the lower polysilicon layer 40, the lower polysilicon layer 40 exposed to high-temperature SC-1 (mixture of NH 4 OH + H 2 O 2 + H 2 O) cleaning is oxidized and The method may further include etching, and after removing the oxide layer on the surface by using a hydrofluoric acid-based chemical compound, a low concentration SC-1 cleaning process may be performed to make the upper surface of the lower polysilicon layer 40 hydrophilic.
도 4 및 도 5는 상기 단계 후에 하부폴리실리콘층(40) 상에 텅스텐실리사이드층(50) 및 상부폴리실리콘층(60)을 순차적으로 적층하여 식각으로 게이트전극(A)을 형성하는 상태를 도시하고 있으며, 그 후에는 통상적으로 알려져 있는 후속공정을 진행하도록 한다. 4 and 5 illustrate a state in which the gate electrode A is formed by etching by sequentially stacking the tungsten silicide layer 50 and the upper polysilicon layer 60 on the lower polysilicon layer 40 after the step. After that, to proceed with a conventionally known subsequent process.
따라서, 상기한 바와 같이 본 발명에 따른 게이트전극 결함발생억제방법을 이용하게 되면, 반도체기판에 STI공정으로 소자분리막을 형성하고, 그 위에 게이트산화막 및 하부폴리실리콘층을 형성한 후 후속공정에서 하부폴리실리콘층 상에 불산계케미칼로 자연산화막을 제거하고, 오존수를 사용하여 표면을 친수성으로 만들고, As가 포함된 이온주입공정을 실시하게 되면 텅스텐실리사이드층을 적층하면서 발생되는 결함이 방지될 뿐만 아니라 후속 열공정에서 하부폴리실리콘층에 포함된 인이 텅스텐실리사이드층으로 이동하는 것을 방지하여 하부폴리실리콘층이 공핍층화되는 것을 방지하도록 하는 매우 유용하고 효과적인 발명이다.Accordingly, when the gate electrode defect generation suppression method according to the present invention is used as described above, the device isolation film is formed on the semiconductor substrate by the STI process, the gate oxide film and the lower polysilicon layer are formed thereon, and then, Removing the natural oxide film with hydrofluoric acid-based chemical on the polysilicon layer, making the surface hydrophilic with ozone water, and performing an ion implantation process containing As not only prevents defects caused by laminating the tungsten silicide layer. It is a very useful and effective invention to prevent the phosphorus contained in the lower polysilicon layer from moving to the tungsten silicide layer in the subsequent thermal process to prevent the lower polysilicon layer from depletion.
도 1 내지 도 5은 일반적인 반도체장치의 트랜지스터에서 게이트전극을 형성하는 방법을 순차적으로 보인 도면이다. 1 to 5 are diagrams sequentially illustrating a method of forming a gate electrode in a transistor of a general semiconductor device.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
10 : 반도체기판 20 : 소자분리막10: semiconductor substrate 20: device isolation film
30 : 게이트산화막 40 : 하부폴리실리콘층30 gate oxide film 40 lower polysilicon layer
50 : 텅스텐실리사이드층 60 : 상부폴리실리콘층50: tungsten silicide layer 60: upper polysilicon layer
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950001904A (en) * | 1993-06-25 | 1995-01-04 | 김주용 | Gate electrode formation method |
| KR960008564A (en) * | 1994-08-10 | 1996-03-22 | A device for a computer memory interface, a portable mobile computer and a method for fetching program instructions and performing a data write / read request on the computer | |
| JPH0936360A (en) * | 1995-07-20 | 1997-02-07 | Nec Corp | Fabrication of semiconductor device |
| KR980006135A (en) * | 1996-06-29 | 1998-03-30 | 김주용 | Wiring method using tungsten silicide |
| US5814562A (en) * | 1995-08-14 | 1998-09-29 | Lucent Technologies Inc. | Process for semiconductor device fabrication |
| US5851892A (en) * | 1997-05-07 | 1998-12-22 | Cypress Semiconductor Corp. | Fabrication sequence employing an oxide formed with minimized inducted charge and/or maximized breakdown voltage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950001904A (en) * | 1993-06-25 | 1995-01-04 | 김주용 | Gate electrode formation method |
| KR960008564A (en) * | 1994-08-10 | 1996-03-22 | A device for a computer memory interface, a portable mobile computer and a method for fetching program instructions and performing a data write / read request on the computer | |
| JPH0936360A (en) * | 1995-07-20 | 1997-02-07 | Nec Corp | Fabrication of semiconductor device |
| US5814562A (en) * | 1995-08-14 | 1998-09-29 | Lucent Technologies Inc. | Process for semiconductor device fabrication |
| KR980006135A (en) * | 1996-06-29 | 1998-03-30 | 김주용 | Wiring method using tungsten silicide |
| US5851892A (en) * | 1997-05-07 | 1998-12-22 | Cypress Semiconductor Corp. | Fabrication sequence employing an oxide formed with minimized inducted charge and/or maximized breakdown voltage |
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