KR100567056B1 - Method of manufacturing SRAM device - Google Patents

Abstract

The present invention discloses a method for manufacturing an SRAM device. The disclosed method of manufacturing an SRAM device includes forming a gate on a semiconductor substrate, sequentially forming an oxide film and a nitride film on an entire region of the substrate including the gate, and maintaining a predetermined thickness of the oxide film. Forming a spacer on both side walls of the gate by spacer etching the nitride film and the oxide film, and performing source / drain ion implantation into the substrate on both sides of the gate including the spacer using the remaining oxide film as a buffer film; Removing an oxide film remaining on a surface, forming an oxide film for a buffer on the substrate, performing annealing at an in-situ N2 atmosphere and 850 ° C. for 20 minutes, and the source / drain ion implanted dopant Performing a rapid thermal process at 950 ° C. for 20 seconds to be activated, and BLC (Bit-Lin) on the buffer oxide film. e Contact) a step of depositing a nitride film, wherein the buffer oxide film is formed to a thickness of 80 ~ 120∼ over a temperature range of 680 ~ 830 ℃, it is formed by a CVD method, a wet or dry oxidation method. According to the present invention, by applying heat of 650 ℃ or more at the time of forming the oxide film for the buffer, it is possible to suppress the occurrence of the dislocation during the subsequent RTP process, and also to improve the leakage characteristics through the two-step annealing, In addition, it is possible to reduce the stress caused by the application of the BLC nitride film by forming the buffer oxide film.

Description

Method of manufacturing SRAM device {Method of manufacturing SRAM device}

1A to 1D are cross-sectional views of processes for describing a method of manufacturing an SRAM device according to an exemplary embodiment of the present invention.

FIG. 2 is a graph depicting critical stress for dislocation occurrence depending on annealing temperature after source / drain ion implantation.

3 is a graph showing leakage current characteristics from an N + drain to a P + substrate.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 2 gate oxide film

3: polysilicon film 4: capping nitride film

5 gate 6 oxide film

7 spacer oxide film 8 spacer nitride film

9 spacer 10 buffer oxide film

11: BLC nitride film

The present invention relates to a method for manufacturing an SRAM device, and more particularly, to a method for relieving stress caused by applying a bit-line contact (BLC) film while preventing the occurrence of dislocation during a rapid thermal process for dopant activation.

As is well known, SRAM (SRAM) devices have the advantage of being operated at high speed, low power consumption and simple operation. In addition, unlike a DRAM (DRAM) device, an SRAM device does not need to periodically refresh stored information, and is easy to design.

Hereinafter, a manufacturing method of a conventional SRAM device will be briefly described.

First, a polysilicon gate is formed on a semiconductor substrate provided with an isolation layer according to a known process, and then an oxidation process and an LDD ion implantation process are sequentially performed. Thereafter, a spacer oxide film is deposited to a thickness of about 200 GPa on the entire region of the substrate, and then a spacer nitride film is deposited to a thickness of 600 to 700 GPa by LPCVD.

Subsequently, the nitride layer and the oxide layer are etched with a spacer to form a spacer on the sidewall of the gate. In this case, the spacer etching is controlled such that the thickness Rox of the residual oxide layer is about 100 ± 50 μs. Then, source / drain ion implantation is performed on the substrate surfaces on both sides of the gate, and then a rapid thermal process (hereinafter referred to as RTP) is performed on the substrate resultant to activate the implanted impurities.

Then, a BLC (Bit-Line Contact) nitride film to be used as an etch stop film in a subsequent metallization process is deposited to a thickness of approximately 300 kW.

Thereafter, a series of subsequent SRAM processes including contact etching are performed. The contact etching is preferably adjusted such that the thickness Rox of the remaining oxide layer is about 50 GPa.

However, the conventional method of manufacturing the SRAM device as described above has the following problems.

First, after source / drain ion implantation, it is common to perform RTP for activation of dopants. In this case, the portion of the substrate amorphous by ion implantation is recrystallized and desorption is performed at the gate edge. ), Which causes deterioration of device characteristics.

Next, the residual oxide film is an oxide film left during the spacer etching, and the thickness control is very important. However, since the residual thickness is not easily controlled from the spacer etching process, it is difficult to control the oxide film residual thickness even in subsequent contact etching. Accordingly, in the portion where the residual oxide film thickness Rox is thin, the stress of the BLC nitride film is transferred to the substrate as it is, resulting in deterioration of device characteristics.

Accordingly, an object of the present invention is to provide a method for manufacturing an SRAM device capable of relieving stress caused by application of a BLC nitride film while preventing the occurrence of dislocation during RTP. have.

Method of manufacturing an SRAM device according to the present invention for achieving the above object comprises the steps of forming a gate through a gate oxide film on a semiconductor substrate; Sequentially forming an oxide film and a nitride film on the entire region of the substrate including the gate; Etching the nitride layer and the oxide layer to form spacers on both sidewalls of the gate, such that the oxide layer remains on the semiconductor substrate by a predetermined thickness; Performing source / drain ion implantation into the semiconductor substrate on both sides of the gate including the spacer using the remaining oxide film as a buffer film; Removing the remaining oxide film on the semiconductor substrate; Forming an oxide film for a buffer on the resultant of the semiconductor substrate; Performing a rapid thermal process at 950 ° C. for 20 seconds to activate the source / drain ion implanted dopant; And depositing a BLC nitride film on the buffer oxide film.

Here, the buffer oxide film is formed to a thickness of 80 ~ 120 Pa in the temperature range of 680 ~ 830 ℃, deposited by using SiH2Cl2 and N20 gas at a pressure of 0.25 ~ 0.5 Torr and a temperature of 810 ~ 830 ℃ according to the CVD method Or deposit using SiH4 and N20 gas at a pressure of 0.25 to 0.5 Torr and a temperature of 770 to 790 ° C, or use Si (OC2H5) 4 and O2 gas at a pressure of 0.25 to 0.5 Torr and a temperature of 680 to 710 ° C. By vapor deposition.

In addition, the buffer oxide film is formed to a thickness of 80 ~ 120 ℃ in the temperature range of 680 ~ 830 ℃, grown by dry oxidation method using O2 gas, or wet oxidation method using O2 and H2 gas Form by growing.

In addition, annealing is performed for 10 to 20 minutes at 840 to 860 ° C using N2 gas in-situ in the furnace after the step of depositing the buffer oxide film and before the rapid thermal process.

According to the present invention, by applying a heat of 650 ℃ or more at the time of forming the buffer oxide film, it is possible to suppress the occurrence of dislocation during the subsequent RTP process, and also the stress of applying the BLC nitride film through the formation of the buffer oxide film Can alleviate

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating processes for manufacturing a SRAM device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a gate oxide film 2, a polysilicon film 3, and a capping nitride film 4 are sequentially formed on a semiconductor substrate 1 including an isolation layer (not shown), and then the films 4 are formed. , 3 and 2 are patterned to form the gate 5. Then, an oxidation process is performed to form a thin film oxide film 6 on the gate 5 and the substrate 1 surface.

Subsequently, a spacer oxide film 7 and a spacer nitride film 8 are sequentially formed on the substrate resultant, and then the films 8 and 7 are spacer-etched on both side walls of the gate 5 including the oxide film 6 of the thin film. The spacer 9 is formed. In this case, the spacer etching is performed such that the spacer oxide layer 7 remains at a predetermined thickness on both sides of the gate 5 including the spacer 9.

Referring to FIG. 1B, source / drain ion implantation is performed in the substrate surface on both sides of the gate 5 including the spacer 9 using the spacer oxide film remaining on the substrate surface as a buffer film. The residual oxide film on the surface of the substrate is then removed by wet etching with a conventional oxide etchant, such as HF or BOE solution.

Referring to FIG. 1C, an oxide film 10 for a buffer is formed on a substrate resultant up to this step. The buffer oxide film 10 is formed to a thickness of 80 to 120 kPa in a temperature range of 680 to 830 ° C, and is formed by a CVD method or an oxidation method.

In detail, the buffer oxide film 10 is formed by depositing with DCS HTO using SiH 2 Cl 2 and N 20 gas at a pressure of 0.25 to 0.5 Torr and a temperature of 810 to 830 ° C. according to a CVD method, or a pressure of 0.25 to 0.5 Torr. It is formed by depositing with HTO using SiH4 and N20 gas at a temperature of 770-790 ° C, or TEOS (Tetra-Ethyl-Ortho-Silicate: Si (OC2H5) at a pressure of 0.25-0.5 Torr and a temperature of 680-710 ° C. 4) and O2 gas to form a vapor deposition.

In addition, the buffer oxide film 10 is formed by growing in a dry oxidation method using O2 gas, or is formed by growing in a wet oxidation method using O2 and H2 gas.

Subsequently, with respect to the substrate product in which the oxide film 10 for the buffer 10 is formed in accordance with the CVD method or the oxidation method, in an in-situ furnace in an N 2 atmosphere and 840 to 860 ° C., preferably, 850. Annealing is carried out at < RTI ID = 0.0 > 10-20 < / RTI >

Subsequently, RTP is performed at 950 ° C. for 20 seconds on the substrate resultant so that the source / drain implanted dopant is sufficiently activated in the previous process step.

Referring to FIG. 1D, a BLC nitride film 11 is deposited on the buffer oxide film 10 at a thickness of 300 kPa by a CVD method.

Subsequently, although not shown, a series of subsequent SRAM processes including contact etching are performed to complete the manufacture of the SRAM device according to the present invention.

According to the method of the present invention as described above, it is possible to prevent deterioration of device characteristics due to dislocation and stress as follows.

In general, the stress causing dislocation due to recrystallization after source / drain ion implantation is significantly reduced when heat of 650 ° C. or higher is applied.

FIG. 2 is a graph showing the critical stress for the dislocation occurrence depending on the annealing temperature after source / drain ion implantation. The critical stress for the dislocation occurrence is not significantly changed at the annealing temperature of 650 ° C. or lower, but is higher than 650 ° C. It can be seen that the critical stress is significantly reduced at.

3 is a graph showing the leakage current characteristic from the N + drain to the P + substrate, wherein the leakage characteristic from the N + drain to the P + substrate after activation of the dopant is 850 ° C rather than the case where annealing at 950 ° C is performed once. It can be seen that the case where the two-step annealing of annealing and annealing at 950 ° C. is performed is improved.

Therefore, the method of the present invention performs annealing at 850 ° C. in-situ after formation of the buffer oxide film 10 and subsequently performs RTP at 950 ° C., thereby suppressing the above-described dislocation occurrence. In addition to reducing critical stress, leakage characteristics are also improved.

On the other hand, in applying the BLC nitride film, it is very important to control the residual thickness Rox of the spacer oxide film. In the related art, it is difficult to control the residual thickness. Therefore, deterioration of device characteristics due to stress is caused by the application of the BLC nitride film. Triggered.

However, the method of the present invention forms a new buffer oxide film after removing the remaining spacer oxide film, and at this time, by forming the thickness again to a desired thickness, that is, to sufficiently relieve the stress of the BLC nitride film, It is possible to prevent deterioration of device characteristics due to stress caused by the application of the BLC nitride film.

As a result, the method of the present invention can effectively prevent deterioration of device characteristics due to dislocation and stress from further proceeding further formation of the buffer oxide film at a temperature of 650 ° C. or higher and in-situ annealing after the formation.

As described above, the present invention forms a buffer oxide film after source / drain ion implantation and before deposition of the BLC nitride film, and further performs annealing at 850 ° C. in the process of forming the buffer oxide film, and then, By performing RTP at 950 ° C for dopant activation, dislocation generation can be effectively suppressed, and the stress caused by the application of the BLC nitride film can be alleviated by forming the buffer oxide film. Properties can be improved.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (8)

Forming a gate by interposing a gate oxide film on the semiconductor substrate; Sequentially forming an oxide film and a nitride film on the entire region of the substrate including the gate; Etching the nitride layer and the oxide layer to form spacers on both sidewalls of the gate, such that the oxide layer remains on the semiconductor substrate by a predetermined thickness; Performing source / drain ion implantation into the semiconductor substrate on both sides of the gate including the spacer using the remaining oxide film as a buffer film; Removing the remaining oxide film on the semiconductor substrate; Forming an oxide film for a buffer on the resultant of the semiconductor substrate; Performing a rapid thermal process at 950 ° C. for 20 seconds to activate the source / drain ion implanted dopant; And And depositing a BLC nitride film on the buffer oxide film. The method of claim 1, wherein the buffer oxide film is formed at a thickness of 80 to 120 kPa at a temperature of 680 to 830 deg. The method of claim 1, wherein the buffer oxide film is deposited using SiH2Cl2 and N20 gas at a pressure of 0.25 ~ 0.5 Torr and a temperature of 810 ~ 830 ℃ according to the CVD method. Manufacturing method. The SRAM device according to claim 1 or 2, wherein the buffer oxide film is deposited using SiH4 and N20 gas at a pressure of 0.25 to 0.5 Torr and a temperature of 770 to 790 ° C according to the CVD method. Manufacturing method. The method of claim 1 or 2, wherein the buffer oxide film is deposited using a Si (OC 2 H 5) 4 and O 2 gas at a pressure of 0.25 ~ 0.5 Torr and a temperature of 680 ~ 710 ℃ according to the CVD method. Method of manufacturing the SRAM element. The method for manufacturing an SRAM device according to claim 1 or 2, wherein the buffer oxide film is grown by a dry oxidation method using O2 gas. The method for manufacturing an SRAM device according to claim 1 or 2, wherein the buffer oxide film is grown by a wet oxidation method using O2 and H2 gas. 10. The method of claim 1, wherein after the deposition of the buffer oxide film and before the rapid thermal process, the N2 gas is used in-situ in the furnace at 840 to 860 ° C. Annealing is carried out for ˜20 minutes.

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