KR100564204B1 - Method of forming a isolation layer in a semiconductor device - Google Patents

Abstract

According to the present invention, a method of forming an isolation layer of a semiconductor device includes forming a trench in an isolation region of a semiconductor substrate, forming an oxide film under the trench by a thermal oxidation process, and forming an oxide film over the trench by a deposition method. By forming a, the lower portion of the high aspect ratio trench can be easily buried without oxide into the oxide film while preventing the occurrence of buzz big, further reducing the area of the device isolation region and improving the integration degree. Can be.

Device Separator, STI, Anti-Oxidation Spacer, Thermal Oxidation Process, HDP Oxide

Description

Method of forming a isolation layer in a semiconductor device             

1A to 1J are cross-sectional views of devices for describing a method of forming a device isolation layer of a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

101 semiconductor substrate 102 pad oxide film

103: pad nitride film 104: first trench

105: liner oxide film 106: anti-oxidation spacer

107: second trench 108: thermal oxide film

109: deposited oxide film 110: device isolation film

147: trench

The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device having a shallow trench isolation (STI) structure.

As a method for electrically isolating the semiconductor devices formed on the semiconductor substrate, in the method of manufacturing a semiconductor device having a design rule of 0.35um or more, the devices are isolated by the LOCOS method. However, the LOCOS method has a difficulty in high-integrating devices because a bird's beak phenomenon occurs due to lateral oxidation.

For this reason, in the method of manufacturing a semiconductor device having a design rule of 0.25 µm or less, an isolation layer is formed in a shallow trench isolation (STI) structure. The device isolation film having the STI structure is formed by forming a trench in the device isolation region of the semiconductor substrate and filling the trench with an insulating material. However, as the degree of integration of the device increases, the width of the trench to be filled with the insulating material becomes narrower and the depth deeper. For this reason, the bias power applied to the plasma must be increased to improve the embedding properties of the insulating material. However, although the buried characteristic may be improved by increasing the bias power, plasma damage may occur in the pattern formed on the semiconductor substrate due to the high power plasma.

On the other hand, the method of manufacturing the NAND flash memory device proposed by the present invention                         

After the trench is formed in the device isolation region of the semiconductor substrate, an oxide film is formed in the lower portion of the trench by a thermal oxidation process, and an oxide film is formed in the upper portion of the trench by the deposition method to prevent the occurrence of buzz big. While the oxide film can be easily formed without a void in the lower portion of the trench having a high aspect ratio, the buried property can be improved.

In the method of forming a device isolation layer of a semiconductor device according to an embodiment of the present invention, an oxide spacer is formed by filling a lower portion of a trench with a thermal oxide layer in a state in which an antioxidant spacer is formed only on an upper portion of a trench sidewall formed on a semiconductor substrate, and then removing an oxide layer and depositing an oxide. The upper portion of the trench is filled with the deposited oxide film.

In another embodiment, a method of forming a device isolation layer of a semiconductor device includes forming a first trench in a device isolation region of a semiconductor substrate at a predetermined depth, and forming an antioxidant spacer on a sidewall of the first trench; Etching the device isolation region of the semiconductor substrate further to form a second trench having a target depth, performing a thermal oxidation process to fill the second trench with the thermal oxide film, and removing the anti-oxidation spacer; And filling the first trench with a deposition oxide film.

In another embodiment, a method of forming a device isolation film of a semiconductor device includes sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate, removing the pad nitride film and the pad oxide film in a device isolation region, and Forming a first trench at a predetermined depth in the isolation region, forming an anti-oxidation spacer on the sidewall of the first trench, and etching the device isolation region of the semiconductor substrate further to form a second trench at a target depth. And depositing the second trench with the thermal oxide film by performing a thermal oxidation process, removing the anti-oxidation spacer, filling the first trench with the deposition oxide film, and chemical mechanical polishing process. And flattening while removing.

The method may further include forming a liner oxide layer on a sidewall and a bottom of the first trench by a thermal oxidation process after forming the first trench and before forming the antioxidant spacer.

The anti-oxidation spacer may be formed of nitride, and may be formed by forming nitride on the entire structure and then leaving the nitride only on the sidewalls of the first trench by a front etching process.

The antioxidant spacer may be removed by a wet etching method using phosphoric acid, or may be removed by sputtering by applying a predetermined bias to the semiconductor substrate to generate ions and collide with the semiconductor substrate.

The vapor deposition oxide film may be formed of a high density plasma oxide film.

The thermal oxide film forming step, the antioxidant spacer removing step, and the deposition oxide film forming step may be performed in the same chamber. For example, when the second trench is completely filled with the thermal oxide film in order to form a thermal oxide film and then the second trench is completely filled with the thermal oxide film, the oxygen is blocked and the antioxidant spacer is removed by sputtering or reactive ion etching. The deposition oxide film may be deposited by supplying a source gas and a reactant gas and generating a plasma with a bias.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

1A to 1J are cross-sectional views of devices for describing a method of forming a device isolation layer of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a pad oxide film 102 and a pad nitride film 103 are sequentially formed on a semiconductor substrate 101 substrate. Here, the pad oxide film 102 may be formed to a thickness of 50 kPa to 300 kPa. The pad nitride film 103 may be formed to a thickness of 1000 kPa to 2000 kPa.

Referring to FIG. 1B, the pad nitride film 103 and the pad oxide film 102 in the device isolation region are sequentially etched. As a result, the device isolation region of the semiconductor substrate 101 is exposed.

Referring to FIG. 1C, the first isolation region 104 is formed by etching the device isolation region of the semiconductor substrate 101 by a predetermined depth. At this time, the depth of the first trench 104 is formed to be shallower than the trench of the target depth for forming the device isolation film of the STI structure, it is preferable to form deeper than the depth of the junction such as the source / drain of the transistor to be formed in a subsequent process. Do. The etching process for forming the first trenches 104 may be performed at a pressure of 1 mTorr to 50 mTorr, and N ₂ / HBr / Cl ₂ / O ₂ gas may be used as the etching gas. At this time, top power of 500W to 1500W and bottom power of 20W to 300W are applied.

Referring to FIG. 1D, in order to alleviate the etching damage generated in the process of forming the first trench 104 and to improve the interfacial characteristics of the device isolation layer and the semiconductor substrate 101 to be formed in a subsequent process, the first trench ( The sidewalls and bottom surface of 104 are oxidized by a thermal oxidation process to form a liner oxide film 105. Since the liner oxide film 105 is formed by a thermal oxidation process, excellent interface characteristics with the semiconductor substrate 101 can be obtained at the sidewalls and the bottom of the first trench 104. This thermal oxidation process may be carried out in a wet oxidation method at a temperature of 900 ℃ to 1300 ℃.

Since the liner oxide layer 105 is formed by a thermal oxidation process, the upper and lower edges of the first trench 104 may be rounded to prevent concentration of an electric field. The liner oxide film 105 serves as a buffer film that can alleviate the stress applied to the semiconductor substrate 101 by the anti-oxidation spacer to be formed in a subsequent process.

On the other hand, since the liner oxide layer 105 is formed by a thermal oxidation process, a bird's beak may occur from an upper edge of the first trench 104 to the active region, but damage to the bottom surface of the sidewall of the first trench 104 may occur. The amount of buzz big generated is negligible because the thermal oxidation process is only performed to mitigate and achieve only the rounding effect. Rather, damage mitigation and field concentration mitigation characteristics can be further improved compared to buzz big occurrences.

As described above, the thermal oxidation process performs the thermal oxidation process so that the liner oxide film 105 is formed to an appropriate thickness in consideration of the width of the first trench 104 and the occurrence of buzz big.

After the liner oxide film 105 is formed, annealing is performed in a nitrogen atmosphere so that the film quality of the liner oxide film 105 becomes dense. This annealing of the nitrogen atmosphere may be carried out for 20 to 30 minutes at a temperature of 1000 ℃ to 1100 ℃.

This thermal oxidation process is not an essential process and can be omitted.

Referring to FIG. 1E, the anti-oxidation spacer 106 is formed on the sidewall of the first trench 104. The anti-oxidation spacer 106 is formed to prevent oxidation from progressing in the horizontal direction on the sidewall of the first trench 104 by a subsequent thermal process. On the other hand, the surface of the semiconductor substrate 101 is exposed on the bottom of the first trench 104. If the liner oxide film is formed on the sidewalls and the bottom of the first trench 104 as shown in FIG. 1D, the liner oxide film 105 is exposed.

The anti-oxidation spacer 106 may be formed of any material that can inhibit the oxidation action. It may be formed of the same material as the pad nitride film 103. For example, in the case of forming a nitride-based material such as Si ₃ N ₄ , nitride is formed on the entire structure, and then the entire surface etching process is performed to form nitride as a sidewall of the pad nitride film 103 and the first trench 104. The anti-oxidation spacer 106 may be formed by remaining only on the sidewalls of the anti-oxidation spacer 106.

On the other hand, if the nitride is formed too thick to form the antioxidant spacer 106, the antioxidant spacer 106 may be formed to be thick so that the width of the first trench 104 may be narrowed and the aspect ratio may increase. If the nitride is formed too thin, the nitride is removed from the sidewall portion of the pad nitride film 103, and in severe cases, the nitride is not etched from the upper portion of the sidewall of the first trench 104 so that the sidewall of the first trench 104 is etched. May be exposed.

The ideal deposition thickness of such nitride can vary depending on the degree of integration. Therefore, since the antioxidant spacer 106 needs to be formed at least only on the sidewalls of the first trenches 104, the antioxidant spacers 106 may be formed at least after the front side etching process while considering the device integration and the aspect ratio of the first trenches 104. It is important to form the nitride to a thickness sufficient to completely cover the sidewall of the first trench 104.

Referring to FIG. 1F, when the oxide film of the liner oxide 105 is formed, the oxide film of the liner oxide 105 of the bottom of the first trench 104 is removed. Thereafter, the second trench 107 is formed by etching the exposed device isolation region of the semiconductor substrate 101 to a target depth in an etching process using the pad nitride film 103 and the anti-oxidation spacer 106 as an etching mask. . As a result, the trench 147 having the semiconductor substrate 101 exposed on the lower portion and the anti-oxidation spacer 106 formed on the upper portion is formed.

In the above, the liner oxide layer 105 may be performed by a front etching method or a wet etching method. In the case of wet etching, a solution of dilute hydrofluoric acid (Diluted HF) and SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) containing H ₂ O: HF in a ratio of 50: 1 to 100: 1 BOE and SC-1 (NH ₄₎ diluted in H ₂ O at a ratio of 1: 100 to 1: 300, or a mixed solution of NH ₄ F: HF mixed at 4: 1 to 7: 1. OH / H ₂ O ₂ / H ₂ O) solution can be used sequentially.

The etching process for forming the second trench 107 may be performed at a pressure of 1 mTorr to 50 mTorr, and N ₂ / HBr / Cl ₂ / O ₂ gas may be used as an etching gas. In this case, as in the case of forming the first trench 104, a top power of 500W to 1500W and a bottom power of 20W to 300W may be applied, or a higher bias may be applied to form a deeper trench.

Referring to FIG. 1G, the sidewalls and the bottom of the second trench 107 are oxidized by a thermal oxidation process to fill the second trench 107 with the thermal oxide film 108. In this case, the thermal oxidation process is performed such that the second trench 107 is completely filled with the thermal oxide film 108.

On the other hand, since the thermal oxide film 108 is formed while expanding from side to side, if the thermal oxidation process is excessively performed, the thermal oxide film 108 formed on the left side wall and the right side wall abuts against each other, causing a push force to the second trench. A crack may occur in the semiconductor substrate 101 on the bottom surface. Therefore, in consideration of the growth rate of the thermal oxide film 108 and the width of the second trench 108, the second trench 107 is heated without cracking in the semiconductor substrate 101 at the bottom of the second trench 107. It is preferable to adjust the thermal oxidation process time so as to be embedded in the oxide film 108.

Since the thermal oxide film 108 is formed by a thermal oxidation process, even if the second trench 107 is deep and the aspect ratio is high, the second trench 107 may be sufficiently filled with the thermal oxide film 108 without great difficulty. In addition, since the second trench 107 is narrow and particularly narrower than the first trench 104 by the anti-oxidation spacer 106, the second trench 107 is converted into the thermal oxide film 108 only by the thermal oxidation process. We can bury enough.

On the other hand, since the second trench 107 is buried in the thermal oxidation process, excellent interface characteristics between the thermal oxide film 108 and the semiconductor substrate 101 can be obtained. In addition, the bottom surface of the second trench 107 is rounded, and the interface property of the liner oxide film 105 and the thermal oxide film 108 remaining on the sidewall of the first trench 104 may be improved.

By forming the thermal oxide film 108 as described above, the aspect ratio of the trench 147 is lowered. Since the thermal oxide film 108 is formed while expanding the volume, the aspect ratio of the trench 147 is formed higher than the lower portion of the first trench 104. Is lower than.

The thermal oxidation process for forming the thermal oxide film 108 is performed only for an appropriate time considering the growth rate of the thermal oxide film and the width of the second trench 107.

Referring to FIG. 1H, the antioxidant spacer (106 of FIG. 1G) is removed. This is to lower the aspect ratio of the first trench 104 even further. Since the antioxidant spacer (106 of FIG. 1G) is formed only on the sidewall of the first trench 104, removing it may increase the width of the first trench 104 to lower the aspect ratio, and as a subsequent process, the second trench ( The process of embedding 107 with an insulating material can be carried out more easily, and the embedding properties can be further improved.

In this case, when the antioxidant spacer (106 of FIG. 1G) is made of nitride, it may be removed by a wet etching method or a dry etching method. When removing by wet etching, phosphoric acid may be used to remove the antioxidant spacer (106 of FIG. 1G). A portion of the pad nitride film 103 may be etched in the process of removing the antioxidant spacer (106 of FIG. 1G), but the thickness of the pad nitride film 103 is etched because the thickness of the antioxidant spacer (106 of FIG. 1G) is thin. Can be ignored.

Referring to FIG. 1I, an oxide is deposited on the entire structure so that the first trench 104 is completely filled to form a deposition oxide film 109. The deposition oxide film 109 is deposited in a state where the aspect ratio of the trench 147 is lowered by the thermal oxide film 108, and the anti-oxidation spacer (106 in FIG. 1G) is removed to lower the aspect ratio of the first trench 106. Therefore, the inside of the first trench 104 can be completely filled with the deposition oxide film 109 without generating voids. The deposition oxide film 109 may be formed of a high density plasma (HDP) oxide film.

Meanwhile, when the antioxidant spacers are removed by a dry etching method in FIG. 1H, the thermal oxide film 108 deposition process, the antioxidant spacer removal process, and the deposition oxide film 109 forming process may be performed in the same chamber. That is, in the deposition chamber in which the oxide film is formed, the oxygen oxide film is initially formed by supplying only oxygen to form the thermal oxide film 108 by a thermal oxidation process. Then, the oxygen supply is stopped and a bias is applied to the semiconductor substrate 101 to sputter. The anti-oxidation spacer or the reactive ion etching method to remove the anti-oxidation spacer and then apply a predetermined bias (e.g., bottom bias, source bias, RF power, etc.) to generate a plasma and then source and react gas. Is supplied to form the deposition oxide film 109 immediately without delay.

Through the above method, even if the aspect ratio of the trench 147 increases as the degree of integration increases, the inside of the trench 147 may be completely filled with an oxide film without generating voids in a conventional deposition apparatus.

Referring to FIG. 1J, the deposition oxide layer 109 on the pad nitride layer 103 is removed.

Referring to FIG. 1K, the pad nitride film 103 (FIG. 1I) on the pad oxide film 102 is removed. In this case, the pad nitride film 103 in FIG. 1I may be removed by a chemical mechanical polishing process. The polishing end point of the chemical mechanical polishing process is preferably set to the point where the detection amount of nitride decreases rapidly and the detection amount of oxide increases sharply. When the chemical mechanical polishing process is performed under these conditions, the upper portion of the deposition oxide film 109 protruding higher than the surface of the semiconductor substrate 101 may also be polished to obtain more excellent planarization characteristics.

Although not shown in the drawing, the pad nitride film 103 of FIG. 1I may be removed first, and then the deposition oxide film 109 protruding higher than the semiconductor substrate 101 may be removed.

As a result, an isolation layer 110 including only the thermal oxide film 108 and the deposition oxide film 109 is formed.

As described above, according to the present invention, after forming a trench in an isolation region of a semiconductor substrate, an oxide film is formed in a lower portion of the trench by a thermal oxidation process, and an oxide film is formed in an upper portion of the trench by a deposition method to form an isolation layer In addition, the lower portion of the trench having a high aspect ratio can be easily filled with an oxide film without voids while preventing the occurrence of buzz big, thereby further reducing the area of the device isolation region and improving the degree of integration.

Moreover, there is an advantage in that reproducibility of the process can be secured without the addition of expensive equipment.

Claims (11)

delete Forming a first trench in a device isolation region of the semiconductor substrate at a predetermined depth; Forming an antioxidant spacer on sidewalls of the first trenches; Etching the device isolation region of the semiconductor substrate to form a second trench of a target depth; Performing a thermal oxidation process to fill the second trench with a thermal oxide film; Removing the antioxidant spacer; And And depositing the first trench with a deposition oxide film. Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; Removing the pad nitride film and the pad oxide film in the device isolation region; Forming a first trench in the device isolation region to a predetermined depth; Forming an antioxidant spacer on sidewalls of the first trenches; Etching the device isolation region of the semiconductor substrate to form a second trench of a target depth; Performing a thermal oxidation process to fill the second trench with a thermal oxide film; Removing the antioxidant spacer; Filling the first trenches with a deposition oxide film; And And planarizing the pad nitride layer while removing the pad nitride layer by a chemical mechanical polishing process. The method of claim 2, wherein after forming the first trench and before forming the antioxidant spacer, And forming a liner oxide film on the sidewalls and the bottom of the first trench by a thermal oxidation process. The method of claim 2 or 3, The method of claim 1, wherein the anti-oxidation spacer is formed of nitride. The method of claim 2 or 3, And forming the nitride on the entire structure and then leaving the nitride only on the sidewalls of the first trenches by a front surface etching process. The method of claim 2 or 3, The method of claim 1, wherein the anti-oxidation spacer is removed by a wet etching method using phosphoric acid. The method of claim 2 or 3, And a predetermined bias is applied to the semiconductor substrate so that the anti-oxidation spacer generates ions and the ions collide with the semiconductor substrate. The method of claim 2 or 3, A device isolation film forming method of a semiconductor device wherein the deposited oxide film is a high density plasma oxide film. The method of claim 2 or 3, And forming said thermal oxide film, removing said anti-oxidation spacer, and forming said deposited oxide film in the same chamber. The method of claim 10, After the thermal oxidation process is performed in an oxygen atmosphere to form the thermal oxide film and the second trench is completely filled with the thermal oxide film, oxygen is blocked and the antioxidant spacer is removed by sputtering or reactive ion etching. A method of forming a device isolation layer in a semiconductor device, wherein the deposition oxide film is deposited by supplying a gas and a reactant gas and generating a plasma with a bias.

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