KR100564178B1 - Hierarchical coding method and apparatus for constant amplitude transmission in cdma communication system and device thereof - Google Patents

Abstract

According to the present invention, in a multi-code CDMA system that receives three N-squared (N is an integer) information bit strings as inputs and generates four N-squared encoded output bit strings, one spare bit is provided for each three-bit input in the first step. After generating the 4-bit coded output, the process is repeated recursively, and the coded output of 4 N-squares is input to the bandpass modulator (not shown) for the input of the N-bit information bits of 3. As the signal has the same amplitude, the structure of the transceiver is simplified, and the transmission signal in the code division multiple access communication system that enables the low cost implementation of the terminal due to the constant amplitude of the transmission signal while maintaining high information transmission rate per chip. A hierarchical constant amplitude encoding method and apparatus thereof are provided.

DS / CDMA, PW / CDMA, MP / CDMA, CS / CDMA, Orthogonal Code, Constant Amplitude, Multicode

Description

Hierarchical CODING METHOD AND APPARATUS FOR CONSTANT AMPLITUDE TRANSMISSION IN CDMA COMMUNICATION SYSTEM AND DEVICE THEREOF}

1 is a diagram showing the configuration of a DS / CDMA transmitter according to the related art.

2 is a view showing the configuration of a conventional pulse width CDMA (PW / CDMA) transmitter

3 is a diagram illustrating a method of converting a level of a conventional DS / CDMA signal into a pulse width of a PW / CDMA signal.

4 is a diagram illustrating a configuration of a conventional multiple phase CDMA (MP / CDMA) transmitter.

5 is a block diagram of a transmission signal encoding apparatus in a CS / CDMA communication system.

6 is a diagram when the number of input bits is 3 in the hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system according to the present invention.

7 is a diagram of a case where the number of input bits is 9 in a hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system according to the present invention;

8 is a diagram of a case where the number of input bits is N squares of 3 in the hierarchical constant amplitude encoding method of a transmission signal in a code division multiple access communication system according to the present invention;

<Explanation of symbols for main parts of drawing>

610: level converting section of Q (4) basic coding section

620: a margin bit generator of the Q (4) basic encoder

630: Multiplication unit of the Q (4) basic coding unit

640: Digital summing unit of the Q (4) basic coding unit

650: normalization part of the Q (4) basic coding part

700: distribution part of Q (16) extension coding part

710: Q (4) basic encoder

720: Free bit generator of Q (16) extended encoder

730: multiplier of the Q (16) extended encoder

740: digital summing unit of the Q (16) extension coding unit

750: Normalization unit of the Q (16) extended encoder

800: distribution part of the Q (L) extension encoder

810: Q (L / 4) lower encoder

820: margin bit generation unit of the Q (L) extension encoder

830: Multiplication unit of the Q (L) extension encoder

840: Digital summing unit of the Q (L) extension encoder

850: Normalization unit of the Q (L) extension encoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for hierarchical constant amplitude encoding of a transmission signal in a code division multiple access (CDMA) communication system. In addition, the present invention relates to a method and apparatus for hierarchical constant amplitude encoding of a transmission signal in a CDMA communication system for maintaining a constant amplitude of a signal. In other words, the present invention provides level clipping and complex M-ary phase shift keying (MPSK) modulation on a complex line to transmit a multilevel signal generated by adding multiple orthogonal codes in a conventional CDMA with a constant amplitude. Even if the orthogonal codes are added by encoding the input bit stream instead of using the method, the amplitude of the signal is constant, thus eliminating the need for the level limiting unit, and thus having a higher information rate per chip than the conventional CS / CDMA. The present invention relates to a method and apparatus for transmitting a signal using BPSK (Binary Phase Shift Keying) modulation.

General wireless transmission multiplexing techniques can be broadly classified into frequency division multiple access (FDMA), time division multiple access (TDMA), and code division multiple access (CDMA). .

Among them, the CDMA method has established itself as a global standardization method of the IMT-2000 system, which is called the third generation mobile communication because of its excellent characteristics.

The CDMA method used in mobile communication mainly uses a DS / CDMA (Direct Sequence / Code Division Multiple Access) method in which data is multiplied by a direct orthogonal code to spread a band. In a base station of a DS / CDMA system, signals of multiple channels are linearly summed and transmitted simultaneously. Adding the assigned binary sequence for each channel causes the amplitude of the signal to vary rather than be constant. As the number of channels increases, the number of levels of the output signal increases, so that the amplitude change range becomes larger than that of the analog signal, so that the power amplifier of the base station requires high linearity.

However, unlike the base station, the terminal of the second generation mobile communication uses only one orthogonal code, so that the level of the signal transmitted from the terminal is constant. In next-generation mobile communication, which provides multimedia services including data and video beyond voice-oriented services, even in a terminal used by a single user to support high data transmission speeds, multiple orthogonal channels can be used using multiple channels through serial and parallel converters. Multi-Code CDMA is used to simultaneously use codes, resulting in uneven levels of transmission signals. Therefore, the efficiency of the power amplifier is reduced, and many difficulties are expected to implement a low cost terminal device.

Accordingly, the PW / CDMA, MP / CDMA, and CS / CDMA methods have been proposed as a method for solving the problems caused by the signal level of the modulated signal becoming inconsistent when the transmission data is transmitted in a multicode method.

The most effective of these methods is known as the CS / CDMA method. The CS / CDMA method modulates data by selecting one of the orthogonal codes assigned to the block by using the transmitted data. If the number of channels is large, the number of codes to be stored becomes very large, so the CS / CDMA system is implemented by dividing into several blocks. Since the orthogonal codes output from each block are added, the modulated signal is also a multilevel signal. This multilevel signal can be converted into a signal having a constant amplitude by appropriately adding extra bits to the information bits using a larger number of channels than the number of input information bits. In the case of using four information channels, the information bit stream is divided into three blocks and transmitted to three information channels, and the other one information block is used as an encoding channel for transmitting spare bits as free blocks. The amplitude of the signal input to the pass modulator can be made constant. However, in the case of CS / CDMA, four information channels are required to transmit a 3-bit information bit string. In general, when the information bit string is increased by 6 bits, the number of information channels for transmitting the information increases by four times, which is inefficient because the information transmission rate per chip is low.

Hereinafter, with reference to the accompanying drawings looks at the prior art. 1 is a diagram illustrating a module configuration of a DS / CDMA transmitter based on multicode according to the prior art.

As shown in Fig. 1, the input signals d1, d2, ..., dn are respectively multiplied by the orthogonal code patterns c1, c2, ..., cn and the multipliers 1a, 1b, ... In the unit 100, all are summed and converted into an analog signal S having an (n + 1) level and sent to an RF (Radio Frequency) amplifier (not shown).

That is, in the conventional DS / CDMA method, the transmitting end multiplies each channel's data by multiplying different orthogonal codes, which are several tens to thousands of times faster than the information transmission speed, in order to simultaneously transmit information of several channels at the same frequency. Orthogonality is given so as not to interfere with each other, and then arithmetically summed to transmit several channels simultaneously at the same frequency.

Then, the receiving end receives the signal transmitted in this way, and then multiplies the received signal by the same code as the orthogonal code used in the desired channel, so that the information of the other unwanted channel disappears, leaving only the information of the desired channel.

In the conventional DS / CDMA method, the modulation signal level increases according to the number of orthogonal codes to be used. As a result, the system configuration becomes complicated and signal processing becomes difficult.

As a solution to this problem, PW / CDMA (Pulse) cuts the modulation signal level above a certain value (level limit) and transmits only the remaining level value by changing the pulse width so that the signal waveform is always binary. Width CDMA) (Patent No. 0293128; 2001.03.30) has been proposed.

2 is a diagram illustrating a module configuration of a PW / CDMA transmitter according to the prior art, and FIG. 3 is a signal for a method of converting a level of a conventional DS / CDMA signal into a pulse width of a PW / CDMA signal. The figure which shows a waveform.

As shown in FIG. 2, the level limiter 210 is used instead of the analog summer 100 of the direct spreading code division multiple access (DS / CDMA) method of FIG. After cutting a signal of a predetermined level or more, the pulse generator 220 is used to generate a modulated signal S in binary form using the method illustrated in FIG. 3.

The PW / CDMA method has a merit that a modulated signal has a binary value, but when the number of levels of the cut modulation signal is greater than 2, the bandwidth of the modulated signal increases in proportion to the number of levels.

A multiphase CDMA modulation and demodulation method and its apparatus (Patent Application No. 10-2001-58195: 2001.09.20) have been proposed to transmit CDMA signals of a multi-code method while eliminating these disadvantages.

4 is a diagram illustrating a module configuration of a conventional multiple phase CDMA (MP / CDMA) transmitter.

Comparing the difference between the configuration shown in FIG. 4 and the configuration shown in FIG. 2, various levels of signals produced by the conventional DS / CDMA method shown in FIG. The result of cutting the value is converted into a phase value by the phase converter 410 instead of the pulse generator 220. This converted phase value modulated signal is sent to an RF amplifier (not shown).

In other words, the PW / CDMA method has the advantage of simplifying the waveform, but when the number of remaining levels is greater than or equal to 2, the bandwidth of the modulated signal increases in proportion. The MP / CDMA method is to solve this problem. Instead, the MP / CDMA method replaces the remaining level value with the pulse width instead of the phase value of the transmitted RF signal.

Although the PW / CDMA and MP / CDMA methods cut the signal level of the DS / CDMA method by more than a predetermined size, the system can be simplified by preventing the increase of the signal level. However, the PW / CDMA and MP / CDMA methods also have DS. Like the / CDMA method, orthogonal codes are assigned to one information channel.

As a result, the DS / CDMA, PW / CDMA, and MP / CDMA methods use orthogonal codes equal to the number of information channels transmitted by assigning one orthogonal code to one data channel to be transmitted. There is a problem that the number of orthogonal codes increases and the level of modulated transmission signals increases.

In addition, the truncation of the multi-level signal has a disadvantage in that the orthogonality of the orthogonal code is impaired and thus vulnerable to mutual interference between transmitted signals.

A method and apparatus for encoding a transmission signal in a CS / CDMA communication system using a new modulation and demodulation method in which a amplitude of a generated signal is constant while using multicode, thereby eliminating a truncation process (Patent Application No. 10-2002-20158) 2002.04.12) was proposed. Instead of assigning one orthogonal code to one data channel, this method uses Hadamard code as orthogonal code and solves the problem of orthogonality between channels due to truncation. By creating a spare block composed of spare bits generated according to the information bit string input to the block, the size is kept constant even if the signals output from all four blocks are summed. This technique will be briefly described with reference to the accompanying drawings.

FIG. 5 is a block diagram of an apparatus for encoding a transmission signal in a CS / CDMA communication system. FIG. 5 shows a CS / CDMA encoding an information bit string and dividing an orthogonal code into block units to modulate data to produce a transmission signal having a constant amplitude. It is a figure which shows the structure of a modulator.

In the CS / CDMA method, the input information bit stream is converted into serial / parallel so that (N + 1) information channels are input to each of three blocks (N is a natural number), and each block is divided into (N +) blocks. 1) One of two N-square orthogonal codes is selected from N information channels among the information channels, and this code is multiplied by the data of the other channel. That is, N bits of information data determine an orthogonal code, and the remaining 1 bits of information data determine a sign. One spare block is used to make a multi-level signal formed by summing signals generated in each block by the block-based modulation method to a constant amplitude. The output obtained by inputting the (N + 1) spare bits made from the (3N + 3) information channels of the three information blocks to the spare block, which is the fourth block, and the output of the three information blocks, are summed to have a constant amplitude. Generates a transmission signal.

Orthogonal code portion A, B, C (500, 520, 540) is an orthogonal code portion to carry the information bits passed through a parallel, parallel converter (not shown), D (560) is the three orthogonal code portion 500 The redundant orthogonal code part carries redundant bit sequences after data input to the data sources 520 and 540 is encoded by the encoder 580.

Each orthogonal code part has (N + 1) input channels, and the information bit stream input thereto has data of 1 and 0. In each block, one of two N-squared orthogonal codes is selected from N input channel information (ie, N bit data). This orthogonal code has a length of 2 (N + 2) squares of chips, each element being 1 or -1. The information bits input to the other channel are converted into 1 by (+1) and 0 by (-1) in the polarity converting units 510, 530, 550, and 570 to be bipolar signals, multiplied by the selected orthogonal code, and digitally summed. Input to the unit 590.

Since the code is selected by N bits for each orthogonal code part, there are two N-square codes per block. Since there are four orthogonal code parts, M, the size of the Hadamard matrix, becomes a (N + 2) square of two. For example, if a code is selected with 2 bits per block (i.e., N = 2), the size of the Hadamard matrix is 16x16, and the selected orthogonal code has a length of 16 chips.

In the case of CS / CDMA, four information channels are required to transmit a 3-bit information bit string, and 16 information channels are required to transmit a 9-bit information bit string. In general, when the information bit string is increased by 6 bits, the number of information channels for transmitting the information increases by four times, which is inefficient because the information transmission rate per chip is low.

Accordingly, the present invention has been made to solve the above-mentioned problems according to the prior art, and an object of the present invention is to replace an information bit string input instead of performing level clipping on a multilevel signal in PW / CDMA or MP / CDMA. By adding several orthogonal codes by encoding, the amplitude of the signal is kept constant so that there is no need for level clipping, and as shown in Table 1 below, as the number of information bit strings increases in CS / CDMA per chip, Although the information transmission rate is drastically reduced to 3/4, 9/16, 15/64, ..., the method proposed in the present invention is such that the information transmission rate per chip is 3/4, 9/16, 27/64, ... A method and apparatus for hierarchical constant amplitude encoding of a transmission signal in a code division multiple access communication system maintaining N squares (N is an integer) of 3/4).

TABLE 1

The present invention focuses on maintaining the information rate per chip at an N-squared of (3/4) while solving the problem of inter-channel orthogonality caused by truncation caused by the use of level limiters for multilevel signals in conventional CS / CDMA. It consists of a recursive structure as a whole, and the top-level coder receives three N-squared information bit strings as inputs and divides them into three groups of three (N-1) -squared bits. Is sent to a lower-level encoding unit for encoding the input of (N-1) squares of three, and the lower encoding unit recursively divides the (N-1) squares of three inputs into three groups. Repeatedly, the three bit inputs are processed in the basic block of the last step to obtain four chip output signals with constant amplitude. Afterwards, as a reverse process of distribution, the output of three lower blocks and the output of one spare block are tied together to obtain 16 chip output signals. As such, the process of generating the upper block by combining the outputs of three blocks and the outputs of one spare block is repeated, and finally, an output of four N-squared chip output columns having a constant amplitude from three N-squared information bit strings of three is obtained. Create

SUMMARY OF THE INVENTION The present invention has been made to solve various problems according to the prior art, and an object of the present invention is to encode an input bit string instead of performing level clipping on a multilevel signal in PW / CDMA or MP / CDMA. By adding multiple orthogonal codes, the amplitude of the signal is kept constant so that there is no need for level clipping, and as the number of information bit strings increases in CS / CDMA, the information rate per chip is 3/4, 9/16, 15. / 64, ..., but the method proposed in the present invention, the information transfer rate per chip, such as 3/4, 9/16, 27/64, ... N square of (3/4) (N is an integer) The present invention provides a method and apparatus for hierarchical constant amplitude encoding of a transmission signal in a code division multiple access communication system.

In the code division multiple access communication system according to the present invention for achieving the above object, the method and apparatus for hierarchical constant amplitude encoding of a transmission signal include: a Q (4) basic encoder for processing three information bit streams, (4) An extended coding unit which extends the basic coding scheme to distribute the input bit strings of the N-squared three information bit strings of 3 to the lower coding unit, process them, and then add the spreading results to obtain a chip output having a constant amplitude. (4) The base encoder encodes one spare bit for three information bit streams, spreads them by using a 4 × 4 Hadamard code, and adds them to obtain four chip output signals having a constant amplitude. In 9, the input of the information bit string of 9 bits is divided into three groups of three bits, and each of the three bits is encoded by the base encoder to add a constant amplitude. Four chip outputs are produced, and the outputs of the 12 chips, which are the outputs of the three basic encoders, and the outputs of the four chip spare blocks generated therefrom are banded together using a 16 × 16 code of a similar Hadamard pattern, and then summed together to have a constant amplitude. 16 chip outputs are obtained, and when it is extended to the general case and processes N information squares of 3, the information bit stream is divided into 3 groups of 3 (N-1) squares of 3, each group Is sent to the lower coder Q (4 ^ (N-1)) for processing, and Q (4 ^ (N-1)) divides the (N-1) squares of 3 inputs into three groups again. Send it to the encoder for processing. In this way, the input is recursively sent to the lower encoder to be processed and summed up. Finally, the N-squared output strings of 4 having a constant amplitude are received as N-squared information bit strings of 3 as inputs. Create

That is, according to an aspect of the hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system according to the present invention for achieving the above object, the Q (4) basic encoding unit directly inputs three information bit streams. A level converting unit converting the signal level after the parallel / parallel switching; A margin bit generation unit configured to logically operate the three bits to generate one margin bit; A multiplier for multiplying the level-converted three information bits and one spare bit by a spreading code; A digital adder configured to add the multiplication results to generate four chip signals having a predetermined amplitude; It may include a normalizer for normalizing the magnitude of the chip signal having a predetermined amplitude and converting the chip signal into a chip signal having a magnitude of (+1) or (-1). The expansion encoding unit may include: a distribution unit dividing the N-squared information bit strings of 3 into 3 groups by 3 (N-1) squared bits; Recursively repeating the process of distributing (N-1) squares of 3 input bits and sending them to the Q (4 ^ (N-1)) lower encoder which processes the (N-1) squares of 3 input bits. A lower encoder for generating (N-1) square powers of a predetermined amplitude chip output of a; A margin bit generator for generating margin bits by performing a logical operation on an output of a lower encoder including the basic encoder; A multiplier for multiplying the outputs of the three lower encoders by the spread code by the outputs of the redundant bit generators; A digital adder which adds the multiplication result to produce a chip signal having a predetermined amplitude; It may include a normalization unit for normalizing the magnitude of the chip signal having a predetermined amplitude and converting the chip signal of the magnitude (+1) or (-1).

In addition, according to another aspect of the hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system according to the present invention for achieving the above object, the Q (4) basic encoding unit directly inputs three information bit streams. A level converting unit converting the signal level after the parallel / parallel switching; A margin bit generation unit configured to logically operate the three bits to generate one margin bit; A multiplier for multiplying the level-converted three information bits and one spare bit by a spreading code; A digital adder configured to add the multiplication results to generate four chip signals having a predetermined amplitude; It may include a normalization unit for normalizing the magnitude of the chip signal having a predetermined amplitude and converting the chip signal of the magnitude (+1) or (-1). The expansion encoding unit may include: a divider for dividing three information bit sequences of N squares of 3 into three (N-1) square groups of 3 bits at a time without recursively dividing the information bit streams of three; A Q (4) basic encoder for receiving three bits as input and generating four constant amplitude chip outputs; A margin bit generator for generating a margin bit by performing a logical operation on an output of a lower encoder including the basic encoder; A multiplier for multiplying the outputs of the three lower encoders by the spread code by the outputs of the redundant bit generators; A digital adder which adds the multiplication result to produce a chip signal having a predetermined amplitude; It may include a normalization unit for normalizing the magnitude of the chip signal having a predetermined amplitude and converting the chip signal of the magnitude (+1) or (-1).

On the other hand, according to one aspect of the hierarchical constant amplitude encoding method of a code division multiple access communication system transmission signal according to the present invention, the Q (4) basic encoding step is a signal level after the serial / parallel switching of the three information bit streams inputted A level converting step of converting; A margin bit generation step of logically operating the three bits to generate one margin bit; A multiplication step of multiplying said level-converted three information bits and said one spare bit by a spreading code; A digital summing step of adding up the multiplication result to produce four chip signals having a constant amplitude; A normalization step of normalizing the magnitude of the chip signal having the predetermined amplitude and converting the chip signal into a chip signal having a magnitude of (+1) or (-1) may be included. The extended encoding step may include: a dividing step of dividing the N-square information bit strings of 3 into three groups by three (N-1) squared bits; Recursively repeating the process of distributing the (N-1) squares of 3 input bits and sending them to the Q (4 ^ (N-1)) sub-coding step, which processes the (N-1) squares of 3 input bits. A lower encoding step of generating (N-1) square powers of four constant amplitude chips; A margin bit generation step of generating a margin bit by performing a logical operation on an output of a lower encoding step including the basic encoding step; A multiplication step of multiplying the outputs of the three lower coding steps and the outputs of the spare bit generation steps by a spreading code; A digital summing step of adding the multiplication results to produce a chip signal having a constant amplitude; A normalization step of normalizing the magnitude of the chip signal having the predetermined amplitude and converting the chip signal into a chip signal having a magnitude of (+1) or (-1) may be included.

In addition, according to another aspect of the hierarchical constant amplitude encoding method of a code division multiple access communication system transmission signal according to the present invention, the Q (4) basic encoding step includes a signal after serial / parallel switching of three input bit streams. A level converting step of converting a level; A margin bit generation step of logically operating the three bits to generate one margin bit; A multiplication step of multiplying said level-converted three information bits and said one spare bit by a spreading code; A digital summing step of adding up the multiplication result to produce four chip signals having a constant amplitude; A normalization step of normalizing the magnitude of the chip signal having the predetermined amplitude and converting the chip signal into a chip signal having a magnitude of (+1) or (-1) may be included. The expansion encoding step may include: a distribution step of dividing the N-bit information bits of 3 into groups of three (N-1) squares of 3 bits at a time without recursively dividing the information bit streams of 3; A basic encoding step of receiving three bits as an input and generating four constant amplitude chip outputs; A margin bit generation step of generating a margin bit by performing a logical operation on an output of a lower encoding step including the basic encoding step; A multiplication step of multiplying the outputs of the three lower coding steps and the outputs of the spare bit generation steps by a spreading code; A digital summing step of adding the multiplication results to produce a chip signal having a constant amplitude; The method may include a normalization step of normalizing the magnitude of the chip signal having a predetermined amplitude and converting the chip signal into a chip signal having a magnitude of (+1) or (-1).

The encoder according to the present invention receives an N-squared number of 3 bits having a value of 1 or 0 as an input and is spread using a spreading code, and then the magnitude of the summed signal does not undergo truncation (+1) or (-1 The N-square chip signals of 4 having a constant amplitude value of) are output. The inputs of N squares of 3 are not spread out at a time, but the input strings of N squares of 3 are divided into 3 groups of bits of (N-1) squares of 3, and then each group is divided into 3 (N It is sent to the lower encoder which receives -1) bits as input. The lower encoder recursively repeats the process of dividing its input into three groups and sending it to the lower encoder for processing. In the final step, the code is divided into three bits and encoded to produce four chip signals with a constant amplitude. In this way, a series of processes for producing four chips having a constant amplitude from three input bits become one basic encoder. The outputs of these three basic encoders and the extra bits obtained therefrom are then spread together and summed to obtain a constant. Create 16 chip signals with amplitude. Thereafter, the output of the encoder consisting of 16 chip signals and the extra bits obtained therefrom are spread by band spreading and summing to generate 4 N-squared output chip signals having a constant amplitude.

Hereinafter, a method and apparatus for hierarchical constant amplitude encoding of a transmission signal in a code division multiple access communication system according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 illustrates a configuration of a Q (4) basic encoder for generating four chip signals having a constant amplitude by receiving input of 3 bits in a hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system according to the present invention. The figure shown. 4 of Q (4) means that the output is four chips with constant amplitude, and Q (4) is at the lowest structure in the hierarchical encoder.

와 곱해진 후 디지털 합산부(640)에서 합해져 (+2) 혹은 (-2)의 일정한 진폭을 가지게 되며, 정규화부(650)에서 정규화되어 (+1) 혹은 (-1)의 값으로 변화된다.The level converter 610 receives three input bit strings b ₀ , b ₁ , and b ₂ having a value of 1 or 0, converts a level from 1 to (+1) and 0 to (-1), and then parallelizes them. A block for generating signals of d ₀ , d ₁ , and d ₂ , and the margin bit generator 620 is a block for generating the margin bit d ₃ by using Equation 1 from d ₀ , d ₁ , and d ₂ . Four bits of d ₀ , d ₁ , d ₂ , and d ₃ are orthogonal code patterns each consisting of four chips in the multiplier 630.

After multiplying by and adding in the digital summing unit 640 and having a constant amplitude of (+2) or (-2), it is normalized in the normalizing unit 650 and changed to a value of (+1) or (-1). .

의 값을 수학식 2에 나타내었는데, 이들의 값은 실제로 4 ×4 Hadamard 행렬의 각 행과 동일하다. d ₀,d ₁,d ₂,d ₃ 가

를 사용하여 확산된 후 더해진 출력, S⁴ =[s ₀,s ₁,s ₂ ,s ₃]의 각 비트 s ₀,s ₁,s ₂, s ₃ 는 모두 (+2) 혹은 (-2)의 일정한 값이 됨을 수학식 2에서 증명하였다. 계층적 부호화는 하위 부호화부의 출력을 상위 부호화부의 입력으로 사용하므로, 하위 부호화부의 출력을 (+1) 혹은 (-1)의 값으로 제한하기 위해, S⁴의 값을 정규화부에서 (+2)의 값은 (+1)로, (-2)의 값은 (-1)로 정규화시켜 최종적인 Q(4)의 출력은 (+1) 혹은 (-1)의 값을 갖는 4 칩의 출력 t⁴ ＝[t ₀,t ₁,t ₂, t ₃]이 된다.Orthogonal Code Pattern

Equation 2 is shown in Equation 2, which is actually equal to each row of the 4x4 Hadamard matrix. d ₀ , d ₁ , d ₂ , d ₃

Output after spreading using, S ⁴ = [ s ₀ , s ₁ , s ₂ , s ₃ ], each bit s ₀ , s ₁ , s ₂ , s ₃ are all (+2) or (-2) Equation 2 proved to be a constant value of. Since hierarchical coding uses the output of the lower encoder as the input of the upper encoder, in order to limit the output of the lower encoder to a value of (+1) or (-1), the value of S ⁴ is equal to (+2) in the normalizer. The value of (+1) is normalized to (-1), and the value of (-2) is normalized to (-1) so that the final output of Q (4) is (+1) or (-1). ⁴ = [ t ₀ , t ₁ , t ₂ , t ₃ ].

7 is a diagram illustrating a configuration of a Q (16) extended encoder for generating 16 chip signals having a constant amplitude by receiving 9-bit input in a hierarchical encoding apparatus of a transmission signal in a code division multiple access communication system according to the present invention. to be.

＝(b ₀,b ₁,b ₂),

＝(b ₃,b ₄,b ₅),

＝(b ₆,b ₇,b ₈)의 세 그룹으로 나누어진 후, 3 비트씩 Q(4) 기본 부호화 부에 의하여 부호화된 후, 4 칩 단위로 여유 비트를 생성한 후 함께 확산된 후 합산되어 16 개의 칩 출력 신호를 만들어 낸다.9-bit input b ⁹ = ( b ₀ , b ₁ , Λ, b ₈ ) with unipolar value (1 or 0)

= ( B ₀ , b ₁ , b ₂ ),

= ( B ₃ , b ₄ , b ₅ ),

= Divided into three groups ( b ₆ , b ₇ , b ₈ ), encoded by the Q (4) basic coding unit by 3 bits, and then generated with the 4-bit unit, and then spread together and then summed. To produce 16 chip output signals.

를 만들어 내는데, 여유 비트 생성부(720)는

로 부터 4 비트의 여유 비트,

를 생성한다. 수학식 5에 나타낸 바와 같이 네 개의 4 칩 벡터

는 곱셈부에서 각각 4 ×16 행렬 구조의 유사 Hadamard 코드 패턴

와 4 칩 단위로 곱해진 후, 디지털 합산부(740)에서 합해져 (+2) 또는 (-2)의 일정한 진폭을 가진 16 칩 신호 S¹⁶ ＝[s ₀,s ₁,Λ,s ₁₅]가 만들어지며, S¹⁶은 정규화 부(750)에서 정규화 되어 (+1) 또는 (-1)의 값을 갖는 16 칩 출력 t¹⁶=[t ₀,t ₁,Λ,t ₁₅]이 생성된다.The distribution unit 700 divides the 9-bit input into three groups, and then sends each group to the Q (4) basic encoder for processing. Q (4) basic encoders A, B, and C each have 4 chips

To create a spare bit generator 720

4 bits of free bits from,

Create Four 4-chip vectors as shown in equation (5)

Hadamard code pattern similar to each of the 4 × 16 matrix structures in the multiplier

And multiplied by 4 chips, and then summed by the digital adder 740 to have a 16 chip signal S ¹⁶ having a constant amplitude of (+2) or (-2). = [ S ₀ , s ₁ , Λ, s ₁₅ ] is generated, S ¹⁶ is normalized in the normalization section 750 and outputs 16 chips with values of (+1) or (-1) t ¹⁶ = [ t ₀ , t ₁ , Λ, t ₁₅ ] are generated.

을 수학식 4에 나타내었는데, 각각은 4 x 16 행렬의 구조를 갖고 있으며,

로 이루어지는 행렬은 전체적으로 4 ×4 Hadamard 행렬의 구조에서 각 단위 요소를 4 ×4 크기의 Identity 행렬로 대체한 모습을 띠고 있다. 따라서

은 직교코드패턴은 아니며, 유사 Hadamard 코드패턴 이다.Code pattern

In Equation 4, each has a structure of a 4 x 16 matrix,

The matrix consists of 4 x 4 Hadamard matrix, each unit element is replaced with 4 x 4 identity matrix. therefore

Is not an orthogonal code pattern, it is a pseudo Hadamard code pattern.

는 4 칩 단위로

에 대해 수학식 6에 의하여 EXOR 연산과 보수 연산을 행해 얻는다. 여유 비트 벡터

를 얻는 방법은 Q(4)일 때와 다르다. Q(4) 기본 부호화 부는 레벨 변환된 입력 3 비트에 대해서

의 식에 의하여 여유 비트 d ₄ 를 생성하였으나, Q(16) 확장 부호화 부의 여유 비트 벡터

는 9 비트의 입력에 대해 직접 EXOR 연산을 행하여 구하지 않고, 각각의 3 비트에 대하여 먼저 Q(4) 기본 부호화부의 출력

을 구하고 이들에 대해 4 칩 단위로 EXOR 연산을 행하여

를 얻는다.Free bit vector

In units of 4 chips

Is obtained by performing the EXOR operation and the complementary operation according to Equation (6). Free bit vector

The method of obtaining is different from that of Q (4). The Q (4) basic coding unit is for the level-converted input three bits.

Although the margin bit d ₄ is generated by the following equation, the margin bit vector of the Q (16) extended encoder is

The output of the Q (4) basic encoder is first obtained for each 3 bits without performing an EXOR operation directly on a 9-bit input.

, And perform an EXOR operation on each of these 4 chip units

Get

가

와 곱해진 후 이를 합해서 얻은 16 칩신호 S¹⁶ ＝[s ₀,s ₁,Λ,s ₁₅]의 각각의 칩들의 값은 항상 (+2) 혹은 (-2)가 됨을 수학식 6에서 증명하였다.

end

16 chip signal S ¹⁶ multiplied by and summed Equation 6 shows that the values of the chips of [ s ₀ , s ₁ , Λ, s ₁₅ ] are always (+2) or (-2).

The Q (4) basic encoder that produces four chip signals for three-bit input and the Q (16) extended encoder that produces sixteen chip signals for nine-bit input have been described so far. We will extend the general method of generating 4 N-squared chip signals for 3 N-squared inputs.

FIG. 8 is an N of 4 squared signals having a constant amplitude of 4 N squared constant inputs in a hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system according to the present invention. It is a figure which shows the structure of a square chip Q (L) extension coding part. For the convenience of notation, N squares of 4 are simply expressed as L, and N squares of 3 are expressed as M.

＝(b ₀,b ₁,Λ,b _{( M /3-1)}),

＝(b _{M /3},b _{M /3+1},Λ,b _{2 M /3-1}),

＝(b _{2 M /3},b _{2 M /3+1} ,Λ,b _{M -1})의 세 그룹으로 나누어진 후, M/3 비트 단위로 Q(L/4)에 의하여 부호화된 후, L/4 칩 단위로 여유 비트를 생성한다. M bit inputs with unipolar (1 or 0) values b ^M = ( b ₀ , b ₁ , Λ, b _{M -1} )

= ( B ₀ , b ₁ , Λ, b _{( M / 3-1)} ),

= ( B _{M / 3} , b _{M / 3 + 1} , Λ, b _{2 M / 3-1} ),

== ( b _{2 M / 3} , b _{2 M / 3 + 1} , Λ, b _{M -1} ) divided into three groups, then encoded by Q ( L / 4) in M / 3 bit units, and then L Spare bits are generated in units of 4 chips.

를 만들어 내는데, 최상위의 여유 비트 생성부(820)는

로부터 L/4 개의 여유 비트,

를 생성한다. 네 개의 L/4칩 벡터

는 곱셈부에서 각각 L/4 x L행렬 구조의 유사 Hadamard 코드 패턴

와 곱해져, 디지털 합산부(840)에서 합해져 (+2) 혹은 (-2)의 일정한 진폭을 가진 L 칩 신호 S^L ＝[s ₀,s ₁,Λ,s _{L -1}] 가 만들어지며, S^L은 정규화 부(850)에서 (+1) 혹은 (-1)로 정규화 되어 L 칩 출력 t^L ＝[t ₀,t ₁,Λ, t _{L -1}]이 생성된다.The distribution unit 800 divides the input of M bits into three groups, and then sends each group to Q ( L / 4) for processing. The Q ( L / 4) extension encoders A, B, and C each have an output of L / 4 bits.

To generate the uppermost free bit generator 820

L / 4 free bits,

Create Four L / 4 Chip Vectors

Hadamard code pattern similar to the L / 4 x L matrix structure in the multiplier respectively

Multiplied by and combined in the digital adder 840 to produce an L chip signal S ^L = [ s ₀ , s ₁ , Λ, s _{L -1} ] with a constant amplitude of (+2) or (-2), S ^L is normalized to (+1) or (-1) in the normalization unit 850 to generate L chip output t ^L = [ t ₀ , t ₁ , Λ, t _{L -1} ].

을 수학식 8에 나타내었는데,

의 각각은 L/4 x L 행렬의 구조를 갖고 있으며,

의 열로 이루어지는 행렬은 수학식 7에서 알 수 있는 바와 같이 전체적으로 4 x 4 Hadamard 행렬의 구조에서 각 단위 요소를 L/4 x L/4 크기의 Identity 행렬로 대체한 모습을 띠고 있다. Q(16) 확장 부호화부와 마찬가지로, 은 유사 Hadamard 코드 패턴이다.Similar Hadamard Code Patterns

Is represented in Equation 8,

Each of has the structure of an L / 4 x L matrix,

As can be seen from Equation 7, the matrix composed of columns is replaced by an identity matrix of size L / 4 x L / 4 in the structure of the 4 x 4 Hadamard matrix. Like the Q (16) extended encoder, Is a similar Hadamard code pattern.

는 L/4 칩 단위로

에 대해 수학식 9에 의하여 EXOR 연산과 보수 연산을 행해 얻는다. 상기 Q(4) 기본 부호화 부 또는 Q(16) 확장 부호화 부의 경우와 마찬가지로,

가

와 곱해진 후 이를 합해서 얻은 L 칩 신호 S^L ＝[s ₀,s ₁,Λ,s _{L -1}]의 각각의 칩들의 값은 항상 (+2) 혹은 (-2)가 된다.Free bit vector

In L / 4 chips

Is obtained by performing EXOR operation and complementary operation according to Equation (9). As in the case of the Q (4) basic encoder or the Q (16) extended encoder,

end

After multiplying by and summation, the value of each chip of L chip signal S ^L = [ s ₀ , s ₁ , Λ, s _{L -1} ] is always (+2) or (-2).

6, 7 and 8 are summarized as follows: The Q ( L ) extension encoder which processes M input bits first divides the entire input to form three groups of M / 3 bits, and then Q ( L ) A Q ( L / 4) encoder which processes an input of a third size of the extension encoder may process each input group. The Q ( L / 4) encoder divides the received input into three blocks so that each block is processed by the Q ( L / 4) encoder which processes an input of a quarter of Q ( L / 4). do. By repeating this process recursively, the 3-bit input is finally processed by the Q (4) basic encoder to obtain four chip signals with a constant amplitude. Four spare bits are generated from the outputs of the three Q (4) basic encoders, which are spread together and then summed to produce a signal of constant amplitude. As an extension of this, 16 spare bits are made from the outputs of the three Q (16) extension encoders, and these are spread together and summed to obtain a chip signal having a constant amplitude. This process is repeated recursively to obtain L chip signals with a constant amplitude.

[Equation 1]

The following table lists the possible values of d ₀ , d ₁ , d ₂ , and d ₃ .

[Equation 2]

를 사용하여 확산된 후 합해진 4 칩 신호 S⁴ ＝[s ₀,s ₁,s ₂,s ₃]는 다음과 같이 주어지며, 이를 벡터와 행렬을 사용하 여 나타내면 수학식 3과 같다.Bipolar bits d ₀ , d ₁ , d ₂ , d ₃ are

The four-chip signal S ⁴ = [ s ₀ , s ₁ , s ₂ , s ₃ ], which is spread after using D and S, is given by Equation 3 below.

Looking at the table of Equation 1, it can be seen that among the four bits of d ₀ , d ₁ , d ₂ , and d ₃ , three bits always have the same value and the other one has the opposite value. Using this fact, we can prove that s ₀ , s ₁ , s ₂ , and s ₃ are both (+2) or (-2):

d ₀ , d ₁ , d ₂ , and d ₃ have values of (+1) or (-1), where s ₀ is the sum of d ₀ , d ₁ , d ₂ , d ₃ , three of which are equal and the remainder Since one is different, the value of s ₀ is either (+2) or (-2). s ₁ is the sum of d ₀ and d ₂ minus the sum of d ₁ and d ₃ . In this case, if the signs of d ₀ and d ₂ are the same, the signs of d ₁ and d ₃ are different from each other, and the sum of the two is 0. Then s ₁ is the sum of d ₀ and d ₂ , which have the same value, so the size is (+2) or (-2). On the contrary, if d ₀ and d ₂ have different signs, s ₁ is the complement of d ₁ and d ₃ having the same value, and thus the magnitude is (+2) or (-2). We can prove in a similar way that the values of the remaining outputs s ₂ and s ₃ are (+2) or (-2).

The following table shows that when the values of d ₀ , d ₁ , and d ₂ change, s ₀ , s ₁ , s ₂ , and s ₃ are always (+2) or (−2).

[Equation 3]

S ⁴ = [ S ₀ , S ₁ , S ₂ , S ₃ ] = [ d ₀ , d ₁ , d ₂ , d ₃ ] H ₄

H ₄ is a 4 x 4 Walsh-Hadamard matrix.

[Equation 4]

로서 4 x 4의 Identity 행렬을 의미한다.From here,

As an identity matrix of 4 x 4.

가

와 곱해진 후 이를 합해서 얻은 16 칩 신호 출력 S¹⁶ ＝[s ₀,s ₁,Λ,s ₁₅] 을 4 칩 벡터

단위로 구분해서 표현하면 수학식 5와 같다.Outputs of the Q (4) base encoder

end

Multiply by and add the 16-chip signal output S ¹⁶ = [ s ₀ , s ₁ , Λ, s ₁₅ ] to a 4-chip vector

When expressed in units as shown in Equation (5).

[Equation 5]

If this is expressed as determinant, it is as follows.

Here, l ₄ means an identity matrix of 4 x 4.

[Equation 6]

If the above expression is expressed differently, it is as follows.

와 패리티 벡터

의 각 원소가 다음과 같을 때,therefore

And parity vector

When each element of is

t ₀ , t ₁ , Λ, t ₁₅ The following relationship holds between the livers.

의 각각의 원소 칩들의 값은 항상 (+2) 또는 (-2)가 된다. 따라서, 16 칩 신호 S¹⁶ ＝[s ₀,s ₁,Λ,s ₁₅]의 각각의 칩들의 값은 항상 (+2) 또는 (-2)가 된다.Therefore, the four chip vectors shown in Equation 5 by the same logic as in the case of the Q (4) basic coding unit

The value of each elemental chip of is always (+2) or (-2). Thus, the value of each chip of the 16 chip signal S ¹⁶ = [ s ₀ , s ₁ , Λ, s ₁₅ ] is always (+2) or (-2).

[Equation 7]

으로서 L/4 x L/4의 Identity 행렬을 의미한다.

This is the identity matrix of L / 4 x L / 4.

가

와 곱해진 후 이를 합해서 얻은 L 칩 신호 출력 S^L ＝[s ₀,s ₁,Λ,s _{L -1} ]을 L/4 칩 벡터

단위로 구분해서 표현하면 수 학식 8과 같다.

end

L chip signal output S ^L = [ s ₀ , s ₁ , Λ, s _{L -1} ] that is multiplied by and summed up to L / 4 chip vector

When expressed in units, it is as shown in Equation 8.

[Equation 8]

If the output S ^L = [ s ₀ , s ₁ , Λ, s _{L -1} ] is divided into four parts:

는 다음과 같은 식으로 계산된다.

는 Q(L/4) 부호화부의 출력 벡터들이며,

는 L/4 칩 단위의 여유 비트 벡터이다.

Is calculated by the equation

Are output vectors of the Q ( L / 4) encoder,

Is the margin bit vector in L / 4 chip units.

If this is expressed as determinant, it is as follows.

Here, l _{L / 4} means an identity matrix of L / 4 x L / 4.

[Equation 9]

If the above expression is expressed differently, it is as follows.

(L/4 개의 1로 구성)

( Consisting of L / 4 one)

The terms used to describe the embodiments of the present invention above are used for the purpose of describing the present invention, and are not used to limit the scope of the present invention as defined in the claims or the claims.

In the code division multiple access communication system according to the present invention as described above, the method and apparatus for hierarchical constant amplitude encoding of a transmission signal encodes input data bits so that the amplitude of the linear combination of orthogonal codes is constant, thereby eliminating the level clipping process. This eliminates the problem of orthogonality due to level clipping. In addition, in conventional CS / CDMA, the information rate per chip is drastically reduced to 3/4, 9/16, 15/64, 21/256 ..., but the present invention maintains the information rate per chip at (3/4) N squared. Has excellent performance (see Table 1 above).

In addition, because bandpass modulation is also required using BPSK, the structure of the transceiver is simplified and the amplitude of the transmission signal is constant so that the linearity of the terminal power amplifier is not required. .

Claims (10)

A recursive extension encoding unit for 3 ^ N (N squares of 3) information bit streams; a divider for dividing an input into 3 groups of 3 ^ (N-1) bits in Q (4 ^ N); Recursively repeating the process of sending the output of the distribution unit to the Q (4 ^ (N-1)) sub-coder, which processes 3 ^ (N-1) input bits, to output 3 ^ (N-1) three A level converter for converting a signal level from (1/0) to (+ 1 / -1) after the serial / parallel switching of Q (4 ^ (N-1)) for the information bit string;

To

One free bit with a value of (+1) or (-1)

A margin bit generation unit configured to generate a margin bit;

A basic coded multiplier that multiplies four bits by a 4 x 4 Hadamard code and spreads, a basic coded digital adder that adds a multiplication result by the basic coded multiplier to produce four chip signals having a constant amplitude, and the basic coded digital A basic encoding unit which is the lowest structure of the lower encoding unit in the hierarchical encoding consisting of a basic encoding normalization unit that normalizes the output of the adder to generate outputs of four constant amplitude chips having a value of (+1) or (-1); Output of a lower encoder including a basic encoder that is a substructure of the lower encoder

In bits

Logical bits by (L / 4) free bits with a value of either (+1) or (-1)

A margin bit generation unit for generating a; Output of the three lower encoders

And output of the margin bit generator

About

beat

To

x

A multiplier for multiplying with a pseudo Hadamard code; A digital adder configured to add a multiplication result of the multiplier to generate a chip signal having a predetermined amplitude; Normalizing the output of the digital summing unit has a constant level of (+1) or (-1)

Hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system for generating 4 ^ N constant amplitude chips, including a normalization unit for generating an output of the bit. delete delete A non-recursive extension coding unit for 3 ^ N information bit streams, wherein Q (4 ^ N) is a distribution unit for dividing an input into 3 ^ (N-1) groups of 3 bits at a time; For the three information bit streams in which the three information bit streams of the divided groups are input to 3 ^ (N-1), Q (4) changes the signal level from (1/0) to (+) after serial / parallel switching. A level converting section for converting to 1 / -1) and an output of the level converting section

To

One free bit with a value of (+1) or (-1)

A margin bit generation unit configured to generate a margin bit;

A basic coded multiplier that multiplies four bits by a 4 x 4 Hadamard code and spreads, a basic coded digital adder that adds a multiplication result by the basic coded multiplier to produce four chip signals having a constant amplitude, and the basic coded digital A basic encoding unit which is the lowest structure of the lower encoding unit in the hierarchical encoding consisting of a basic encoding normalization unit that normalizes the output of the adder to generate outputs of four constant amplitude chips having a value of (+1) or (-1); Output of a lower encoder including a basic encoder that is a substructure of the lower encoder

In bits

Logical bits by (L / 4) free bits with a value of either (+1) or (-1)

A margin bit generation unit for generating a; Output of the three lower encoders

And output of the margin bit generator

About

beat

To

x

A multiplier for multiplying with a pseudo Hadamard code; A digital adder configured to add a multiplication result of the multiplier to generate a chip signal having a predetermined amplitude; Normalizing the output of the digital summing unit has a constant level of (+1) or (-1)

Hierarchical constant amplitude encoding apparatus of a transmission signal in a code division multiple access communication system for generating 4 ^ N constant amplitude chips, including a normalization unit for generating an output of the bit. A recursive extended encoding step of 3 ^ N (N squares of 3) information bit streams may include: a distribution step of dividing an input into three groups of 3 ^ (N-1) bits in Q (4 ^ N); Recursively repeating the process of sending the output of the distribution step to the Q (4 ^ (N-1)) sub-coding step, which processes 3 ^ (N-1) input bits, to input 3 ^ (N-1) A level converting step of converting a signal level from (1/0) to (+ 1 / -1) after the serial / parallel switching of Q (4 ^ (N-1)) for three information bit streams; Output of steps

To

One free bit with a value of (+1) or (-1)

A margin bit generation step of generating a signal; and output information bits of the level conversion step and the margin bits

A basic coded multiplication step of multiplying 4 bits by a 4 x 4 Hadamard code and spreading, a basic coded digital summing step of adding four multiplication results in the basic coded multiplication step to produce four chip signals having a constant amplitude, and the basic coded digital signal In the hierarchical encoding consisting of a basic encoding normalization step that normalizes the output of the summing step and produces an output of four constant amplitude chips having a value of (+1) or (-1), the basic coding, which is the lowest step of the lower coding step, step; Output of a lower encoding step including a basic encoding step which is a lower step of the lower encoding step

In bits

Logical bits by (L / 4) free bits with a value of either (+1) or (-1)

A margin bit generation step of generating; Output of the three lower coding stages

And the output of the above margin bit generation step

About

beat

To

x

A multiplication step of multiplying and spreading by a similar Hadamard code; A digital summing step of adding a multiplication result of the multiplication step to generate a chip signal having a predetermined amplitude; Normalizing the output of the digital summing step has a constant level of (+1) or (-1)

And a normalization step of generating an output of the bit; hierarchical constant amplitude encoding method of a transmission signal in a code division multiple access communication system generating 4 ^ N constant amplitude chips. delete delete delete delete A non-recursive extended encoding step of 3 ^ N information bit streams, Q (4 ^ N) is a distribution step of dividing an input into 3 ^ (N-1) groups of 3 bits at a time; For the three information bit streams in which the three information bit streams of the divided groups are input to 3 ^ (N-1), Q (4) changes the signal level from (1/0) to (+) after serial / parallel switching. 1 / -1) level conversion step and the output of the level conversion step

To

One free bit with a value of (+1) or (-1)

A margin bit generation step of generating a signal; and output information bits of the level conversion step and the margin bits

A basic coded multiplication step of multiplying 4 bits by a 4 x 4 Hadamard code and spreading, a basic coded digital summing step of adding four multiplication results in the basic coded multiplication step to produce four chip signals having a constant amplitude, and the basic coded digital signal In the hierarchical encoding consisting of a basic encoding normalization step that normalizes the output of the summing step and produces an output of four constant amplitude chips having a value of (+1) or (-1), the basic coding, which is the lowest step of the lower coding step, step; Output of a lower encoding step including a basic encoding step which is a lower step of the lower encoding step

In bits

Logical bits by (L / 4) free bits with a value of either (+1) or (-1)

A margin bit generation step of generating; Output of the three lower coding stages

And the output of the above margin bit generation step

About

beat

To

x

A multiplication step of multiplying and spreading by a similar Hadamard code; A digital summing step of adding a multiplication result of the multiplication step to generate a chip signal having a predetermined amplitude; Normalizing the output of the digital summing step has a constant level of (+1) or (-1)

And a normalization step of generating an output of the bit; hierarchical constant amplitude encoding method of a transmission signal in a code division multiple access communication system generating 4 ^ N constant amplitude chips.

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