KR100563418B1 - Communication controller and method - Google Patents

Abstract

Provided are a communication controller and a communication method capable of suppressing occurrence of a state of rejection between a communicating host and communicating information on a packet basis. The communication controller according to the present invention is a communication controller that receives, in a packet unit, information corresponding to a plurality of communication modes having different amounts of information contained in one packet, and temporarily stores and stores the received information temporarily. Means and control means for controlling the number of packets to be stored in the storage means in accordance with the communication mode, wherein the control means stores a plurality of packets in the storage means in a communication mode in which a plurality of packets can be stored in the storage means. To temporarily store a plurality of packets in the storage means.

Packet, Controller, USB Interface

Description

Communication controllers and communication methods {COMMUNICATION CONTROLLER AND METHOD}

1 is a schematic block diagram of a communication system in an embodiment of the present invention;

2 is a schematic diagram showing data in an embodiment of the present invention.

Fig. 3 is a chart showing a communication format of a communication system in the embodiment of the present invention.

Fig. 4 is a schematic diagram showing a storage state of a packet buffer of a communication system in the embodiment of the present invention.

Fig. 5 is a schematic diagram showing a storage state of a packet buffer of a communication system in the embodiment of the present invention.

Fig. 6 is a schematic diagram showing a storage state of a packet buffer of a communication system in the embodiment of the present invention.

Fig. 7 is a chart showing control of the storage state of the packet buffer of the communication system in the embodiment of the present invention.

(Description of Major Symbols in the Drawing)

10: device controller 11: USB interface unit

12: endpoint controller 13: external bus interface unit

14: Transmission controller 15: PHY side control unit for transmission

16: toggle plug portion 17 for transmission; BCU side control unit for transmission

18: transmission buffer interface unit 19: reception control unit

20: reception PHY side control unit 21: reception toggle plug section

22: control unit for reception BCU 23: buffer interface unit for reception

24: buffer control unit 25: memory

38: transaction data 38a: token packet

38b: data packet 38c: handshake packet

42a1, 42a2, 42a3, 42a4, 42a5, 42a6, 42a7, 42a8: Packet

42a1, 42a2, 42a3, 42a4, 42a5, 42a6, 42a7, 42a8, 42a9, 42a10, 42a11, 42a12, 42a13, 42a14, 42a15, 42a16: Packet Buffer

The present invention relates to a communication controller and a communication method, and more particularly, to a communication controller and a communication method for communicating information in the form of a packet.

Conventionally, when connecting a computer main body and a peripheral device, it connects using a peripheral device interface, such as a serial interface and a parallel interface. In addition, a serial interface such as USB (Universal Serial Bus) or IEEE1394 has emerged as an interface for connecting a plurality of peripheral devices into one, and has been moving toward a unified interface and commonization.

In today's information society, the data transfer rate is higher than the USB1.x standard, such as the USB1.0 standard (USB-1F: USB Implements Forum), due to the necessity of communicating a large amount of data at high speed. The USB2.0 specification is being developed. In the conventional USB 1.x standard, the maximum data transfer rate is 12 Mbps in full speed mode (hereinafter referred to as FS mode) and 1.5 Mbps in low speed mode (hereinafter referred to as LS). In the state of maintaining these modes in the USB 2.0 standard, a new High Speed mode (hereinafter referred to as HS mode) with a maximum data transfer rate of 480 Mbps is added. Enables the communication of large amounts of data at high speed.

In a function device using such a USB 2.0 standard, for example, when 512 byte memory is connected in HS mode, 512 byte memory can be used in a 1 packet buffer configuration. In addition, when 512 bytes of memory are connected in FS mode, 64 bytes can be used in a 1 packet buffer configuration. 512 bytes of memory can be treated as 1 packet buffer in HS mode connection or FS mode connection. In FS mode, the maximum packet size for bulk transfers is 64 bytes and the remaining 448 bytes are not used.

When connected in FS mode, the buffer of the system configured with the function device is treated as one packet buffer of 512 byte memory, but 64 bytes are used and the remaining 448 bytes are not used, and the entire 512 bytes of one packet buffer are used. Data may be recorded or data may be read. Therefore, while writing data to or reading data from the buffer, the buffer cannot be accessed from the outside, resulting in a complete NAK (Negative Response) response by making an IN or OUT request to the host. do. When a NAK response occurs, a request for retransmission of the packet is requested to the host making a USB connection, and a transmission wait for retransmission from the host occurs. In addition, when the USB buffer cannot be accessed from the outside, packet corruption or packet loss occurs and a NAK response occurs while executing an IN request or an OUT request to a host to which a USB connection is made.

In the conventional information communication executed in the packet unit as described above, since there is no change in the number of packets storing the packet information according to the communication mode, a portion where the information cannot be stored despite the empty state is generated. There was a problem that a condition of rejection to a host communicating information could not be accessed due to inaccessibility.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and provides a communication controller and a communication method capable of suppressing occurrence of a rejection state with a communicating host when communicating information on a packet basis. For the purpose of

The communication controller according to the present invention is a communication controller that receives, in a packet unit, information corresponding to a plurality of communication modes having different amounts of information contained in one packet, temporarily stores the information, and stores the received information temporarily. Means (for example, the memory 25 in the present embodiment) and control means (for example, the buffer control unit 24 in the present embodiment) for controlling the number of packets to be stored in the storage means in accordance with the communication mode. In the communication mode in which the plurality of packets can be stored in the storage means, the control means sets a storage location of the plurality of packets in the storage means and temporarily stores the plurality of packets in the storage means. With such a configuration, it is possible to suppress the occurrence of the rejection state by controlling and changing the number of packets of the storage means for storing the information received in units of packets in accordance with the communication mode.

Further, in the case of a communication mode in which a plurality of packets can be stored in the storage means, the control means preferably changes the storage state of the packets by changing the storage location of the packets in the storage means. This makes it possible to efficiently store the information by appropriately adjusting the storage location for storing the information received in the packet unit in the storage means according to the communication mode.

The above-mentioned information transmitted and received is communicated via a universal serial bus, and the universal serial bus is preferably a USB2.0 standard or higher. Thus, when using the universal serial bus of the USB2.0 standard or higher standard, it is possible to communicate by controlling and changing the number of packets of the storage means for storing the information received in units of packets according to the communication mode.

According to the communication method of the present invention, information corresponding to a plurality of communication modes having different amounts of information contained in one packet is received in packet units and temporarily stored in a storage means (for example, the memory 25 in the present embodiment). A communication method to be transmitted later, comprising: a mode specifying step for specifying a communication mode, and a control step for controlling the number of packets to be stored in the storage means in accordance with the specified communication mode. In the case of a communication mode capable of storing packets, a storage location of a plurality of packets is set in the storage means, and in the control step, in the communication mode in which a plurality of packets can be stored in the storage means, the plurality of packets are stored. It is stored temporarily in the packet storage of the means. In this way, it is possible to suppress the occurrence of the rejection state by controlling and changing the number of packets of the storage means for storing the information received in units of packets in accordance with the communication mode.

In the communication mode in which a plurality of packets can be stored in the storage means, the storage state of the packet may be changed by changing the storage location of the packet in the storage means. As a result, the information received in units of packets can be efficiently stored in the storage means in accordance with the communication mode.

Embodiment of the invention

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described in detail with reference to drawings. In addition, the following description shows the Example of this invention, and this invention is limited to the following description and should not be interpreted.

An example of the communication controller in the present embodiment will be described. 1 is a block diagram illustrating a device controller formed in a terminal device. Here, the device controller, which is a communication controller, is formed in a terminal device such as a printer. The terminal device is connected to a host computer (hereinafter, referred to as a host), and a central processing unit (CPU) of the host through the device controller. And the central processing unit (CPU) of the terminal equipment communicate. In addition, the terminal device and the host are connected and communicated by a USB cable, for example, even if the communication in the form of a packet such as a communication network by ISDN (Integrated Service Digital Network), the information is sent to the communication controller in the same packet unit. Store and communicate. 1, the CPU of the host and the terminal device is omitted. As shown in Fig. 1, the USB device controller 10 includes a USB interface unit (hereinafter, abbreviated to PHY; 11), a USB endpoint controller 12, and an external bus interface unit (BCU: Bus Control Unit; 13). Is installed. The USB interface unit 11 is configured by an analog transceiver, a serial interface engine, or the like, and performs serial parallel conversion of data transmitted from the host, or analyzes or generates a packet based on the USB protocol to interface with the USB bus. Communicate data by controlling it. The external bus interface unit 13 communicates data by controlling a bus connected to a processing device such as a CPU of a terminal device or a DMA (Direct Memory Access) controller. The USB endpoint controller 12 constitutes two types of endpoints, a receiving endpoint serving as a receiving unit of data on the terminal device side from a host and a transmitting endpoint serving as a transmitting unit, and buffering data transmitted and received to and from the host. Part. In addition, in this embodiment, the case where the USB endpoint controller 12 has one transmission end point and one reception end point respectively is demonstrated, You may have several transmission endpoints and a reception endpoint. In addition, the USB endpoint controller 12 may form a plurality of memories so that one or both of the reception endpoints may be configured as a double buffer configuration.

The USB endpoint controller 12 is provided with a transmission controller section 14, a reception controller section 19, a buffer control section 24, and a memory 25. The buffer control unit 24 instructs the transmission control unit 14 and the reception control unit 19 to allocate the memory 25 as a transmission buffer or a reception buffer. As described later, the buffer control unit 24 determines the buffer configuration of the memory 25 according to the communication mode between the host and the terminal device, and controls the storage state of the data stored in the buffer to transition. The number of packets to be stored in the memory 25 is controlled to determine the buffer configurations of the transmitting endpoint and the receiving endpoint, and the transition of the data storage state stored in the buffer is controlled. For example, a main memory allocated to a buffer such as cache memory can be used as the memory 25. As described later, when data is communicated with an auxiliary storage device such as an IDE (Hard Disk) of an IDE (Integrated Device Electronics) system, the main memory is allocated to a buffer such as a disk cache. Can be used as the memory 25. The memory 25 may be a shared buffer shared between the transmitting endpoint and the receiving endpoint, and assigned with a buffer in accordance with the transmitting endpoint or the receiving endpoint. As described above, when the memory is a double buffered memory, a common buffer, a transmit buffer, a receive buffer, or the like can be used in combination.

The transmission control unit 14 is provided with a transmission PHY side control unit 15, a transmission toggle plug unit 16, a transmission BCU side control unit 17, and a transmission buffer interface unit 18. The PHY side control part 15 for transmission controls data transmission to a host, reads out data from the buffer used as a transmission buffer, and outputs it. The transmission PHY side control unit 15 has a read counter corresponding to the memory 25, and outputs a read address of the memory 25. The transmission BCU side control unit 17 writes data from the external bus interface unit 13 to the memory 25 allocated to the buffer used as the transmission buffer. The transmission BCU side control unit 17 has a write counter corresponding to the memory 25, and outputs a write address of the memory 25. The transmission toggle plug section 16 manages the allocation of the memory 25 to the BCU side buffer or the PHY side buffer, and when the data transmission of the PHY side buffer is completed and the memory 25 becomes empty, the BCU side If there is data written to the buffer, the toggle toggle plug for transmission is toggled. The transmission buffer interface unit 18 assigns a write address corresponding to the memory 25 to the memory 25 serving as the BCU-side buffer based on the state of the transmission toggle plug, and transmits the BCU side control unit. Record the data from (17). In addition, the transmission buffer interface unit 18 reads the data by giving a read address corresponding to the memory 25 to the memory 25 serving as the PHY side buffer and reads the data to the transmission PHY side control unit 15. Output

The reception control unit 19 is provided with a reception PHY side control unit 20, a reception toggle plug unit 21, a reception BCU side control unit 22, and a reception buffer interface unit 25. The reception PHY side control unit 20 writes data from the host to a buffer used as a reception buffer. The reception PHY side control unit 20 has a write counter corresponding to the memory 25, and outputs a write address of the memory 25. The receiving BCU side control unit 22 reads and outputs data from the memory 25 allocated to the shared buffer used as the receiving buffer. The receiving BCU side control unit 22 has a read counter corresponding to the memory 25, and outputs a read address of the memory 25. The receiving toggle plug section 21 manages the allocation of the memory 25 to the BCU side buffer or the PHY side buffer, and when the data transmission of the BCU side buffer is completed and the memory 25 becomes empty, the PHY side If there is data recorded in the buffer, the receiving toggle plug is toggled to switch between the BCU side buffer and the PHY side buffer. The receiving buffer interface unit 23 assigns a write address from the write counter corresponding to the memory 25 to the memory 25 serving as the PHY side buffer based on the state of the receiving toggle plug. Data from the credit PHY side control unit 20 is recorded. In addition, the receiving buffer interface unit 23 reads the data by giving a read address from the read counter corresponding to the memory 25 to the memory 25 serving as the BCU side buffer, and reads the data. It outputs to the control part 22.

The USB endpoint controller 12 in the present embodiment allocates the memory 25 to the buffer of the transmitting endpoint by the buffer control unit 24 and simultaneously buffers the memory 25 according to the communication mode between the host and the terminal device. The configuration is determined, and the storage state of the data stored in the buffer is controlled to transition. The USB endpoint controller 12 switches the BCU side buffer and the PHY side buffer from the memory 25 constituting the buffer to the transmission buffer interface unit 18 according to an instruction from the transmission toggle plug section 16. Then, the data is written to the memory serving as the BCU side buffer while the storage state in the data buffer inputted from the external bus interface unit 13 to the transmission BCU side control unit 17 is changed. In addition, the USB endpoint controller 12 reads data from the memory 25, which becomes the PHY side buffer, by the transmitting PHY side control unit 15, and shifts the storage state in the data buffer. Output to.

In addition, the USB endpoint controller 12 according to the present embodiment allocates the memory 25 to the buffer of the receiving endpoint by the buffer control unit 24 and at the same time the memory (in accordance with the communication mode between the host and the terminal device). 25) determine the buffer configuration, and control to transition the storage state of the data stored in the buffer. The USB endpoint controller 12 switches the BCU side buffer and the PHY side buffer from the memory 25 constituting the buffer to the receiving buffer interface unit 23 according to the instructions from the receiving toggle plug section 21. The data is recorded in the memory 25 serving as the BCU side buffer while the storage state in the data buffer inputted from the USB interface unit 11 to the reception PHY side control unit 20 is changed. In addition, the USB endpoint controller 12 reads data from the memory 25 serving as the BCU side buffer by the receiving BCU side control unit 22 and shifts the storage state of the data buffer to the external bus interface unit ( 13)

An example of one embodiment of the USB transfer operation will be described. The USB transfer process consists of a plurality of transfer units (transaction data), and when transferring data from the host to a terminal device (printer), for example, in the case of printer printing, the USB transfer process consists of a plurality of OUT transaction data. In the case where data is transferred from the terminal apparatus (scanner) 2 to the host such as to read image data by the scanner, the USB transfer process is composed of a plurality of IN transaction data.

Fig. 2 is a schematic diagram showing an example of the configuration of transaction data. As shown in Fig. 2, the transaction data 38 is composed of three types of packets: token packet 38a, data packet 38b, and handshake packet 38c. It is composed. Initially, a token packet 38a having device address and endpoint information is transmitted from the host to the terminal apparatus. The token packet 38a is decoded by the USB interface unit 11, and when it is recognized that the token detected by the decode is a token received by the terminal device, an endpoint to be allocated for data transmission is determined. Once the endpoint assigned to the data transfer is determined, the endpoint number and token type assigned to the data transfer are passed to the USB endpoint controller 12. In the USB endpoint controller 12, preparation for sending or receiving the data packet 38b is performed in accordance with the endpoint number and token type assigned to the data transfer. For example, if transaction data 38 is OUT transaction data (receive), the first OUT token packet 38a determines at which receiving endpoint the data should be received, and the data sent from the host. Receive packet 38b at its determined receiving endpoint. In the case of the USB device controller 10 shown in Fig. 1, the serial parallel converted data in the USB interface unit 11 is stored in the memory 25 allocated to the receiving buffer. Upon receipt of the data packet 38b sent from the host at the determined receiving endpoint, the handshake packet 38c notifies the host whether the data has been successfully received and stored in memory. The USB endpoint controller 12 passes the handshake information to the USB interface unit 11, and the USB interface unit 11 generates a handshake packet 38c according to the handshake information and outputs it to the USB bus. .

Since the data transmitted from the host to the terminal device is composed of a plurality of consecutive transaction data 38, for example, in the case of data reception, it is composed of a plurality of OUT transaction data, so that the buffer is stored when the receiving endpoint is used. By shifting the state and shifting the storage state of the data in the buffer to an optimal state, an empty space for storing data is created in the buffer as data is read from the memory 25 (BCU side buffer) to the terminal device 2. Can receive the next data from memory (25; PHY side buffer).

When transmitting data from a terminal device (scanner) to a host such as reading image data by a scanner, the first IN token packet determines from which transmission endpoint the data should be transmitted. Send data from the determined transmitting endpoint at 38b. In the case of the USB device controller 10 shown in Fig. 1, the data stored in the transmission buffer is parallel serially converted by the USB interface unit 11 and transmitted to the host as a data packet 38b. The USB endpoint controller 12 recognizes by the shaker packet 38c returned from the host whether the transmission of the data was successful. In general, since the data transmission process is composed of a plurality of IN transaction data 38, if the storage state of the buffer can be changed when using the transmission endpoint, the data storage state of the buffer is optimal. By transitioning to the state, as data is transmitted from the memory 25 (PHY side buffer), a space for storing data can be created in the buffer, and the next data from the terminal apparatus can be recorded in the memory 25 (BCU side buffer). have.

When configuring the USB device controller 10 as described above, the buffer control unit 24 allocates the memory 25 to the buffer of the transmitting endpoint or the receiving endpoint, and the memory in accordance with the connection mode of the host and the terminal device. The buffer configuration of the memory 25 can be determined by controlling the number of packets to be stored in the 25. Therefore, by changing the number of packets stored in the memory 25, the buffer control unit 24 can store the data received in packet units in the memory 25 in accordance with the communication mode. For example, in the case of using the 512-byte memory 25 to communicate in the HS mode or the FS mode with less communication capacity than the HS mode, the buffer control unit 24 has a capacity of 1 packet in the HS mode of 512 bytes. The number of packets to be stored in the memory 25 is controlled to have a one packet buffer configuration. In the FS mode, since the capacity of one packet is 64 bytes, which is the maximum packet size of the bulk transfer, this is configured to include eight packets. The number of packets stored in the memory 25 can be controlled. In addition, as will be described later, the buffer control unit 24 controls the number of packets to be stored in the memory 25 and executes the transition of the data storage state by using the buffer which becomes empty by transmission and reception. The occurrence of the NAK response can be avoided between the terminal apparatuses, and transmission waiting or reception waiting can be prevented. In addition, in this embodiment, although the USB device controller 10 was comprised as shown in FIG. 1, in short, the buffer structure of the memory 25 is determined by the connection mode, and the buffer control part 24 of the buffer which stores data is carried out. You can configure the storage state to transition.

The following describes the memory for transitioning the storage state according to the communication format and communication format of the USB transfer. 3 is a chart showing an example of a storage state of a buffer for storing data executed between the terminal apparatus and the host. Here, in Fig. 3, USB transmission is performed by using a USB function device of USB 2.0 standard, and a terminal device such as a printer and a computer main body which is a host are connected by a communication mode HS mode or FS mode connection mode. Communicate data. In addition, the case where data is transmitted by the connection mode of HS mode and FS mode is demonstrated using FIG. 3, For example, it may be a lower mode like LS mode, or a mode higher than HS mode. In that case, a USB function device is selected by the connection mode which connects a terminal apparatus and a host. In the present embodiment, the data communicated between the host and the terminal device is temporarily stored in the memory 25 allocated to the 512-byte buffer, but may be a buffer having a size higher than 512 bytes such as 1024 bytes, for example. .

As shown in Fig. 3, a plurality of transaction data is transmitted from the host to the terminal apparatus in units of packets (S41). At this time, the terminal device and the host are connected via a USB interface, and when the USB is, for example, USB2.0 standard, the terminal device and the host are connected in a connection mode such as FS mode or HS mode to communicate data. When the connection mode is the HS mode, in order to store data having a size of 512 bytes, the memory 25 having 512 bytes has one buffer structure, and 512 bytes of data are stored in one packet buffer (S42a). When the connection mode is FS mode instead of HS mode, since the maximum packet size for bulk transfer in FS mode is defined as 64 bytes, the 512-byte memory 25 has eight buffer configurations with one capacity of 64 bytes. 64 bytes of data are stored in each of the eight packet buffers (S42b). As described above, the packet configuration of the memory 25 having 512 bytes differs in the HS mode and the FS mode because the maximum packet size varies depending on the connection mode. Therefore, the buffer configuration of the memory 25 is determined according to the connection mode, and data is stored in each buffer. In addition, one packet buffer means one divided buffer in which data received in units of packets is stored, and one packet of data is stored in one packet buffer.

When connecting the terminal apparatus and the host in the HS mode or the FS mode having a different maximum packet size, the configuration of the buffer allocated to the memory can be various configurations. A configuration example of a buffer structure based on a plurality of transaction data in units of packets will be described with reference to FIG. In FIG. 4, a configuration example of a 512-byte buffer will be described. However, a buffer having a size higher than 512 bytes may be used, for example, 1024 bytes. Fig. 4A shows the configuration of the buffer 41 in the case where the 512-byte memory 25 is formed in a single buffer configuration and connected in HS mode. In this case, the configuration of one packet buffer is the same as described above. Doing. As shown in Fig. 4 (b), since the maximum packet size is defined as 64 bytes in the FS mode, the buffer 42 has one capacity of 64 bytes, whereas the buffer consists of one packet buffer in the HS mode. 8 packet buffers (packet buffer 42a1 to packet buffer 42a8). Similarly, the buffer structure in the case of connecting by HS mode and FS mode can be described using Figs. 4 (c) and 4 (e). In this case, the case of a double buffer configuration in which one memory is 512 bytes, and when connected in HS mode as shown in Fig. 4 (c), the buffer 43 has two packet buffers (packets of one capacity of 512 bytes). The buffer 43a1 and the packet buffer 43a2 are configured. As shown in Fig. 4D, since the maximum packet size is defined as 64 bytes in the FS mode, each of the packet buffers in the HS mode is divided into eight packet buffers having a capacity of 64 bytes, and the buffer 44 ) Constitutes a total of 16 packet buffers (packet buffers 44a1 to 44a16). In addition, as shown in Fig. 4E, in the case of the double buffer configuration in which one memory is 512 bytes, the buffer 51 has the configuration of two packet buffers in which the packet buffer is 64 bytes.

An example of the transition of the storage state of data executed in the memory allocated to the buffer will be described with reference to FIG. 5 is a schematic diagram showing the transition of the storage state of the buffer. 5 illustrates a case where data is transmitted from a host to a terminal device such as a printer. In the case of transmitting data to the host from a terminal device such as a scanner, the storage state is not the same in a buffer such as a printer buffer. Transition. In FIG. 5, when the memory 25 of 512 bytes as shown in FIG. 4 (b) is installed in a single buffer configuration and connected in the FS mode, one as shown in FIG. 4 (d) is 512 bytes. Similarly, when the memory is formed in a double buffer configuration and connected in the FS mode, the data storage state can be changed.

In the buffer configuration shown in Fig. 4B, when connected in the FS mode, an 8 packet buffer configuration in which the size of one buffer is 64 bytes in a 512-byte memory is obtained. The buffer, which is an 8 packet buffer, is empty when no data is received from the host. However, when receiving 1 packet of data having a size of 64 bytes from the host, the received 1 packet of data is stored in the packet buffer 42a1. (Fig. 5 (a)). At this time, the packet stored in the packet buffer 42a1 is an OUT token packet etc. which have a device address or endpoint information, for example. When three packets of a data packet or the like whose size of one packet are 64 bytes are received from the host, as shown in Fig. 5B, the three packet data are stored in the packet buffers 42a2 to 42a4 in order. When each packet is received from the host and stored in the buffer, it is stored in the packet buffer 42a5 as shown in Fig. 5 (c), and data of 5 packets in total are received in packet units, and the packet buffer 42a1 is received. To the packet buffer 42a5 is embedded. Fig. 5D shows a state in which the CPU of the terminal apparatus is reading data stored in the packet buffer 42a1 which is the first packet. When the data reading of the packet buffer 42a1 is completed, the packet buffer 42a1 becomes empty as shown in Fig. 5E. As shown in Fig. 5E, when the CPU reads data stored in the packet buffer 42a1, one packet of data such as a handshake packet received from the host is stored in the packet buffer 42a6. At this time, while the CPU reads the data stored in the packet buffer 42a1, the buffer is temporarily in a state of using a packet buffer for 64 packets of 6 bytes.

The packet buffer 42a1 of the buffer 42 becomes empty, and the state of storing the data in the buffer 42 is shifted from the state in which the packet buffer for 6 packets is temporarily used. As shown in Fig. 5 (f), the data stored in the five packet buffers of the packet buffer 42a2 to the packet buffer 42a6 are moved to the packet buffer 42a1 to the packet buffer 42a5, and Fig. 5c described above. The storage state of the data in the buffer 42 is shifted in the state of storing the data in the five packet buffers of the packet buffer 42a1 to the packet buffer 42a5. By moving the data stored in the five packet buffers of the buffer 42, the packet buffers 42a6 to 42a8 become empty, and the packet buffers 42a6 to 42a8 that become empty are used. It does not exist. As shown in Fig. 5 (g), data for one packet received from the host is stored in the packet buffer 42a6 which is not used because the buffer 42 is empty. After that, the data stored in the packet buffer 42a1 is read into the CPU of the terminal device again. When the packet buffer 42a1 becomes empty, the data stored in the packet buffer 42a2 or less moves to read the data. Each time the packet buffer where data is stored is changed. The transition of the data storage state is executed by the buffer control unit 24, but can be executed based on the address of the data stored in the buffer and the like. For example, when moving the data of each packet as shown in FIG. 5, the buffer control part 24 performs the packet buffer 42a2 so that the address of the data stored in the packet buffer 42a2 may become the packet buffer 42a1. The address of the data is calculated, the calculated address is assigned to the data stored in the packet buffer 42a2, and the data of the packet buffer 42a2 is shifted to the packet buffer 42a1. In addition, the buffer control section 24 assigns a new address of the data stored in four packets of the packet buffer 42a3 to the packet buffer 42a6 in the same way as the data stored in the packet buffer 42a2, and the packet buffer 42a2. To the packet buffer 42a5 to shift the storage state of the data.

In this way, by controlling the number of packets to be stored in the memory 25 in accordance with a communication mode such as the HS mode or the FS mode, the buffer configuration of the memory 25 is determined and the storage state of the buffer is shifted, thereby making each communication mode possible. In accordance with this, data to be received can be efficiently stored in the memory 25. Therefore, according to the communication mode, a plurality of packets can be efficiently stored in the memory 25, and the occurrence of NAK response between the host and the terminal device can be avoided, and transmission and reception waiting can be prevented to reduce the communication speed. Can be. For example, when moving the packet data remaining in the empty buffer as shown in Fig. 5, the data can be newly stored in the storage location where the remaining packet data has been stored, and the data of the received packet unit can be assured. Can be stored. Therefore, when packet data is transmitted to the buffer, the packet data can be efficiently and reliably stored in the buffer, and the host transmitting the data can transmit the data without generating a transmission wait. In this way, the number of packets of packets stored in the memory 25 is controlled in accordance with the communication mode to efficiently store the data in the memory 25 to prevent a decrease in the communication speed of the data, and also to shift the storage state of the buffer. By doing so, the data communication speed can be improved.

In addition, as shown in Fig. 5, in the case where the storage state of the buffer is changed and the packet data remaining in the empty buffer is moved, the data transmitted to the packet buffer 42a1 is moved and the terminal device is moved from the packet buffer 42a1. Packets can be sent to the CPU. Therefore, data can be transmitted efficiently by using the storage location of the buffer 42 which becomes empty by packet transmission, and data can be transmitted without reducing the communication speed of data. In addition, since the decrease in the communication speed of data can be prevented, the CPU of the terminal apparatus can acquire and read data without generating a read wait.

Further, when the storage state of the buffer is shifted, the order of the data transmitted from the memory 25 can be controlled by shifting the storage state based on the order of transmitting data in units of packets. For example, as shown in Fig. 5, the first received data is stored in the packet 42a1 and then transmitted from the memory 25 first, but the data stored in the packet buffer 42a2 is moved to the packet buffer 42a1. By transmitting the data from the memory 25, the data can be transmitted in the order of the data stored in the memory 25. In this way, by controlling the order of the data to be transmitted from the memory 25, it is possible to efficiently transmit the received packets in order from the received packets while reliably storing the received packets in the memory 25.

Another example of the transition of the storage state executed in the buffer will be described with reference to FIG. 6 is a schematic diagram showing the transition of the storage state of the buffer. 6 illustrates a case where data is transmitted from a host CPU to an auxiliary storage device such as a hard disk of an IDE (Integrated Device Electronics) system, and the data is transmitted from the auxiliary memory device to the CPU of the host. Similarly, the storage state is shifted in a buffer such as a disk cache. Fig. 6 is a case where two 512-byte memories as shown in Fig. 4 (d) are formed in a double buffer configuration and connected in HS mode, but a single 512-byte memory as shown in Fig. 4 (b) is used. The storage state of data can be changed similarly to the case of forming in a buffer configuration and connecting in the FS mode. In addition, the case where the unit of data transmitted to the auxiliary storage device is one sector of 512 bytes is described, but the size of one sector may be other than 512.

In the buffer configuration shown in Fig. 4 (d), when connected in the FS mode, the buffer 44 is two 512 bytes of memory and 16 packet buffers each having a size of 64 bytes (packet buffer 44a1). To packet buffer 44a16). The packet buffer of 16 is empty when no data is received from the CPU of the host. However, when three packets of a packet having a size of 64 bytes are received from the CPU of the host, the received three packets of data are stored in the packet buffer 44a1. To the packet buffer 44a3, and three packets of data are recorded in the auxiliary memory device (Fig. 6 (a)). At this time, the packet stored in the packet buffer 44a1 to the packet buffer 44a3 is a token packet, a data packet, etc., for example. When five packets of data packets, such as a data packet having a data size of 64 bytes, are received from the CPU of the host for five packets, as shown in Fig. 6B, the data for three packets are sequentially processed from the packet buffer 44a4 to the packet. It is stored in the buffer 44a8, and data for three packets is recorded in the auxiliary memory device. Thus, after receiving each packet from the CPU of the host, the packet is stored in a buffer, and as shown in Fig. 6B, a total of 8 packets of data are received in packet units, and the packet buffers 44a1 to packets of the buffer 44 are received. The buffer 44a8 is brought into a buried state. At this time, the auxiliary memory device is recorded without waiting to write data for one sector by the host CPU. After that, for example, when a transmission request is made from a host CPU, or when the transmission mode is set to the automatic transmission mode, as shown in FIG. Is sent to the CPU, and the packet buffer 44a1 and the packet buffer 44a2 become empty. In addition, in Fig. 6C, the auxiliary memory device reads data into the CPU of the host and simultaneously receives and stores three packets of data in the empty packet buffers 44a9 to 44a11. As shown in Fig. 6D, data for five packets of the packet buffer 44a3 to the packet buffer 44a8 is transmitted to the CPU of the host. At this time, the data is transmitted to the CPU of the host, and at the same time, data for 5 packets such as data packets received from the CPU of the host are stored in the packet buffers 44a12 to 44a16. Five packets of data are recorded. At this time, while the data of the packet buffer 44a1 to the packet buffer 44a8 is transmitted to the CPU of the host, the buffer 44 for 64 packets of 64 bytes is temporarily used.

The packet buffers 44a1 to 44a8 of the buffer 44 become empty, and the storage state of the data in the buffer 44 is shifted from the state in which the buffer for 16 packets is temporarily used. As shown in Fig. 6E, the data stored in the 8 packet buffers of the packet buffers 44a9 to 44a16 are moved to the packet buffers 44a1 to 44a8, and Fig. 6B described above. In the same manner as in Fig. 2), the data storage state of the data in the buffer 44 is shifted while data is stored in the 8 packet buffers of the packet buffers 44a1 to 44a8. As a result, data for 8 packets, which is one sector for the auxiliary storage device, can be recorded without causing a recording wait. By moving data stored in five packets of the buffer, the packet buffers 44a9 to 44a16 become empty, and the packet buffers 44a5 to 44a8 which become empty are not used. do. After that, data stored in the packet buffer 44a1 to the packet buffer 44a8 is transmitted to the CPU of the host, and the packet data received from the CPU of the host is stored in the packet buffer 44a9 to the packet buffer 44a16. When the packet buffers 44a1 to 44a8 become empty, data for 8 packets, which is one sector of the auxiliary storage device, is moved. The transition of the data storage state is executed by the buffer control unit, but can be executed based on the address of the data stored in the buffer or the like. For example, as shown in Fig. 6, when moving the data of each packet buffer, the buffer control unit controls the data of the packet buffer 44a9 so that the address of the data stored in the packet buffer 44a9 becomes the packet buffer 44a1. Is calculated, the calculated address is assigned to the data stored in the packet buffer 44a9, and the data of the packet buffer 44a9 is shifted to the packet buffer 44a1. In addition, the buffer control unit allocates a new address of data stored in the seven packet buffers of the packet buffer 44a10 to the packet buffer 44a16 in the same manner as the data of the packet buffer 44a9, and thus the packet buffer 44a1 to the packet buffer ( 44a8) to shift the data storage state.

As described above, by controlling the number of packets to be stored in the memory 25 in accordance with a communication mode such as the HS mode or the FS mode, the buffer configuration of the memory 25 is determined, and the storage state of the buffer is shifted, thereby communicating each communication. Depending on the mode, data to be received can be efficiently stored in the memory 25. Therefore, according to the communication mode, a plurality of packets can be efficiently stored in the memory 25, thereby avoiding the occurrence of NAK response between the CPU of the host and the auxiliary storage device, and preventing transmission waiting or reception waiting, thereby reducing the communication speed. It can prevent. For example, as shown in Fig. 6, when data corresponding to one sector of the auxiliary storage device is moved to an empty buffer, the buffer can be newly stored in a storage place where data for one sector is stored. It is possible to reliably store data in a buffer unit to receive the data and to record the data in the auxiliary memory device. Therefore, when packet data is transmitted to the buffer, the packet data can be efficiently and reliably stored in the buffer, and the host which transmits the data can transmit the data without transmitting waiting. By controlling the number of packets of the packets stored in the memory 25 in accordance with the communication mode as described above, the data can be efficiently stored in the memory 25 to prevent the communication speed of the data from being lowered, and the state of the buffer is shifted. The data communication speed can be improved.

As shown in Fig. 6, when the storage state of the buffer is shifted and packet data remaining in the empty buffer is shifted by one sector of the auxiliary storage device, the host is transferred from the packet buffer 44a1 to the packet buffer 44a8. One sector of data can be transmitted to the CPU. Therefore, data can be transmitted efficiently using the storage location of the buffer 44 which becomes empty by packet transmission, and data can be transmitted without reducing the communication speed of data. In addition, since the decrease in the communication speed of data can be prevented, the CPU of the host can acquire data without reading waiting and read data for one sector of the auxiliary storage device together.

In addition, when the storage state of the buffer is shifted, the order of data transmitted from the memory 25 can be controlled by shifting the storage state based on the order of transmitting data in units of buffers. For example, as shown in Fig. 6, in the packet buffer 44a1 to the packet buffer 44a8 corresponding to one sector, the first received data is stored and then transmitted from the memory 25 first, but one sector of the auxiliary memory device. By moving the packet buffer 44a9 to the packet buffer 44a16 corresponding to the packet buffer 44a1 to the packet buffer 44a8 and transmitting data from the memory 25, the data is stored in the memory 25 in the order of the data. One sector of data can be transmitted. In this way, by controlling the order of the data transmitted from the memory 25, the received packet is reliably stored in the memory 25 while efficiently storing the data for one sector from the received packet to the auxiliary storage device in order. Can record

The buffer control unit for transitioning the storage state of the memory in accordance with the communication format of the USB transfer will be described. 7 is a chart showing an example of an operation of a control unit for transitioning a storage state of a memory. First, the buffer control unit 24 specifies the communication mode between the host and the terminal apparatus according to the flow already described with reference to Fig. 3, and determines the buffer configuration of the memory 25 (S50). Here, description has been made using a case in which a 512-byte memory 25 as shown in Fig. 4B is formed in a single buffer configuration and connected in the FS mode, but one as shown in Fig. 4D is 512 bytes. Similarly, in the case where the memory is formed in the double buffer configuration and connected in the FS mode, the buffer control unit can execute the control. First, when communicating in the FS mode, the buffer control unit 24 divides the 512-byte memory having one packet buffer structure into eight pieces so that the capacity of each packet buffer becomes 64 bytes when connected in the HS mode. Thereafter, as shown in S51, the buffer control unit 24 recognizes the stored packet. At this time, the buffer control unit 24 recognizes the storage location where the packet is stored, for example, from the token packet or the like based on the address of the memory in which the packet is stored. Recognizing the packet buffer in which the packet is stored, the buffer control unit 24 checks whether there is a packet to be received from the host, for example, and if there is a packet to receive, stores the received packet (S53b). The buffer controller recognizes a packet to be stored again while storing the received packet. When not receiving a packet as shown in S52, the buffer control section recognizes, for example, whether or not a packet is read and transmitted to the CPU of the terminal apparatus (S53a). Since the packet buffer is generated, an empty packet buffer is recognized (S54a), and the storage state of the entire buffer is shifted (S55). The transition of the stored state of the buffer is, for example, movement of the entire packet as shown in FIG. If there is no packet to transmit as shown in S53a, the buffer controller checks whether there is an empty buffer without transmitting the packet (S54), and if there is no packet buffer in the empty state, the received packet The process returns to step S52 for checking whether there is any error, and executes the above-described steps again. If there is an empty packet buffer when there is no packet to be transmitted, as shown in S54a as described above, the empty packet buffer is recognized and the storage state of the entire buffer is shifted (S55). After shifting the storage state of the buffer, the buffer control unit returns to the step shown in S51, recognizes again the storage state of the buffer, and controls the transition of the storage state.

As described above, when the buffer control unit executes the operation, the configuration of the buffer can be changed in correspondence with the connection mode such as the FS mode or the HS mode, and the transition of the storage state of the buffer can be realized. By controlling the transition of the storage state of the buffer, the buffer controller can store the packet newly in a storage place where the remaining packet data is stored, and can efficiently store the packet in the buffer. In addition, a data transmission side apparatus such as a host that transmits data can transmit data without transmitting waiting, and can prevent the communication speed of data from being lowered.

In addition, the buffer control unit configures the buffer according to the connection mode to efficiently store the data in the buffer unit in the memory 25, and simultaneously changes the storage state of the buffer to store the data in the memory 25 more efficiently. have. Therefore, the number of packets to be stored in the memory 25 is controlled in accordance with the communication mode to efficiently store the data in the memory 25 to prevent the degradation of the communication speed of the data. By changing the storage state of the buffer, it is possible to improve the data communication speed.

As described above, for example, when a USB connection of a host and a terminal device is performed using a USB 2.0 standard USB cable, communication is performed in the FS mode. By shifting the storage state of the buffer allocated to the memory by the buffer control unit, a plurality of packet buffers can be allocated to the memory, and data can be newly stored in the packet buffer which is in a state after being transmitted. Therefore, even in the case of the communication by the FS mode, it is possible to efficiently store the packet in the buffer to communicate, and there is no waiting for transmission to the host transmitting data, and no NAK response to the host occurs. Data can be sent. In this way, since the host can transmit data without generating a transmission standby or NAK response, even when communicating in the FS mode, data can be communicated without reducing the communication speed of the data.

In addition, when data is transmitted from the terminal device to the host using a USB 2.0 standard USB cable, for example, when communicating in the FS mode, the storage state of the buffer allocated to the memory is changed by the buffer controller, By storing the data again in the buffer to be in the state, it is possible to efficiently transmit data from the buffer in which the data is stored again. Therefore, even in the case of communicating in the FS mode, no reception wait occurs in the host that receives the data, and no NAK response occurs to the terminal device, and the host can receive the data. As described above, since the host can receive data without receiving reception or NAK response, even when communicating in the FS mode, data can be communicated without reducing the communication speed of the data.

Further, in the case of data communication in which the CPU of the host writes data to the auxiliary memory device, one sector can be recorded simultaneously by controlling the transition of the storage state of the buffer. Therefore, the CPU of the host can efficiently write data to the auxiliary storage device, and can increase the recording speed of the data to the auxiliary storage device. In the case of data communication in which the CPU of the host reads data from the auxiliary storage device, the control of the transition of the storage state of the buffer can be controlled so that one sector can be read simultaneously and the data can be efficiently read into the auxiliary storage device. Therefore, the communication speed of data communication between the CPU of the host and the auxiliary storage device can be improved.

The present invention can provide a communication controller and a communication method capable of suppressing occurrence of a condition of rejection between communicating hosts when communicating information in packet units.

Claims (12)

A communication controller for receiving, corresponding to a packet unit, information corresponding to a plurality of communication modes having different amounts of information contained in one packet, temporarily storing the information, and transmitting the information. Storage means for temporarily storing the received information; Control means for controlling the number of packets to be stored in the storage means according to the communication mode; In the communication mode in which the plurality of packets can be stored in the storage means, the control means sets a storage location of the plurality of packets in the storage means and temporarily stores the plurality of packets in the storage means. The communication controller according to claim 1, wherein said control means transitions the storage state of the packet by changing the storage location of the packet in said storage means in a communication mode in which a plurality of packets can be stored in said storage means. The communication controller according to claim 2, wherein said control means makes a transition to a storage state of a packet by moving another stored packet to a storage place that is empty due to transmission of the packet. The communication controller according to claim 2, wherein the control means transmits the packets in the order stored in the storage means, and shifts the storage state of the packets by moving the next transmitted packet to a storage place which is empty by being transmitted. 2. The communication apparatus according to claim 1, wherein the plurality of communication modes include a first communication mode and a second communication mode in which the amount of information included in one packet is smaller than the first communication mode, The storage means has a storage capacity corresponding to a packet of information amount corresponding to the first communication mode, The control means temporarily stores one packet in the storage means when the packet in the first communication mode is received, and stores a plurality of packets in the storage means when receiving the packet in the second communication mode. A communication controller that temporarily stores packets. The communication controller according to claim 1, wherein the information is communicated via a universal serial bus, and the universal serial bus is a USB 2.0 standard. A communication method for receiving information corresponding to a plurality of communication modes having different amounts of information contained in one packet in packet units, temporarily storing the information in a storage means, and then transmitting the information. A mode specifying step of specifying the communication mode; A control step of controlling the number of packets to be stored in the storage means according to the specified communication mode, In the mode specifying step, when it is specified that the communication mode is capable of storing a plurality of packets in the storage means, a storage location of the plurality of packets is set in the storage means, In the control step, in the communication mode in which a plurality of packets can be stored in the storage means, the plurality of packets are temporarily stored in a packet storage location of the storage means. 8. The communication method according to claim 7, wherein in the case of a communication mode in which a plurality of packets can be stored in the storage means, the storage state of the packets is changed by changing the storage location of the packets in the storage means. The communication method according to claim 8, wherein the storage state of the packet is shifted by moving another stored packet to a storage place which is empty by transmitting the packet. 9. The communication method according to claim 8, wherein said packet is transmitted in the order stored in said storage means, and said packet is shifted to a storage place which is empty by being transmitted, thereby transferring a packet to be transmitted next. 8. The communication apparatus according to claim 7, wherein the plurality of communication modes include a first communication mode and a second communication mode in which a smaller amount of information is included in one packet than the first communication mode, In the mode specifying step, when it is specified that the communication mode is the second communication mode, a storage location for a plurality of packets is set in the storage means, In the control step, when a packet of the first communication mode is received, one packet is temporarily stored in the storage means, and when a packet of the second communication mode is received, a plurality of packets are stored in the storage means. A communication method that is temporarily stored. 8. The communication method according to claim 7, wherein the information is communicated via a universal serial bus, and the universal serial bus is a USB 2.0 standard.

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