CN1252602C

CN1252602C - Communication controller and communication method

Info

Publication number: CN1252602C
Application number: CNB031364241A
Authority: CN
Inventors: 大津智彦; 高梨刚
Original assignee: NEC Corp
Current assignee: Renesas Electronics Corp
Priority date: 2002-05-17
Filing date: 2003-05-15
Publication date: 2006-04-19
Anticipated expiration: 2023-05-15
Also published as: KR100563418B1; TW200308157A; JP2003333108A; KR20030089480A; CN1460951A; TWI227979B

Abstract

The present invention provides a communication controller and its communication method to prevent the occurrence of a receiving rejection status from the host under communicating during information communication in a packet unit. The communication controller of this invention receives, in the packet unit, information corresponding to a plurality of communication modes different from one another in the information volume included in one packet. This communication controller that temporarily stores the information and then transmits it includes a memory means for temporarily storing the received information and a control means for controlling the number of the packets stored in the memory means corresponding to the communication modes. While in a communication mode wherein the memory means can store a plurality of packets, the control means sets the storing locations of a plurality of packet in the memory means to enable the memory means to temporarily store a plurality of packets.

Description

Communication controler and communication means

Technical field

The present invention relates to a kind of communication controler and communication means, particularly a kind of communication controler and communication means that carries out information communication with packets of information (packet) form.

Background technology

Up to now, when connecting computing machine and peripherals, the interface that uses serial line interface (SerialInterface) or parallel interface peripherals such as (Parallel Interface) to use connects.In addition,, serial line interfaces such as USB (Universal Serial Bus) and IEEE1394 occurred, made nuclear interface standardizing, universalization become a kind of trend as the interface that a plurality of various peripherals are connected as one.

In informationized society in recent years, owing to need carry out Large Volume Data communication at high speed, so developed the USB2.0 standard, this standard is compared with prior USB 1.0 standards USB1.x standards such as (USB-IF:USB Implements For um standards), and data transmission rate is higher.It is full speed (Full Speed) pattern (below be designated as the FS pattern) of 12Mbps and low speed (Low Speed) pattern of 1.5Mbps (below be designated as the LS pattern) that the connection mode of prior USB 1.x standard has peak data transfer rate, in USB2.0, kept above-mentioned pattern, also increase peak data transfer rate in addition newly and be high speed (HighSpeed) pattern (below be designated as the HS pattern) of 480Mbps, thereby can carry out more large-capacity data communication at high speed.

State in the use in the function element (function device) of USB2.0 standard, when for example under the HS pattern, connecting 512 byte memorys, 512 byte memorys can be constituted as a packet buffer and use.In addition, when under the FS pattern, connecting 512 byte memorys, 64 byte memorys can be constituted as a packet buffer and use, no matter be under the HS pattern, to connect, still under the FS pattern, connect, 512 byte memorys can be used as a packet buffer, but under the FS pattern, the maximum information bag size of employed high capacity transmission (bulk transfer) is 64 bytes, and 448 remaining bytes are not used.

When the FS pattern connects, the impact damper of the system that constitutes by function element, though 64 bytes are used 448 remaining bytes of back and are not used, but 512 bytes of memory devices are used as a packet buffer, utilize 512 byte integral body of a packet buffer to carry out writing or reading of data.Therefore, with the data write buffer or during the impact damper sense data, can not carry out other visit to impact damper, main frame is carried out IN request or OUT request, NAK (Negative Acknowledge) replys (negative response) and take place completely.When NAK taking place reply, the main frame that USB is connected carries out the request of transmission once more of packets of information, waits for producing to send from the transmission once more of main frame and waits for.In addition, can not carry out under the situation of other visits, during the IN request or OUT request that the main frame to the USB connection carries out, packets of information takes place damage or packets lost, and then generation NAK reply at the USB impact damper.

Therefore, existing be to have following problem in the information communication of unit with the packets of information, promptly since the packets of information number of canned data bag unit information not along with communication pattern changes, can not canned data so even dummy status can take place, in communication process, can not carry out other visit, and to the phenomenon of the main frame rejection of carrying out information communication.

The present invention proposes in order to address the above problem, and its objective is provides a kind of communication controler and communication means, when with the packets of information being unit when carrying out information communication, can be suppressed at the state that rejection takes place between the main frame that communicates.

Summary of the invention

Communication controler of the present invention is that unit receives the information corresponding with plurality of communication schemes with the packets of information, send after the temporary transient storage, the quantity of information that plurality of communication schemes comprises in a packets of information is different, it is characterized in that, comprise: storage unit (for example storer in the present embodiment 25), the information that temporary transient storage is received; And control module (for example impact damper control module in the present embodiment), come the packets of information number of control store in storage unit according to communication pattern, if a plurality of packets of information can be stored in communication pattern in the storage unit, then control module is set the memory address of a plurality of packets of information in storage unit, and a plurality of packets of information temporarily are stored in the storage unit.By above-mentioned formation, can control that to be used to store with the packets of information be the packets of information number of the storage unit of the information that unit received according to communication pattern, and it is changed, suppress to produce the state of rejection.

If a plurality of packets of information can be stored in communication pattern in the said memory cells, then preferred above-mentioned control module is by changing the memory address of the packets of information in this storage unit, the store status of coming the transition information bag.Thus, adjust suitably according to communication pattern that to be used to store with the packets of information be the memory address of the information that unit received, thus canned data efficiently.

The information of preferred above-mentioned T-R communicates by USB (universal serial bus), and this USB (universal serial bus) is the USB2.0 standard.Thus, when using the USB (universal serial bus) of USB2.0 standard, can control that to be used to store with the packets of information be the packets of information number of the storage unit of the information that unit received, and make its variation, thereby communicate according to communication pattern.

Communication means of the present invention, with the packets of information is that unit receives the information corresponding with plurality of communication schemes, send after temporarily being stored in the storage unit (for example storer in the present embodiment 25), the quantity of information that plurality of communication schemes comprises in a packets of information is different, it is characterized in that, may further comprise the steps: pattern given step, specified communication mode; And controlled step, according to specified communication pattern, the packets of information number of control store in storage unit, in the pattern given step, if specified the communication pattern that a plurality of packets of information can be stored in the storage unit, then in storage unit, set the memory address of a plurality of packets of information, in controlled step, if a plurality of packets of information can be stored in communication pattern in the storage unit, then a plurality of packets of information temporarily are stored in the packets of information memory address of storage unit.According to said method, can control that to be used to store with the packets of information be the packets of information number of the storage unit of the information that unit received according to communication pattern, and it is changed, suppress to produce the state of rejection.

If a plurality of packets of information can be stored in communication pattern in the storage unit, then can be by changing the packets of information memory address in this storage unit, the store status of coming the transition information bag.Thus, can be according to communication pattern, will be with the packets of information efficient information that receives of unit be stored in the storage unit.

Description of drawings

Fig. 1 is the schematic block diagram of the communication system of expression embodiment of the present invention.

Fig. 2 is the synoptic diagram of the data of expression embodiment of the present invention.

Fig. 3 is the process flow diagram of communication mode of the communication system of expression embodiment of the present invention.

Fig. 4 is the synoptic diagram of store status of packet buffer of the communication system of expression embodiment of the present invention.

Fig. 5 is the synoptic diagram of store status of packet buffer of the communication system of expression embodiment of the present invention.

Fig. 6 is the synoptic diagram of store status of packet buffer of the communication system of expression embodiment of the present invention.

Fig. 7 is the process flow diagram of store status of packet buffer of the communication system of expression control embodiment of the present invention.

Embodiment

Following with reference to accompanying drawing, preferred implementation of the present invention is elaborated.Below illustrated be embodiments of the invention, but the invention is not restricted to the following description.

Below an embodiment of the communication controler of present embodiment is described.Fig. 1 is the block scheme that expression is formed on the device controller in the end device.Wherein, device controller as communication controler is arranged in the end devices such as printer, end device is connected with principal computer (being designated hereinafter simply as main frame), and the CPU (central processing unit) (CPU) of CPU (central processing unit) of main frame (CPU:CentralProcessing Unit) and end device communicates by device controller.In addition, end device is connected by USB cable with main frame and communicates, but under the situation that the packets of information form with ISDN communication networks such as (Integrated Service Digital Network) communicates, can be that unit is stored in the communication controler and communicates too with the packets of information with information.In Fig. 1, omitted the CPU of main frame and end device.As shown in Figure 1, in USB device controller 10, be provided with usb interface unit (being designated hereinafter simply as PHY) 11, USB endpoint controller (end point controller) 12 and external bus interface unit (BCU:Bus Control Unit) 13.Usb interface unit 11 is by analog transceiver (analog transceiver) or serial interface engine formations such as (serial interface engine), the data of sending from main frame are carried out the serial parallel conversion, perhaps to resolving based on the data of USB controller or generation etc., the interface of control and usb bus carries out data communication.The bus that treating apparatus such as the CPU of external bus interface unit 13 control and end device or DMA (DirectMemory Access) controller are connected is carried out data communication.USB endpoint controller 12 constitutes two kinds of end points (end point): promptly receiving end points and transmit port promptly sends end points from the end device Data Receiving port of host receiving data, is the part of carrying out the buffering link of the data of main frame transmitting-receiving.In the present embodiment, USB endpoint controller 12 is had a transmission respectively describe, but also can have a plurality of transmissions with end points and reception end points with end points and reception situation with end points.In addition, USB endpoint controller 12 can be provided with a plurality of storeies, and making to receive with end points and send with any one or both in the end points becomes the double buffer formation.

Sending controling unit 14 is set in USB endpoint controller 12, receives control module 19, impact damper control module 24 and storer 25.Impact damper control module 24 indication sending controling units 14 and reception control module 19 distribute storer 25 as transmission buffer or reception buffer.As described later, impact damper control module 24 carries out following control, promptly determines that according to the communication pattern of main frame and end device the impact damper of storer 25 constitutes, and changes the store status that is stored in the data in the impact damper.At the packets of information number of control store in storer 25, the definite transmission used end points and received the impact damper of using end points when constituting, the transformation of the store status of the data of control store in impact damper.For example, the main storage means of distributing to cache memory impact dampers such as (Cache Memory) can be used as storer 25.In addition, as described later, and the hard disk auxilary units such as (HardDisk) of IDE (Integrated Device Electronics) mode between carry out under the situation of data communication, can distribute to the main storage means of disk speed buffering impact dampers such as (Disk Cache) and use as storer 25.Storer 25 can be used as common buffer, is sent out with end points and receives to use end points shared, comes the distributing buffer device according to sending with end points or receiving with end points.As mentioned above, under the situation of the storer that storer is constituted as double buffer, can be with uses that combines such as common buffer, reception buffer, transmission buffers.

Transmission PHY side control module 15, transmission switching mark (toggle flag) unit 16 are set in sending controling unit 14, send and use BCU side control module 17 and transmission buffer interface unit 18.Send with the data transmission of PHY side control module 15 controls, export then from impact damper sense data as transmission buffer to main frame.Send with PHY side control module 15 and have the read-out counter (read counter) corresponding with storer 25, output storage 25 read address (read address).Send and to write the storer 25 that is assigned as the impact damper of transmission buffer from the data of external bus interface unit 13 with BCU side control module 17.Send with BCU side control module 17 and have corresponding with storer 25 counter (write counter) that writes, output storage 25 write the address.Send with of the distribution of switching mark unit 16 diode-capacitor storages 25 to BCU side buffer or PHY side buffer, when the data transmission end of PHY side buffer, when storer 25 becomes dummy status, if the data that write the BCU side buffer are arranged, then trigger to send and use switching mark, switch.Send with buffer interface unit 18 and use switching mark, distribute the write address corresponding for the storer 25 that becomes the BCU side buffer, write the data of using BCU side control module 17 from transmission then with this storer 25 according to sending.In addition, send with buffer interface unit 18 and distribute the read address corresponding with this storer 25 to the storer 25 that becomes the PHY side buffer, sense data outputs to transmission usefulness PHY side control module 15 then.

Reception PHY side control module 20, reception switching mark unit 21 are set in receiving control module 19, receive and use BCU side control module 22 and reception buffer interface unit 23.Receive with PHY side control module 20 and will write impact damper from the data of main frame as reception buffer.Receive with PHY side control module 20 and have the write counter corresponding with storer 25, output storage 25 write the address.Receive with BCU side control module 22 from being assigned to storer 25 sense datas, and export as the common buffer of reception buffer.Receive with BCU side control module 22 and have the read-out counter corresponding with storer 25, output storage 25 read the address.Receive with of the distribution of switching mark unit 21 diode-capacitor storages 25 to BCU side buffer or PHY side buffer, data transmission end when the BCU side buffer, when storer 25 becomes dummy status, if the data that write the PHY side buffer are arranged, then trigger to receive and use switching mark, carry out the switching between BCU side buffer and the PHY side buffer.Receive with buffer interface unit 23 and use switching mark, provide corresponding with this storer 25 for the storer 25 that becomes the PHY side buffer, write the data of using PHY side control module 20 from receiving then from the address that writes that writes counter according to receiving.In addition, receive with buffer interface unit 23 and the read address from read-out counter corresponding with this storer 25 is provided for the storer 25 that becomes the BCU side buffer, sense data outputs to then and receives usefulness BCU side control module 22.

The USB endpoint controller 12 of present embodiment carries out following control, promptly by impact damper control module 24, give the buffer allocation storer 25 that sends with end points, and according to the communication pattern between main frame and the end device, the impact damper of determining storer 25 constitutes, and changes the store status that is stored in the data in the impact damper.USB endpoint controller 12 is according to the indication of using switching mark unit 16 from transmission, by sending with buffer interface unit 18, switch BCU side buffer and PHY side buffer from the storer 25 that constitutes impact damper, transformation is input to the transmission store status of the data of BCU side control module 17 at impact damper from external bus interface unit 13, simultaneously it is write in the storer that becomes the BCU side buffer.In addition, USB endpoint controller 12 is by sending with PHY side control module 15, and from storer 25 sense datas that become the PHY side buffer, the store status of data transfer in impact damper outputs to usb interface unit 11 simultaneously.

In addition, the USB endpoint controller 12 of present embodiment carries out following control, promptly by impact damper control module 24, give the buffer allocation storer 25 that receives with end points, and according to and end device between communication pattern, the impact damper of determining storer 25 constitutes, and changes the store status that is stored in the data in the impact damper.USB endpoint controller 12 is according to the indication of using switching mark unit 21 from reception, by receiving with buffer interface unit 23, switch BCU side buffer and PHY side buffer from the storer 25 that constitutes impact damper, transformation is input to the reception store status of the data of PHY side control module 20 at impact damper from usb interface unit 11, it is write in the storer 25 that becomes the BCU side buffer simultaneously.In addition, USB endpoint controller 12 is by receiving with BCU side control module 22, and from storer 25 sense datas that become the BCU side buffer, the store status of data transfer in impact damper outputs to external bus interface unit 13 simultaneously.

Below an embodiment of USB transmission action is described.The USB transmission process is by (the transaction data of a plurality of unit of transfer, transaction data) constitutes, for example under the situation of printer prints, when from main frame during to end device (printer) transmission data, the USB transmission process is made of a plurality of OUT transaction datas, reading in scanner under the situation of view data, when from end device (scanner) 2 during to main frame transmission data, the USB transmission process is made of a plurality of IN transaction datas.

Fig. 2 is the synoptic diagram of an embodiment of expression transaction data, as shown in Figure 2, transaction data 38 is made of 3 kinds of packets of information: marks packets (token packet) 38a, packet (data packet) 38b and synchronous exchange bag (handshake packet) 38c.Beginning most, the label information bag 38a with device address and terminal point information is sent to end device from main frame.Label information bag 38a is decoded by usb interface unit 11, and when detected mark (token) was considered to the mark of end device by decoding, the end points that distributes for data transmission was determined.When the end points of distributing to data transmission is determined, distributes to the end points numbering of data transmission and the kind of mark and be transmitted to USB endpoint controller 12.USB endpoint controller 12 is according to distributing to the end points numbering that data transmission distributes and the kind of mark, sends or the preparation of receiving data information bag 38b.For example, when transaction data 38 is OUT transaction data (reception), according to initial OUT label information bag 38a, determine that should receive end points by which receives data, receives the data packets 38b that sends from main frame by this reception end points that is determined then.Under the situation of USB device controller 10 shown in Figure 1, carried out the serial parallel data converted by usb interface unit 11 and be stored in the storer 25 of distributing to the impact damper that receives usefulness.When receiving by the reception end points that is determined, whether normally received and be stored in the storer by synchronous exchange bag notice host data from data packets 38b that main frame sends.USB endpoint controller 12 transmits synchronous exchange information to usb interface unit 11, and usb interface unit 11 generates synchronous exchange packets of information 38c according to synchronous exchange information, outputs to usb bus.

Constitute by continuous a plurality of transaction datas 38 from the data of main frame to the end device transmission, for example under the situation of Data Receiving, constitute by a plurality of OUT transaction datas, when using the reception end points, change the store status of impact damper, be converted to optimum condition by store status with the data in the impact damper, can be along with data are read in end device 2 from storer 25 (BCU side buffer), make the impact damper of storage data become dummy status, thereby can use storer 25 (PHY side buffer) to receive the data of back.

In order to read in the view data of scanner, and transmit under the data conditions to main frame from end device (scanner), according to the IN label information bag that begins most, determine that should send end points from which sends data, sends data by data packets 38b from determined transmission end points.If USB device controller 10 shown in Figure 1, then the data that are stored in the transmission buffer by 11 pairs of usb interface units are carried out the serial parallel conversion, send to main frame as data packets 38b then.USB endpoint controller 12 is according to the synchronous exchange packets of information 38c that returns from the main frame foldback, and whether judgment data sends successful.Usually, the processing that data send is made of a plurality of IN transaction datas, so when using the transmission end points, if can change the store status of impact damper, then by changing the state data memory in the impact damper into optimum condition, can make the impact damper of storage data become dummy status along with sending data from storer 25 (PHY side buffer), thereby subsequently in the writing data into memory 25 (BCU side buffer) from end device.

Under the situation that constitutes USB device controller 10 as mentioned above, impact damper control module 24 can be to the buffer allocation storer 25 that receives end points or transmission end points, according to the communication pattern between main frame and the end device, the packets of information number of control store in storer 25 determines that the impact damper of storer 25 constitutes.Therefore, impact damper control module 24 is stored in packets of information number in the storer 25 by change, can will be that the data storage that receives of unit is in storer 25 with the packets of information according to communication pattern.For example, utilizing 512 bytes of memory devices 25, under the situation about communicating with HS pattern or the message capacity FS pattern littler than HS pattern, impact damper control module 24 can the packets of information number of control store in storer 25, make that the capacity that constitutes a packets of information under the HS pattern is a packet buffer of 512 bytes, and can the packets of information number of control store in storer 25, make under the FS pattern, because a packets of information capacity is that high capacity transmits maximum information bag size 64 bytes of (bulk transfer), so 512 bytes of memory devices 25 comprise 8 packets of information and constitute.In addition, as described later, the packets of information number that 24 pairs of impact damper control modules are stored in the storer 25 is controlled, utilize the impact damper that becomes dummy status owing to data transmit-receive simultaneously, carry out the transformation of state data memory, reply thereby can avoid between main frame and end device, taking place NAK, prevent to send and wait for or receive wait.In the present embodiment, constituted USB device controller 10 as shown in Figure 1, in a word, can determine that the impact damper of storer 25 constitutes, and changes the store status of the impact damper of storage data by impact damper control module 24 according to connection mode.

Below describe to the communication mode of USB transmission with according to the storer of communication mode conversion store status.Fig. 3 is the process flow diagram of an example of store status that is illustrated in the impact damper of the storage data of carrying out between end device and the main frame.In Fig. 3, end device such as USB transmission utilizes the USB function element of USB2.0 standard, printer with as the basic computer of main frame by being connected as the HS pattern of communication mode or the connection mode of FS pattern, carry out the data communication of 512 bytes.In addition, utilize Fig. 3, the connection mode by HS pattern and FS pattern is sent data conditions describe, but also can be bit pattern down such as LS pattern for example, perhaps upper pattern than HS pattern.In this case, select the USB function element according to the connection mode of connecting terminal device and main frame.In the present embodiment, be temporarily stored in the data that communicate between main frame and the end device in the storer 25 of the impact damper of distributing to 512 bytes, but also can be impact damper with the upper size of such ratio 512 bytes of 1024 bytes for example.

As shown in Figure 3, be that unit sends a plurality of transaction datas (S41) from main frame with the packets of information to end device.At this moment, connect by USB interface between end device and the main frame,, under connection modes such as FS mode or HS pattern, connect, communicate as USB during for USB2.0 standard for example.When connection mode is the HS pattern, in order to store the data that size of data is 512 bytes, 512 bytes of memory devices 25 are constituted as an impact damper, thereby the data of 512 bytes are stored in the packet buffer (S42a).When connection mode is the FS pattern, rather than during the HS pattern, because the maximum information bag size of the high capacity of FS pattern transmission is defined as 64 bytes, so 512 bytes of memory devices 25 become 8 impact dampers formations that a capacity is 64 bytes, the data of 64 bytes are respectively stored in 8 packet buffer formations (S42b).Like this, because maximum information bag size is different along with connection mode, be different so the packets of information of 512 bytes of memory devices 25 is formed under HS pattern and the FS pattern.Therefore, determine that according to connection mode the impact damper of storer 25 constitutes, with data storage in each impact damper.A so-called packet buffer is meant that storage is data, the divided impact damper that unit receives with the packets of information, and the data of a packets of information are stored in the packet buffer.

Under the situation of the HS pattern that varies in size by the maximum information bag or FS pattern connecting terminal device and main frame, the formation of distributing to the impact damper of storer can be various formations.Below utilize Fig. 4, the configuration example that constitutes based on the impact damper that with the packets of information is a plurality of transaction datas of unit is described.In Fig. 4, the configuration example relevant with the impact damper of 512 bytes described, but also can be the impact damper of the upper size of the sort of ratio 512 bytes of 1024 bytes for example.Fig. 4 (a) shows to constitute with single impact damper 512 bytes of memory devices 25 is set, and the formation by the impact damper 41 under the HS pattern connection situation constitutes a packet buffer in this case same as described abovely.Shown in Fig. 4 (b), with constitute a packet buffer at HS pattern lower bumper relative, because maximum information bag size is defined as 64 bytes under the FS pattern, so impact damper 42 is constituted as 8 packet buffer (packet buffer 42a1 is to packet buffer 42a8) that a capacity is 64 bytes.Equally, can utilize Fig. 4 (c) and Fig. 4 (e), the impact damper when being connected with the FS pattern by the HS pattern constitutes and describes.This situation is that the double buffer that a storer is 512 bytes constitutes, shown in Fig. 4 (c), when connecting under the HS pattern, impact damper 43 is that a capacity is 2 packet buffer (packet buffer 43a1 and packet buffer 43a2) formation of 512 bytes.Shown in Fig. 4 (d), because maximum information bag size is defined as 64 bytes under the FS pattern, so the packet buffer under the HS pattern is split into 8 packet buffer of 64 byte capacities respectively, impact damper 44 is the formation of 16 packet buffer (packet buffer 44a1 to 44a16) on the whole.In addition, shown in Fig. 4 (e), under the situation that the double buffer that a storer is 512 bytes constitutes, impact damper 51 constitutes 2 packet buffer that a packet buffer is 64 bytes.

Below utilize Fig. 5, the example relevant with the transformation of the state data memory that is undertaken by the storer of distributing to impact damper described.Fig. 5 is the synoptic diagram of expression buffer stores state-transition.In Fig. 5, to being illustrated, but, in the such impact damper of printer buffer, change store status too sending under the data conditions to main frame from end devices such as scanners from the situation of main frame to end terminal device transmits data such as printers.In Fig. 5, be to constitute with single impact damper 512 bytes of memory devices 25 shown in above-mentioned Fig. 4 (b) are set, situation about under the FS pattern, connecting, but for constitute with double buffer be provided with and a capacity shown in the connection layout 4 (d) is 512 bytes of memory devices under the FS pattern situation too, store status that can data transfer.

In the constituted mode of the impact damper shown in Fig. 4 (b), when under the FS pattern, connecting, form 8 packet buffer formations that a buffer sizes is 64 bytes by 512 bytes of memory devices.When certain impact damper of 8 packet buffer during not from host receiving data, be dummy status, when having received size from main frame and be the data of a packets of information of 64 bytes, the data of a packets of information that is received are stored in (Fig. 5 (a)) among the packet buffer 42a1.At this moment, being stored in packets of information among the packet buffer 42a1 is the OUT label information bag with device address for example or terminal point information.When dividing 3 groups when main frame has received a packet size and is the packets of information such as data packets of 64 bytes, shown in Fig. 5 (b), the data of 3 packets of information are stored among the packet buffer 42a2 to 42a4 successively.Receiving each packets of information from main frame, when being stored in impact damper then, be stored among the packet buffer 42a5 shown in Fig. 5 (c), be data that unit altogether received 5 packets of information with the packets of information this moment, and packet buffer 42a1 becomes full state to packet buffer 42a5.The CPU that Fig. 5 (d) shows end device is reading the state that packet buffer 42a1 is the data in first packets of information that is stored in.When the data of packet buffer 42a1 were read end, shown in Fig. 5 (e), packet buffer 42a1 became dummy status.Shown in Fig. 5 (e), read in the process that is stored in the data among the packet buffer 42a1 at CPU, the data of packets of information such as synchronous exchange packets of information that receive from main frame are stored in the packet buffer 42a6.At this moment, CPU read the data that are stored among the packet-buffering 42a1 during, temporarily become the state that impact damper is used as the packet buffer of 6 packets of information of 64 bytes.

Become dummy status from the packet buffer 42a1 of impact damper 42, temporarily use the state of the packet buffer of 6 packets of information to begin, change the state data memory of impact damper 42.Shown in Fig. 5 (f), make and be stored in packet buffer 42a2 and move to packet buffer 42a1 to packet buffer 42a5 to the data in 5 packet buffer such as packet buffer 42a6, same with above-mentioned Fig. 5 (c), state data memory in the impact damper 42 is converted to data storage at the state of packet buffer 42a1 to 5 packet buffer such as packet buffer 42a5.By the data of mobile storage in 5 packet buffer of impact damper 42, packet buffer 42a6 becomes dummy status to packet buffer 42a8, and the packet buffer 42a6 that becomes dummy status becomes untapped state to packet buffer 42a8.Shown in Fig. 5 (g), the data of a packets of information that receives from main frame are stored in becoming dummy status and the untapped packet buffer 42a6 of impact damper 42.Then, data in being stored in packet buffer 42a1 are read by the CPU of end device once more, when packet buffer 42a1 becomes dummy status, being stored in packet buffer 42a2 (containing) data afterwards is moved, and during each sense data, the packet buffer of storage data all changes.The transformation of state data memory is carried out by impact damper control module 24, can wait according to the address that is stored in the data in the impact damper and carry out.For example, when the data that make each packets of information as shown in Figure 5 move, impact damper control module 24 calculates the address of the data of packet buffer 42a2, make the address that is stored in the data among the packet buffer 42a2 become packet buffer 42a1, be stored in the address that the data allocations among the packet buffer 42a2 calculates then, the data shift that makes packet buffer 42a2 is to packet buffer 42a1.In addition, with the data that are stored in packet buffer 42a2 similarly, impact damper control module 24 is redistributed the address that is stored in the data of packet buffer 42a3 to 4 packets of information such as packet buffer 42a6, make it be displaced to packet buffer 42a2 to packet buffer 42a5, thus the data transfer store status.

Like this, can be according to communication patterns such as HS pattern or FS patterns, the packets of information number of control store in storer 25, the impact damper of determining storer 25 constitutes, simultaneously by changing the store status of impact damper, thereby can be according to each communication pattern, with the data efficient that communicates be stored in the storer 25.Therefore, can a plurality of packets of information be stored in the storer 25 efficiently, reply, prevent to send and wait for and the reception wait, prevent the decline of communication speed thereby can avoid taking place between main frame and the end device NAK according to communication pattern.For example, as shown in Figure 5, under the data that make residual packets of information move to situation in the impact damper of dummy status, data can be stored in again in the memory address of the residual packet data of storage, with the packets of information data of unit thereby can store what received reliably.Therefore,, can efficiently and reliably packet data be stored in the impact damper, just can not send data thereby wait can not appear sending in the main frame of transmission data when when impact damper sends packet data.Like this, can come the bag number of the packets of information of control store in storer 25 according to communication pattern, efficiently with data storage in storer 25, this can not only prevent the decline of data signaling rate, and can improve data signaling rate by the store status that changes impact damper.

In addition, as shown in Figure 5, in the store status that changes impact damper, residual packet data is moved under the situation in the impact damper of dummy status, the data that sent can be moved among the packet buffer 42a1, thereby can send packets of information to the CPU of end device from packet buffer 42a1.Therefore,, can utilize the memory address of the impact damper 42 that becomes dummy status, send data efficiently, thereby can not make data signaling rate send data with descending by sending packets of information.In addition, descend owing to can prevent data signaling rate, so wait can not appear reading in the CPU of end device, just can sense data.

In addition, when changing the store status of impact damper, be that the order of the data of unit changes store status, thereby can control the order of the data that send from storer 25 according to sending with the packets of information.For example, as shown in Figure 5, after though the data of Jie Shouing are stored among the packet buffer 42a1 at first, sent from storer 25 at first, but because the data that are stored among the packet buffer 42a2 are moved among the packet buffer 42a1, send data from storer 25 then, so can send data according to the order that is stored in the data in the storer 25.Like this, by the order of control, the packets of information that is received can be stored in the storer 25 reliably, and can send data in order efficiently from the packets of information that is received from the data of storer 25 transmissions.

Below utilize Fig. 6, another embodiment relevant with the transformation of the store status of carrying out in impact damper described.Fig. 6 is the synoptic diagram of transformation of the store status of expression impact damper.In Fig. 6, CPU from main frame is illustrated to hard disk auxilary units such as (Hard Disk) the transmission data conditions of IDE (Integrated Device Electronics) mode, but send data conditions too from auxilary unit to the CPU of main frame, in disk speed buffering impact dampers such as (Disk Cache), change store status.Fig. 6 constitutes the situation that 2 512 bytes of memory devices are set with double buffer shown in above-mentioned Fig. 4 (d), but the usefulness single impact damper of figure shown in (b) constitutes 512 bytes of memory devices is set, the store status that situation about connecting under the FS pattern too can data transfer.To the data unit that sends to auxilary unit is that the situation of 1 sector (sector), 512 bytes is illustrated, but the size of 1 sector also can be the sizes beyond 512 bytes.

In the constituted mode of the impact damper shown in Fig. 4 (d), when under the FS pattern, connecting, impact damper 44 is in 2 512 bytes of memory devices, and the size that constitutes an impact damper is 16 packet buffer (packet buffer 44a1 is to packet buffer 44a16) of 64 bytes.When 16 packet buffer are not dummy status when the CPU of main frame receives data, when the CPU from main frame divides 3 group of received sizes to be the packets of information of 64 bytes, the data of 3 packets of information that received are stored in packet buffer 44a1 to packet buffer 44a3, and the data of 3 packets of information are written into (Fig. 6 (a)) in the auxilary unit then.At this moment, be stored in packet buffer 44a1 to the packets of information among the packet buffer 44a3 be for example label information bag or data packets.When the CPU from main frame divides the size of data of a packets of information of 5 group of received to be the packets of information such as data packets of 64 bytes, shown in Fig. 6 (b), the data of 5 packets of information are stored in packet buffer 44a4 in order to packet buffer 44a8, and the data of 5 packets of information are written in the auxilary unit then.Like this, after the CPU of main frame receives each packets of information, it is stored in the impact damper, shown in Fig. 6 (b), with the packets of information is the data that unit has received 8 packets of information altogether, and the packet buffer 44a1 of impact damper 44 becomes the state that fills up to packet buffer 44a8.At this moment, auxilary unit writes a sectors of data by the CPU of main frame, and can not write wait.Then, send in for example transmission request according to the CPU of main frame, perhaps become under the situation of the pattern that automatically sends according to the transmission situation, shown in Fig. 6 (c), to the data of 2 packets of information of the CPU of main frame transmission, thereby packet buffer 44a1 and packet buffer 44a2 become dummy status.In addition, in Fig. 6 (c), auxilary unit in the CPU that data is read into main frame in, receive the data of 3 packets of information, and the packet buffer 44a9 that is stored in dummy status is to packet buffer 44a11.And then shown in Fig. 6 (d), send the data of packet buffer 44a3 to 5 packets of information of packet buffer 44a8 to the CPU of main frame.At this moment, when the CPU to main frame sends data, the data of 5 packets of information such as data packets that receive from the CPU of main frame are stored in packet buffer 44a12 to packet buffer 44a16, and the data of 5 packets of information are written in the auxilary unit.At this moment, sending packet buffer 44a1 to the CPU of main frame during the data of packet buffer 44a8, impact damper temporarily becomes the state that the impact damper 44 as 16 packets of information of 64 bytes uses.

Become dummy status from the packet buffer 44a1 of impact damper 44 to packet buffer 44a8, temporarily use the state of the impact damper of 16 packets of information to begin, change the state data memory in the impact damper 44.Shown in Fig. 6 (e), make and be stored in packet buffer 44a9 and move to packet buffer 44a1 to packet buffer 44a8 to the data in 8 packet buffer such as packet buffer 44a16, same with above-mentioned Fig. 6 (b), make state data memory in the impact damper 44 change state in packet buffer 44a1 storage data to 8 packet buffer such as packet buffer 44a8.Thus, can write the data of 8 packets of information of a sector in the auxilary unit, and write wait can not send data the time.By the data of mobile storage in 5 packets of information of impact damper, can make packet buffer 44a9 become dummy status to packet buffer 44a16, and make the packet buffer 44a5 that becomes dummy status become untapped state to packet buffer 44a8.Then, continue to be sent to the CPU of main frame to the data among the packet buffer 44a8 when being stored in packet buffer 44a1, and the data of the packets of information that receives from the CPU of main frame are stored in packet buffer 44a9 to packet buffer 44a16, when packet buffer 44a1 becomes dummy status to packet buffer 44a8, the data of 8 packets of information of a sector of auxilary unit are moved.The transformation of state data memory is carried out by the impact damper control module, can wait according to the address that is stored in the data in the impact damper and carry out.For example, when the data that make each packets of information as shown in Figure 6 move, the impact damper control module calculates the address of the data of packet buffer 42a9, make the address that is stored in the data among the packet buffer 42a9 become packet buffer 42a1, give the data that are stored among the packet buffer 42a9 address assignment that calculates then, the data shift that makes packet buffer 42a9 is to packet buffer 42a1.In addition, with the data that are stored in packet buffer 42a9 similarly, the impact damper control module is redistributed the address to being stored in the data of packet buffer 42a10 to 7 packets of information such as packet buffer 42a16, make it be displaced to packet buffer 42a2 to packet buffer 42a8, thus the data transfer store status.

Like this, can be according to communication patterns such as HS pattern or FS patterns, the packets of information number of control store in storer 25, the impact damper of determining storer 25 constitutes, simultaneously by changing the store status of impact damper, thereby can be according to each communication pattern, with the data efficient that received be stored in the storer 25.Therefore, can a plurality of packets of information be stored in the storer 25 efficiently, reply, prevent to send and wait for and receive and wait for, prevent the decline of communication speed thereby can avoid taking place between the CPU of main frame and the auxilary unit NAK according to communication pattern.For example, as shown in Figure 6, under the situation in the impact damper that will the data suitable moves to dummy status with a sector of auxilary unit, data can be stored in again in the memory address of a sectors of data of storage, thereby can store what received reliably is the data of unit with the packets of information, and data are write in the auxilary unit.Therefore,, can efficiently and reliably packet data be stored in the impact damper, just can not send data thereby wait can not take place to send the main frame of transmission data when when impact damper sends packet data.Like this, can come the bag number of the packets of information of control store in storer 25 according to communication pattern, efficiently with data storage in storer 25, this can not only prevent the decline of data signaling rate, and can improve data signaling rate by the store status that changes impact damper.

In addition, as shown in Figure 6, in the store status that changes impact damper, make under the situation to the impact damper of dummy status of a sector that residual packet data moves auxilary unit, can send a sectors of data by the CPU to main frame from packet buffer 44a1 to packet buffer 44a8.Therefore,, can utilize the memory address of the impact damper 42 that becomes dummy status, send data efficiently, thereby can not make data signaling rate send data with descending by sending packets of information.In addition, descend,, just can obtain data, a sectors of data of auxilary unit is read out together so wait can not appear reading in the CPU of end device owing to can prevent data signaling rate.

In addition, when changing the store status of impact damper, be that the order of the data of unit changes store status, thereby can control the order of the data that send from storer 25 according to sending with the packets of information.For example, as shown in Figure 6, though at first the data of Jie Shouing be stored in the packet buffer 44a1 suitable with sector to packet buffer 22a8 after, sent from storer 25 at first, but because packet buffer 44a9 that will be suitable with a sector of auxilary unit moves to packet buffer 44a1 to packet buffer 44a8 to packet buffer 44a16 data, send data from storer 25 then, so can send a sectors of data according to the order that is stored in the data in the storer 25.Like this, by the order of control, the packets of information that is received can be stored in the storer 25 reliably, and can from the packets of information that is received a sectors of data be write the auxilary unit together efficiently in order from the data of storer 25 transmissions.

Below the communication mode according to USB transmission is changed the store status of storer the impact damper control module describe.Fig. 7 is the process flow diagram of an example of the expression action that makes the control module that the store status of storer changes.At first, in flow process illustrated in fig. 3, the communication pattern between given host and the end device determines that the impact damper of storer 25 constitutes (S50) to impact damper control module 24 according to.So far, though to utilizing constituting shown in Fig. 4 (b) that 512 bytes of memory devices 25 are set according to single impact damper, situation about connecting under the FS pattern describes, but for constituting according to double buffer that a capacity is set is 512 bytes of memory devices shown in Fig. 4 (d), situation about connecting under the FS pattern, the impact damper control module is controlled similarly.At first, under situation about communicating under the FS pattern, the 512 bytes of memory devices that constitute as a packet buffer when impact damper control module 24 will connect under the HS pattern are divided into 8, make that the capacity of each packet buffer is 64 bytes.Then, shown in S51,24 pairs of institutes of impact damper control module canned data bag is discerned.At this moment, impact damper control module 24 is for example according to the address of the storer of canned data bag, the memory address of identification canned data bag from the label information bag.The impact damper control module 24 of the packet buffer of identification canned data bag for example confirms whether to have the packets of information that receives from main frame, when the packets of information that receives, and the packets of information (S53b) that storage is received.The impact damper control module is discerned canned data bag once more under the state of having stored the packets of information that is received.Shown in S52, under the situation that does not receive packets of information, whether the identification of impact damper control module for example has the packets of information (S53a) of being read and sending by the CPU of end device, when packets of information that existence is sent out, owing to the packet buffer of dummy status occurs, so discern the packet buffer (S54a) of dummy status, change the store status (S55) of impact damper integral body then.The transformation of buffer stores state is moving of packets of information integral body for example shown in Figure 5 etc.Shown in S53a, under the situation of the packets of information that does not have to send, the impact damper control module confirms whether to exist the impact damper (S54b) of dummy status under the state that does not send packets of information, the if there is no packet buffer of dummy status, then return the step S52 whether affirmation exists the packets of information of reception, and then carry out above-mentioned steps.Under the situation of the packets of information that does not have to send, when having the packet buffer of dummy status, with above-mentioned same, shown in S54a, the packet buffer of identification dummy status, the store status (S55) of transformation impact damper integral body.The impact damper control module returns the step shown in S51 after the store status that changes impact damper, once more the store status of impact damper is discerned the conversion of control store state.

As mentioned above, the impact damper control module can change the formation of impact damper with connection modes such as FS pattern or HS patterns accordingly by carrying out above-mentioned action, realizes the transformation of buffer stores state.The impact damper control module can be stored in packets of information again in the stored memory address of residual packet data, thereby can efficiently packets of information be stored in the impact damper by the transformation of controller buffer store status.In addition, wait can not take place to send the data sending devices such as main frame that send data just can send data, thereby can prevent the decline of data signaling rate.

In addition, the impact damper control module can constitute impact damper according to connection mode, will be with the packets of information unit data efficient be stored in the storer 25, and can change the store status of impact damper, data are stored in the storer 25 more efficiently.Therefore, can not only come the bag number of the packets of information of control store in storer 25 according to communication pattern, with data efficient be stored in the storer 25, prevent the decline of data signaling rate, and can further improve data signaling rate by changing the store status of impact damper.

As mentioned above, using for example USB cable of USB2.0 standard, main frame and end device are carried out under the situation that USB is connected, in the process that communicates by the FS pattern, make the store status transformation of distributing to the impact damper of storer by the impact damper control module, thereby can give a plurality of packet buffer of memory allocation, data are stored in transmission again become in the packet buffer of dummy status afterwards.Therefore, even under situation about communicating by the FS pattern, also packets of information can be stored in efficiently in the impact damper and communicate, thereby can not taking place to receive, do not wait for by the main frame that sends data, and can not take place the NAK of main frame is replied, main frame just can send data.Like this, because main frame can not take place to send wait or NAK replys, just can send data, so, also can under the situation that does not reduce data signaling rate, carry out data communication even when communicating by the FS pattern.

In addition, using for example USB cable of USB2.0 standard, send under the data conditions to main frame from end device, in the process that under the FS pattern, communicates, make the store status transformation of distributing to the impact damper of storer by the impact damper control module, data are deposited in the impact damper that becomes dummy status once more, thereby can send data efficiently from the impact damper of having stored data once more.Therefore, even when utilizing the FS pattern to communicate, main frame can receive wait for not taking place, and end device is not taken place to receive data under the situation that NAK replys.Like this and since main frame can do not receive wait for or situation that NAK replys under receive data, so, also can under the situation that does not reduce data signaling rate, carry out data communication even when utilizing the FS pattern to communicate.

In addition, carry out data are write under the situation of the data communication in the auxilary unit at the CPU of main frame, the transformation of the store status by controller buffer can write a sectors of data simultaneously.Therefore, the CPU of main frame can with data efficient write in the auxilary unit, thereby can improve writing speed to auxilary unit.Carry out under the situation of the data communication of auxilary unit sense data too at the CPU of main frame, the transformation of the store status by controller buffer, can read in a sectors of data simultaneously, with data efficient read in the auxilary unit, thereby can improve the CPU of main frame and the data signaling rate between the auxilary unit.

The present invention can provide a kind of communication controler and communication means, is being that unit carries out in the information communication process with the packets of information, produces the state of rejection between the main frame that can prevent and communicate.

Claims

1. a communication controler is that unit receives the information corresponding with plurality of communication schemes with the packets of information, sends after the temporary transient storage, and the quantity of information that above-mentioned plurality of communication schemes comprises in a packets of information is different,

It is characterized in that, comprising:

Storage unit, the above-mentioned information that temporary transient storage is received; And

Control module comes the packets of information number of control store in said memory cells according to above-mentioned communication pattern,

Under the communication pattern that a plurality of packets of information can be stored in the said memory cells, above-mentioned control module is set the memory address of a plurality of packets of information in said memory cells, a plurality of packets of information temporarily are stored in the said memory cells.

2. communication controler according to claim 1, it is characterized in that, under the communication pattern that a plurality of packets of information can be stored in the said memory cells, above-mentioned control module is by changing the memory address of the packets of information in this storage unit, the store status of coming the transition information bag.

3. communication controler according to claim 2 is characterized in that, other packets of information that above-mentioned control module is stored by making move to because packets of information is sent out in the memory address that becomes dummy status, come the store status of transition information bag.

4. communication controler according to claim 2, it is characterized in that, above-mentioned control module is by sending above-mentioned packets of information according to the order that is stored in the storage unit, the packets of information that will send is subsequently moved to owing to packets of information is sent out in the memory address that becomes dummy status, come the store status of transition information bag.

5. communication controler according to claim 1 is characterized in that,

Above-mentioned plurality of communication schemes comprises the second communication pattern that the quantity of information that comprises in first communication pattern and the packets of information is lacked than above-mentioned first communication pattern,

Said memory cells has the memory capacity of the packets of information that is equivalent to the quantity of information corresponding with above-mentioned first communication pattern,

Above-mentioned control module temporarily is stored in a packets of information in the said memory cells when receiving the packets of information of above-mentioned first communication pattern, when receiving the packets of information of above-mentioned second communication pattern, a plurality of packets of information temporarily is stored in the said memory cells.

6. communication controler according to claim 1 is characterized in that above-mentioned information communicates by USB (universal serial bus), and this USB (universal serial bus) is USB 2.0 standards.

7. a communication means is that unit receives the information corresponding with plurality of communication schemes with the packets of information, temporarily is stored in the storage unit to send afterwards, and the quantity of information that above-mentioned plurality of communication schemes comprises in a packets of information is different,

It is characterized in that, may further comprise the steps:

The pattern given step is specified above-mentioned communication pattern; And

Controlled step, according to specified communication pattern, the packets of information number of control store in said memory cells,

In above-mentioned pattern given step, when having specified the communication pattern that a plurality of packets of information can be stored in the said memory cells, in said memory cells, set the memory address of a plurality of packets of information,

In above-mentioned controlled step, under the communication pattern that a plurality of packets of information can be stored in the said memory cells, a plurality of packets of information temporarily are stored in the packets of information memory address of said memory cells.

8. communication means according to claim 7 is characterized in that, under the communication pattern that a plurality of packets of information can be stored in the said memory cells, by changing the packets of information memory address in this storage unit, the store status of coming the transition information bag.

9. communication means according to claim 8 is characterized in that, other packets of information of storing by making move to because packets of information is sent out in the memory address that becomes dummy status, come the store status of transition information bag.

10. communication means according to claim 8, it is characterized in that, by sending above-mentioned packets of information according to the order that is stored in the said memory cells, the packets of information that will send is subsequently moved to owing to packets of information is sent out in the memory address that becomes dummy status, come the store status of transition information bag.

11. communication means according to claim 7 is characterized in that,

In above-mentioned pattern given step, when having specified above-mentioned second communication pattern, in said memory cells, set the memory address of a plurality of packets of information,

In above-mentioned controlled step, when having received the packets of information of above-mentioned first communication pattern, a packets of information temporarily is stored in the said memory cells of the suitable memory capacity of packets of information with quantity of information corresponding with above-mentioned first communication pattern, when having received the packets of information of above-mentioned second communication pattern, a plurality of packets of information temporarily are stored in the said memory cells.

12. communication means according to claim 7 is characterized in that, above-mentioned information is to communicate by USB (universal serial bus), and this USB (universal serial bus) is USB 2.0 standards.