KR100562805B1 - Content addressable memory - Google Patents

Abstract

The two-dimensional decoding required to achieve a suitable array aspect ratio for large content addressing memories has multiple match lines per physical row, and these match lines are routed on top of the array core cells in the upper metal layer. Is realized. In order to limit the power consumption of large content addressing memories, the match function is realized with two or more NAND chains per word. Also disclosed are means for achieving precharging and evaluation of such chains and for realizing dummy chains for providing timing information.

Description

Content Addressing Memory {CONTENT ADDRESSABLE MEMORY}

The present invention relates to a content addressable memory (CAM).

A CAM is a storage device that is selected based on its content, not its physical location. This feature is useful for many applications, especially when performing lock-up to map long identification words to shorter words. This task is required for numerous telecommunications functions, including asynchronous transfer mode (ATM) address translation.

February 22, 1994, J.D. U.S. Patent 5,289,403, entitled "Self-Timed Content Addressable Memory Access Mechanism with Built-In Margin Test Feature," titled Yetter, entitled "Self-Timed Content Addressable Memory Access Mechanism with Built-In Margin Test Feature." Means are provided for providing self-timing to a NOR match line CAM using dummy columns and dummy rows. While all other cells in the row are always matched, the bits of the intersection of the dummy column and the dummy row are always missed, which creates the slowest mismatchable state on the dummy match line. Next, it generates a clock to time the next event and evaluate all other match lines.

U.S. Patent 5,453,948, issued to M. Yoneda on September 26, 1995 and entitled "Associative Memory", discloses a low power implementation of a matchline realized as a serial chain instead of a NOR.

Associative Memory Device with Small Memory Cells Selectively Storing Data Bits and Don, issued to H. Yamada on October 3, 1995 and entitled "Data Bits and Don Care Bits." US Patent No. 5,455,784, "t Care Bits", discloses a CAM with individual storage cells consisting of a series combination of two EEPROM devices. The serial connection of the cells (1 per bit) forming the word of CAM forms a serial match line chain. The programmatically shifted transistor threshold voltage allows the EEPROM device to operate as an enhancement or depletion mode transistor, and "don't cares" can be stored by putting both devices in depletion mode. .

Content Addressable Memory Having Match Line Transistors Connected in Series and Coupled to R. Albon et al. to Current Sensing Circuit, "US Patent No. 5,469,378, discloses a serial match line chain.

Most previous CAMs employ a dynamic wired NOR (line of wire) match line pull down, which provides a high throughput rate, but the prior art circuit configuration does not match the match lines associated with mismatched words. Undergoes a transition, but no transition occurs on the match lines associated with the matched words, because the number of matches is much smaller than the number of mismatches, i.e., the number of transitions, Excessive

The present invention is intended to realize a sufficient capacity CAM, for example, for ATM address transition table applications. The disadvantages of the techniques known as prior art are due to both architectural and circuit limitations. The two design problems addressed by the present invention are: (i) realization of the two-dimensional decoding necessary to achieve a suitable array aspect ratio for large memory, and (ii) simultaneously searching the entire contents of a large capacity CAM. Low power consumption.

In order to realize two-dimensional decoding, multiple words must exist within a single physical row. This can be done by (a) sharing match lines between multiple words, or (b) having multiple match lines per physical row. In the present invention, the second method is chosen.

According to the main features of the present invention,

When w, i, and b are integers, as word matching means, each word includes I segment match line chains, each match line b / i core cells chained by the matchline. Each core cell comprising: means for matching a w word comprising means for storing data;

Logic means for logically combining match line chains in each row; And

Encoding means for providing a search result based on the output from the logic means

A content addressing memory (CAM) comprising a is provided.

For example, the logic means includes NAND circuit means. In the case of a NAND circuit, which is a dynamic NAND circuit, power consumption is reduced. The CAM further includes means for sensing a transition of the data signal on the chain. In CAM, the cell array is directed in a mirror image such that the outputs face each other, thereby facilitating a logical combination of two partial match results generated from the two cell arrays by logic means.

CAM can use dummy words, but not dummy columns. In addition, the dummy word models a match, not a mismatch. The word in the CAM is divided into a plurality of segments with match line chains per segment. CAM uses purely voltage sensing means.

The invention will be better understood from the following detailed description with reference to the accompanying drawings.

Many of the prior art CAMs use a wired-NOR match line as shown in FIG. Referring to Fig. 1, a single chip CAM of w (= 4) word x b (= 4) bits is realized as a CAM with w rows and b columns. The memory cell array includes w x b (= 16) memory core cells 110 disposed at the intersection of the match line 112 and the pair of bit lines 114, respectively. The pair of bit lines 114 carry differential data representing one bit of data rather than two bits of data. Each core cell 110 operates to store one bit of data and may perform a one bit compare (logical exclusive NOR (XNOR)) operation in addition to its bit storage capability. In FIG. 1, cells 110 belonging to a given word are connected to the match line 112 of that word in a logical NOR manner.

Bit lines 114 for differential data are connected to a bit word driver 116 and a reference word memory that receives the input data D for loading the contents of the CAM and the search reference word. Data stored in the core cells 110 of the array is retrieved by using the reference word on the bit lines 114.

When differential data is asserted on a pair of bit lines 114 in a seek operation, core cell 110 compares its stored data bits with differential data (or reference data, or known as a one-bit comparison operator). do. When the stored data is not the same as the reference data, the core cell 110 pulls down the match line 112 (precharged to a logic high state) in a low state. When the stored data is the same as the reference data, the cell 110 does not produce a result on the match line 112 to which it is connected. Since all b core cells 110 in a given word are connected to match line 112 in the same manner, if any bit in that word is not equal (or mismatched) to the corresponding reference bit, match line 112 Becomes low. Match line 112 remains logical high only when all the bits in that word are equal to the reference data.

The CAM includes an encoder 118 that produces three outputs representing the results of the search operation. If any of the w words are storing data that matches the reference data, the hit signal hit will indicate a logic high state. The binary address of this matching word is encoded to provide the address signal sa. When a plurality of words match the reference data, the majority match signal mult indicates a logic high state. In such a case, the address sa output of encoder 118 may be a sequence of outputs representing (a) an invalid result, (b) a address indicating the position of one of the multiple matches, or (c) the positions of each of the matched words. Will produce.

Large capacity alternative CAMs with successive time division comparators and multiple match lines on each core cell were described in K.J. US patent application Ser. No. 08 / 748,928, filed by Schultz et al., Entitled " Content Addressable Memory ", which is used herein by reference. The CAM employs a dynamic wired-NOR match line pull down and does not place in core cells, but instead includes 1-bit comparators that are time-divided among multiple words. This circuit configuration causes match lines connected to mismatched words to undergo a transition, and does not cause a transition to the matched words.

Since only one or at most several matches are expected to occur, the number of transitions and the resulting power consumption will be excessive for the NOR match line.

2 illustrates a CAM according to an embodiment of the invention. Referring to FIG. 2, a w (= 4) word is shown, each occupying one row and having b (= 8) bits and b (= 8) core cells 210, respectively. The word is divided into two halves and the result of the match on each half word is combined. Each two halves are provided in an array of four rows by four columns. The array includes sixteen core cells 210 each disposed at the intersection of a pair of bit lines 214 carrying a match line 212 and a differential data representing one bit. Bit lines 214 for differential data are connected to a bit word driver 216 and a reference word memory that receives the input data D for loading the contents of the CAM and searching for the reference word. Data stored in array core cells 210 is retrieved by using a reference word on bit line 214.

Each core cell 21 is operable to store one bit of data and can perform one bit compare (logical exclusive NOR (XNOR)) operations in addition to the bit storage capability. In FIG. 2, cells 210 belonging to a given word are connected to the match line 212 of that word in the logical NAND form. The core cells 210 of each word are chained within each match line 212. One end of each chain is connected to an inverter 218. The other end of the chain is connected to the terminal of logic zero. The outputs of the inverters 218 are connected to an AND gate 220, whose output is referred to as a "word match line" 224 and is connected to an encoder 222.

In Fig. 2, the connections (half words each) are logical NAND. If all bits in the half word are the same as the reference data, match line 212 will only have a downward transition. Therefore, the path to ground for match line 212 is in series ("match line chain") rather than parallel, and this path is in a conductive state (i.e., circuit closed) in the case of a non-match match.

The advantage of this technique is due to the smaller number of match lines 212 transitioning in each search operation (the embodiment shown in FIG. 2 compared to one per mismatch in the prior art circuit shown in FIG. 1). 1 per match). This significantly reduces power consumption, enabling the realization of a larger memory capacity. Dividing the word in half increases the speed by reducing the length of the NAND chain.

The embodiment of the CAM shown in FIG. 2 also includes means for placing multiple words in a physical row by using an upper metal layer over the core cell for multiple word match lines 224. This increases the possible storage capacity.

The CAM generates three output signals hit, sa, and mult representing the results of the search operation, all of which can be generated by encoder 222. If any of the w words is storing data that matches the reference data, the hit signal hit indicates a logic high state. The binary address of this matching word is encoded to provide the address signal sa. When a plurality of words match the reference data, the majority match signal mult indicates a logic high state. In this case, the address sa output of encoder 222 is a sequence of outputs representing (a) an invalid result, (b) a address indicating the position of one of the multiple matches, and (c) the positions of each of the matched words. Can be generated.

The CAM shown in FIG. 2 uses a low power circuit equivalent to a NOR match line. The logical equivalent of NOR is NOT-AND, as shown in FIG. Therefore, instead of checking if any bit is a mismatch and generating a logical m1 = match, it can be checked if all bits are a match (if it is a pull down), producing a logical m1n = match. The choice of Boolean implementation has little transition (since transition only occurs in the case of a match), thus consuming low power. Unfortunately, dynamic NAND is obviously slower than dynamic NOR. This is particularly valid for wide words (b> 16). On the other hand, delays caused by long pull down chains, etc., are tolerated for advanced CMOS technology, particularly for "slow" (<100 MHz) applications. On the other hand, it would be advantageous to use several steps to reduce the delay. This is easily done by dividing the word into number I ≧ 2 segments and combining them into one serial chain per segment as shown in FIG. This simultaneously satisfies the design goal of realizing high speed and wide word.

When each first stage NAND is realized as a dynamic gate, it is evident that more transitions and higher power are made due to partial word matches. Therefore, successive power-speed trade-offs result in more segmented word segments, resulting in higher speed and power, and the logical extremes of both speed and power become NOR. The other extreme at low power and low speed is one NAND chain, which is equally undesirable. Since the implementation of the simplest division is to split into i = 2 chains, this will apply to the example embodiments shown in FIGS. 5A, 6A, and 7A.

FIG. 5A shows a match line circuit composed of two segments (two chains) used in the CAM shown in FIG. 2. 5B conceptually illustrates first and second segments (chains) 522 and 524. 5A, the N-channel FETs of match line chains are clearly shown with the core cells. Each of the match line chains is connected to an inverter 218 and each output of the two inverters 218 is connected to an AND gate 220. In two divided words, the second chain 524 is oriented as a mirror image of the first chain 522 and brings them together so that their outputs face each other. In FIG. 5A, the chain is physically realized as a pull down chain and has a GND (or VSS) connection used at one end opposite the output of the chain. Alternatively, the chain is realized as a pull up chain, with the power supply (or VDD) connection used at one end opposite the output of the chain, and the inverters are logically removed.

The word match line must be routed to the encoder, and the actual physical address information is obtained from the match information as shown in FIG. 2 above. This routing is most easily done in core cells at the highest level of available metal. This was done assuming that the encoder is on the right in FIG. 6A. If this is enlarged, as shown in FIG. 6B, it is possible to extend a plurality of match lines on each core cell and to place a plurality of rows of words adjacent to the same encoder. The capacity, which is a multiple of four words, can be achieved by stacking a plurality of said units in the vertical direction.

If the number of word match lines on each core cell (actually, the number of word match lines on the core cells closest to the encoder) is m, there will be m words adjacent to each other without intervening the encoder. As shown in Figs. 7A and 7B, the encoder is not limited to one. There is a 2xm word associated with each encoder per row.

If the number of encoders is e, there will be 2 x m x e words per row. If the number of rows is r, the array will have a capacity of 2xmxexr words. The output of the e encoder will be combined at the physical bottom or top of the array as shown in FIG. 7B.

If the word is divided into I> 2 segments instead of correctly i = 2 segments, the output of the circuit as shown in Figs. 5A and B shows a partial word result rather than the actual word match line. These partial word results can be immediately combined adjacent to the encoder as shown in FIGS. 8A and 8B.

The parameters are summarized as follows.

The number of word match lines extending over each core cell is m.

The sum of the number of word match lines extending over each core cell and the number of partial word result lines is i × m / 2 (i is assumed to be even, but odd may be possible).

The number of word match lines per physical row is also the same as the number of words per physical row, which is 2 × m × e.

• The number of inputs to each encoder per row is 2 x m.

FIG. 9 shows an example of the memory core cell 210 of the CAM shown in FIG. 2. The core cell shown in FIG. 9 is a transistor level core cell. The cell consists of two static memory nodes and two cross-coupling inverters between two access FETs 710 and 712 gated by word line wl to pair memory nodes c and cn with a pair of bit lines. To bl and bln. This is a known arrangement for static SRAM core cell (inverters of P- and N-channel FETs). The other three N-channel FETs 721, 723, and 725 form a comparison of the cell. The gate, drain, and source of the FET 721 are connected to the negative memory node cn, the negative comparison bit line kn, and the gate of the FET 723, respectively. The gate, drain, and source of the FET 725 are connected to the positive memory node c, the positive comparison bit line k, and the gate of the FET 723, respectively. FET 723 itself forms part of the match line chain and constitutes the device shown in FIGS. 5A and 8A, the source and drain of which comprise a suitable location in the chain, a similar FET in adjacent cells, or any end of the chain. Is connected to a circuit.

The comparison bit line k / kn is physical wires separated from the standard bit line pair bl / bln and extends parallel to them in the vertical direction. Using separate wiring reduces each capacitive load, thus reducing power consumption and increasing speed. It also enables independent setting of the stop state in the storage access device and the comparison device. bl / bln remains high during the search in preparation for the next read or write, and k / kn remains high or low during the read or write while preparing for the next search.

The function performed by the cell is (a) to store one bit of data, and (b) to be on if the compare bit matches the stored bit, and to off if the compare bit is mismatched with the stored bit. This is a combination of device switching of a match line chain. That is, if the binary value stored in node c matches the comparison operator on line k, FET 723 is in a conductive state. In order to mask a given bit from a search, it must be ensured that the binary values are always matched and the chain of FETs 723 is always in a conductive state. This is done by putting k and kn high.

An overall signal top metal diagram of the core cell, assuming I = 2 and m-4, ignoring the power rails VDD / VSS, is shown in FIG. The second metal and all further layers are shown. Referring to FIG. 10, the third metal layer is disposed above the second metal layer and below the fourth and fifth metal layers. The second metal is a word line metal (wl). The third metals are the bit line metals bl and bln and the comparison bit line metals k and kn. The fourth and fifth metals are match line metals. The number of horizontal signals in the top layer of metal will be the same as for i = 4 and m = 2, or i = 8 and m = 1.

The core cell can be modified in three different ways in terms of transistor level to always obtain a matching cell. That is, while occupying the same area as the actual core cell and using transistors of the same size, the result of the search is guaranteed to be in the conduction state of the chain device. These three modified core cells are useful for realizing dummy words (or models) or chains, which are shown in FIGS. 11, 12, and 13. The cell shown in FIG. 11 turns the chain device on continuously (the discharge path for the gate of the chain device does not exist). The cells shown in FIG. 12 (marked "conditional on") are matched when either k / kn or both are high. When both are low, the chain device is off. Two additional devices (not shown) may be included in the cell shown in FIG. 12 to provide model load on the word line. In Fig. 13, node cn is successively pulled up by diode-connected P-channel FET 731 and also pulled up to VDD whenever the word line wl is asserted (VDD connection is not necessary, May be replaced with a floating drain, depending on the choice that provides a more convenient layout form). As a result, node c remains low. The combination of cn high at the gate of the FET 741 and VDD applied to the source of the FET 741 connected to the FET 743 causes the FET 745 to be in continuous conduction as desired.

The dummy chain can be used for two purposes. The first object is to determine when a sufficient time for precharging the chain has been allocated. A chain that can be used for this purpose is shown in FIG. 14. This chain consists of a number of consecutive "always on" cells 810 as shown in FIG. 11, a "conditional on" cell 812 as shown in FIG. 12, and a precharge sense as shown in FIG. 15. Circuit 814. The precharge sense circuit includes an FET 821 and an inverter. The precharge signal is supplied to the gate of the FET 821 and the precharge execution signal is provided from the output of the inverter 823. A " conditional on " cell 812 is included to reflect the condition that precharge cannot be terminated until k / kn signals are asserted to their effective search voltage. In order to reflect the propagation delay through the chain as a result of the k / kn assertion, the entire dummy chain may be composed of "conditional on" cells (its implementation is omitted). The precharge sensing dummy chain is not required for all implementations as described below.

The second purpose of the dummy chain is to determine a time interval for successful evaluation of a match as a segment of a dummy word. The always matched word is used to generate a timing signal that can be used to clock the evaluation of all other match signals. This word may consist of a chain as shown in FIG. 14, "conditional on" cells, or cells shown in FIG. 13. Note that no precharge sense circuit is required. The generated timing signal can be further used as clocking the encoder or as part of a magnetic timing path for the entire CAM. The match evaluation timing dummy word can be used for all implementations.

Note that the CAM architecture incurs inherent search delays. All match lines start in the mismatch state and all have the same delay for the transition to the match state. Therefore, in modeling a match, it is guaranteed to model the slowest condition. In the prior art, in the case of a NOR match line, all match lines start in a match state and the transition rate to the mismatch state depends on the number of mismatch bits. An important timing condition of the validity of the match state on the match line should be obtained by observing the slowest mismatch.

There are various ways of realizing match line chains in terms of polarity selection, precharge and evaluation timing and control. The following description includes such various implementations, but the invention is not so limited. Those skilled in the art will be able to invent other similar techniques without difficulty.

16A and 16B show the signal timing of the pull down chain circuit and the precharge, respectively. Each of the chain circuits shown in FIGS. 16A and 17A is used with a precharge pulse that occurs after the start of the cycle. The precharge pulse is supplied to the gates of the FETs 831 and 833 connected to the chains. To avoid the charge-sharing problem that comes with precharge, the precharge should overlap the assertion of valid data on k / kn. A dummy chain for precharge sensing is required to determine when the precharge ends and to initialize the timing of the rest of the search operation. In the case of a match, there is a very resistive power supply GND (or VDD-VSS) path towards the end of the precharge operation through the entire chain.

If precharge is initiated at the end of the clock cycle (i.e., the stop state of the signals applied to the chain remains precharged), there is no need to sense the end of the precharge before initiating the rest of the seek operation. do. In this case, the precharge end indicates the minimum requirement for the cycle time of the CAM. This observation applies to all remaining chains described herein.

The chains shown in FIGS. 18A and 19B are identical to FIGS. 16A and 17A except for the precharge timing. Note that k / kn is currently stopped high, so it is possible to terminate precharging of all intermediate nodes in the chain. 18A shows a chain designed to realize pull down, and FIG. 19A shows a chain designed to realize pull up. 18B and 19B show the precharge timing of the chains shown in FIGS. 18A and 19A, respectively.

Since precharging from one end of the chain is too slow in some applications, the precharge device can be placed at both ends of the chain. This requires the addition of a third device that switches off the evaluation condensation to the opposite supply during precharge to avoid supply GND currents that may otherwise be significant. The timing is the same as in the case of the chains of Figs. 18A and 19A. 20A shows a chain designed to realize pull down, and FIG. 21A shows a chain designed to realize pull up. The chain shown in FIG. 20A has P and N-channel FETs 841 and 843 connected in series to the power supply GND (or VDD-VSS) path, and the junction of these FETs is connected to the end of the chain. Similarly, the chain shown in FIG. 21A has P and N-channel FETs 851 and 853 connected in series to a power supply GND (or VDD-VSS) path, the junctions of which are connected to the ends of the chain. Due to FET gating signal selection, Except during the transition, none of the VDD-VSS paths are conductive. 20B and 21B show the precharge timing of the chain shown in FIGS. 20A and 21A, respectively.

While precharging from one end of the chain is sufficiently fast, the circuits of FIGS. 18A and 19A may be undesirable due to the resistive power-GND current path in a stationary precharge state. The chain shown in Figures 22A and 23A solves this problem by including a transistor that stops the evaluation until the precharge ends. Fig. 22A shows a chain designed to realize pull down, and Fig. 23A shows a chain designed to realize pull up. The chain shown in FIG. 22A has an N-channel FET 861 connected between the end of the chain and ground. A P-channel FET 863 is connected between the end of the chain shown in FIG. 23A and the power supply VDD terminal. Precharge pulses are supplied to the gates of the FETs 861 and 863. 22B and 23B show the precharge timing of the chain shown in FIGS. 22A and 23A, respectively.

It would be desirable to limit the number of clocked devices in the chain while at the same time eliminating the possibility of a resistive power supply-GND short circuit during precharge. It is preferable to precharge only from one end, as in FIGS. 18A, 19A, 22A, and 23A, but it is also preferable to use a data control device that prevents short circuit current in place of the clock control device of FIGS. 22A and 23A. Therefore, a circuit is provided for driving a k / kn signal (referred to as a "k driver") so that the k driver corresponding to the column furthest from the precharge device is provided in the other columns of FIGS. In this case it has a stop low / low state, not high / high. The chain design is shown in FIGS. 24A and 25A, two different types of k signals conceptually shown as a single line through the chain device, labeled kL or kH. The core cell used is still the core cell of FIG. 9 and the k line on the chain device is simply conceptual. 24A shows a chain designed to realize pull down, and FIG. 25A shows a chain designed to realize pull up. 24B and 25B show the precharge timing of the chain shown in FIGS. 24A and 25A, respectively.

In all previous chain designs, the design goal is to entirely eliminate the possibility of charge sharing. If the chain length does not need to be variable and is instead fixed, some charge sharing can be allowed and can be intentionally designed into a chain. Precharge delay and power can be reduced slightly by leaving some uncharged chain nodes. This technique is shown in FIGS. 26A and 27A. The kL rows are moved toward the middle of the chain from the chain end opposite the precharge device. The left column of the kL column can be driven with either kL or kH. If there is no statistical possibility that all bits of the kH columns are matched and one or more other columns are mismatches, the charge (or lack of charge) on the uncharged nodes should not be evaluated as a match of the voltage at the inverter gate. Move to the median. If this situation is understood and considered, it should be acceptable. FIG. 26A shows a chain designed to realize pull down, and FIG. 27A shows a chain designed to realize pull up. 26B and 27B show the precharge timing of the chain shown in FIGS. 26A and 27A, respectively.

In all the designs shown, the match sense circuit is shown as a simple inverter. In practice, such a circuit can be realized with any static or dynamic voltage sense device.

Because some target applications tend to have high commonality between matches and mismatches (ie, they can only differ a few bits, and contiguous long strings can be common), this "near-miss" Excessive power consumption may occur in the precharge. This is especially true when word segments (full chains) are matched in matched words. Note that this situation does not traditionally correspond to the wired-NOR match line CAM.

One example of this situation (but not to limit the application) is an ATM address lookup. The address consists of two fields: the virtual channel identifier (VCI) and the virtual path identifier (VPI). The multiple entries may be (a) having the same VPIs and different bits of the VCI, or (b) having the same VCIs and different bits of the VPI. In this case, to limit the power consumption, it is advantageous to scramble the order of the bits in the chain.

In most storage devices, the columns are organized in the form of bit slices so that all the columns associated with a given data bit are grouped together. The architecture described herein is a word slice instead of a bit slice as shown in FIG. This requires a common data bus 910 that connects all the words (ie, connects all the columns associated with each of the bits). The details of these buses are as follows.

The bus 910 can be used for search, read, or write operations and supply bidirectional data.

All drivers on the bus 910 should be tri-statable.

While specific embodiments of the invention have been described in detail, it will be appreciated that various changes, modifications, and adaptations may be made without departing from the scope of the invention as defined by the appended claims.

The present invention realizes the two-dimensional decoding necessary to achieve a suitable array aspect ratio for large memory, and simultaneously consumes low power while simultaneously searching the entire contents of the large capacity CAM.

1 shows a prior art CAM.

2 illustrates a CAM according to an embodiment of the invention.

3 shows the logic equivalent of NOR and NOT-AND gates.

4 illustrates a logical segment of NOT-AND gates.

5A shows a match line circuit consisting of two segments.

FIG. 5B conceptually illustrates the two segment circuit shown in FIG. 5A. FIG.

6A illustrates storage of the match line.

6b shows four words sharing an encoder.

7A shows a physical single word with two encoders.

FIG. 7B illustrates an array with a plurality of rows shown in FIG. 7A.

8A shows a plurality of words in each of four segments.

8B shows a plurality of words in each of the eight segments.

9 is a transistor level schematic of a memory core cell.

10 is a view of the memory core cell upper metal layers.

11 shows a first example of an aqueous core cell.

12 shows a second example of an aqueous core cell.

FIG. 13 shows a third example of an aqueous core cell; FIG.

14 illustrates a dummy chain used to detect completion of precharge.

Fig. 15 shows a simple realization of a precharge sense circuit.

16A illustrates a pull down chain circuit of in-cycle precharge.

Fig. 16B is a diagram showing signal timing of precharge.

FIG. 17A shows a pull-up chain circuit of in cycle precharge; FIG.

17B is a diagram showing signal timing of precharge.

Fig. 18A shows a pull down chain circuit of a stopped precharge.

18B shows signal timing of precharge.

Fig. 19A shows a pull-up chain circuit of a stopped precharge.

19B is a diagram showing signal timing of precharge.

20A shows a pull down chain circuit of a stopped precharge from both ends of the chain;

20B is a diagram showing signal timing of precharge.

Fig. 21A shows the pull-up chain circuit of the stopped precharge from both ends of the chain.

21B is a diagram showing signal timing of precharge.

FIG. 22A illustrates a pull down chain circuit with a stop precharge and a single clock control quiescent-off device. FIG.

Fig. 22B is a diagram showing signal timing of precharge.

FIG. 23A illustrates a pull up chain circuit with a stop precharge and a single clock control quiescent-off device. FIG.

Fig. 23B is a diagram showing signal timing of precharge.

24A shows a pull down chain circuit with a stop precharge and a single data control stop device.

Fig. 24B is a diagram showing signal timing of precharge.

25A shows a pull up chain circuit with a stop precharge and a single data control stop device.

Fig. 25B is a diagram showing signal timing of precharge.

FIG. 26A illustrates a pull down chain circuit with stop precharge and intentional charge sharing. FIG.

Fig. 26B is a diagram showing signal timing of precharge.

FIG. 27A illustrates a pull up chain circuit with stop precharge and intentional charge sharing. FIG.

27B is a diagram showing signal timing of precharge.

FIG. 28 illustrates an architecture in which columns are formed in the form of word slices.

<Explanation of symbols for the main parts of the drawings>

212: match line

214: bit line

218: inverter

220: AND gate

222 encoder

224: word match line

Claims (27)

means for matching w words, each word comprising i segment match line chains, each said match line chain comprising b / i core cells concatenated in series by a match line, each said core cell being Means for storing data, the order of the bits in the chain segments and the order between the chain segments constituting each word being matched means of w words deterministically scrambled -w, i, And b is an integer; Logic means for logically combining the match line chains in each row; And Encoding means for providing a search result based on an output from said logic means Content addressing memory device (CAM) comprising a. The content addressing memory device of claim 1, wherein the logic means comprises NAND circuit means for providing logic outputs in response to outputs from the match line chains in each row. The content addressing memory device of claim 1, further comprising means for sensing a transition of data signals on the chains. 4. The content addressing memory device of claim 3, wherein the polarity of the data signal swinging to indicate a match is up or down. The method of claim 1, wherein i = 2 and a pair of match line chains are directed in a mirror image such that their outputs face each other and, by logic means, a logical combination of two partial match results from two chains is obtained. Content bungee storage that becomes easy. 6. The word match lines of claim 5, wherein the logic means comprises an AND logic means, and wherein the word match lines resulted by ANDing the partial match results on the match line chains and assigned one word match line per word. And a content addressed memory device routed to said encoding means. 7. The content addressing memory device of claim 6, wherein the word match lines are selectively routed physically over the core cells in a metal layer over all other signals used in the core cell. 7. The content addressing memory device according to claim 6, wherein the encoding means comprises a plurality of encoders. 7. The method of claim 6, wherein a plurality of words are arranged adjacent to the encoding means, and a plurality of word match lines extend over each of the core cells to define a per low path of the plurality of word match lines. Content bungee storage. 10. The content addressing memory device of claim 9, wherein the word match lines are selectively routed over the core cell in a metal layer over all other signals used in the core cell. 7. The content addressing memory device of claim 6, wherein the partial match results are optionally routed over the core cell and combined within the AND logic means. 12. The result of claim 11, wherein the results from the match line segment pairs are first combined into a second partial result by a logical AND operation, which is then routed over the core cell, such that at the last AND gate adjacent to the encoder. Content bungee storage combined. The matched line of claim 1, wherein the core cell includes a plurality of field effect transistors (FETs) for data storage operations, and supplies a first binary logic level to one end of the chain segment and the match line in response to a clock signal. And a logic level / precharging means for precharging the chain segment to a second binary logic level. 14. The content addressing memory device of claim 13, wherein the logic level / precharging means comprises means for directly coupling one end of the chain to a power source of the first binary logic level. 14. The content addressing memory device of claim 13, wherein the logic level / precharging means comprises a first FET at the other end of the chain closest to the match sense circuit. 16. The apparatus of claim 15, wherein the logic level / precharging means further comprises means for precharging the chain to the second binary logic level by the first FET, the means for pre-charging the clock cycle during a search. Content addressing memory that begins following startup. 16. The apparatus of claim 15, wherein the logic level / precharging means further comprises means for precharging the chain to the second binary logic level by the first FET, beginning following the end of a search operation and The content addressing memory device which continues during the non-search stop state of the CAM and terminates prior to the start of the next seek operation, wherein the FETs of the chain remain in the conduction state during precharging due to the high logic level on their gates. 14. The content addressing memory device of claim 13, wherein the logic level / precharging means comprises a first FET at one end of the chain and a second FET at the other end of the chain furthest from the match sense circuit. . 19. The power supply of claim 18 wherein the logic level / precharging means is coupled to one end of the chain by a third FET that is in a conductive state when the first and second FETs are in a non-conductive state. And means for connecting to the FETs in the chain, wherein the FETs in the chain remain conductive during precharge due to the high logic level on their gates. 19. The content addressing memory device according to claim 18, wherein the second FET is in a conductive state when the first FET is in a non-conductive state. The method of claim 13, Said logic level / precharging means comprising logic level means and precharging means, The precharging means includes means for precharging the chain segment to the second binary logic level by a first FET at the end of the chain segment closest to the match sense circuit, following termination of the search operation. Begins and continues during the non-search-stop state of the CAM and ends before the start of the next search operation, The logic level means is for directly coupling one end of the chain segment with a power source of the first binary logic level, The core cell in the chain of one final end of the match sense circuit includes the same FETs as the FETs of the other core cells in the chain segment, and comparison data is applied to the opposite polarity during the stop precharge state so that only the FET of the chain segment And a FET in the chain which is in a non-conducting state from the stop precharge state. The method of claim 13, Said logic level / precharging means comprising logic level means and precharging means, The precharging means is for precharging the chain to the second binary logic level by the first FET at the end of the chain closest to the match sense circuit, beginning following the end of the search operation and starting the CAM. Continues during the nonbrowsing stop of, and ends before the start of the next seek action, Said logic level means is for directly coupling said chain with a power source of said first binary logic level, The core cell at the predetermined constant position in the chain includes the same FETs as the FETs of the other core cells in the chain, and comparison data is applied at opposite polarities during the stop precharge state so that only the FETs in the chain are in the stop precharge state By becoming a FET in a chain that is nonconductive at, any charge sharing that occurs during the search of the chain causes the mismatch to appear somewhat like a match, but content bunkering occurs where understanding and consideration of charge sharing occurs. store. The method of claim 13, wherein the core cell, First and second N-channel FETs and first and second P-channel FETs forming two cross coupled inverters for storing differential data; Third and fourth N-channel FETs gated by word lines to provide access for data read and write operations and coupled with differential data nodes to differential bit lines; A fifth N-channel FET; And Sixth and seventh N-channel FETs, one of which is gated by a positive storage node and connects a positive compare bit line to the gate of the fifth N-channel FET, and the other is gated by a negative storage node and negative compare A bit line is connected to the gate of the fifth N-channel FET, and the comparison bit lines are physically distinct from the bit lines used for read and write access, and the source and drain of the fifth N-channel FET are such FETs. Sixth and seventh N-channel FETs connected to the FETs of adjacent cells to form a chain of holes Content bungee storage device including a. 10. The method of claim 1, further comprising a dummy chain for determining when precharge of all chains ends, wherein the dummy chain includes as many dummy cells as the core cells of an actual storage chain and is matched with a matched actual storage chain. And means for detecting when the precharge ends in the precharge circuit at the opposite end and is always in conducting to model a match in response to comparing the bit line transitions in the same manner. The method of claim 1, further comprising a dummy word for determining a time point when sufficient time has elapsed for the match to end, The word is divided into the same chain number as the actual stored word, Each chain has the same number of cells as the actual storage chain, but consists of dummy core cells instead of the actual core cells, Each chain is always on to model a match, and content addressing memory responsive to comparing bit line transitions in the same manner as the actual chain matched. 2. The system of claim 1, further comprising a common data bus that connects peripheral circuitry to the words of the CAM, wherein the bus joins all words and is used for search, read, or write operations. Supply and all of the drivers on the bus are tri-statable. First and second N-channel FETs and first and second P-channel FETs forming two cross coupled inverters for storing differential data; Third and fourth N-channel FETs gated by word lines to provide access for data read and write operations and coupled with the differential data node to differential bit lines; A fifth N-channel FET; And Sixth and seventh N-channel FETs, one of which is gated by a positive storage node and connects a positive compare bit line to the gate of the fifth N-channel FET, and the other is gated by a negative storage node and negative compare A bit line is connected to the gate of the fifth N-channel FET, and the comparison bit line is physically distinct from the bit lines used for read and write access, and the source and drain of the fifth N-channel FET are such FETs. Sixth and seventh N-channel FETs connected to the FETs of adjacent cells to form a chain of holes Core cell comprising a.