KR100561517B1 - Method For Manufacturing Semiconductor Device - Google Patents

Method For Manufacturing Semiconductor Device Download PDF

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KR100561517B1
KR100561517B1 KR1020030101654A KR20030101654A KR100561517B1 KR 100561517 B1 KR100561517 B1 KR 100561517B1 KR 1020030101654 A KR1020030101654 A KR 1020030101654A KR 20030101654 A KR20030101654 A KR 20030101654A KR 100561517 B1 KR100561517 B1 KR 100561517B1
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metal wiring
film
semiconductor device
metal
semiconductor substrate
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KR1020030101654A
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Korean (ko)
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KR20050069512A (en
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이완기
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

Abstract

본 발명은 반도체 소자의 제조 방법을 개시한다. 이에 의하면, 반도체 기판 상에 알루미늄층의 금속 배선을 형성하고, 상기 금속 배선을 세정액에 의해 세정하고, 상기 금속 배선을 포함하여 상기 반도체 기판 상에 SiON막과 같은 보호막을 적층하고, 상기 SiON막 상에 층간 절연막을 적층한다.The present invention discloses a method for manufacturing a semiconductor device. According to this, the metal wiring of an aluminum layer is formed on a semiconductor substrate, the said metal wiring is wash | cleaned with a washing | cleaning liquid, the protective film like a SiON film is laminated | stacked on the said semiconductor substrate including the said metal wiring, An interlayer insulating film is laminated on the substrate.

따라서, 본 발명은 상기 금속 배선을 SiON막으로 보호함으로써 상기 금속 배선의 부식이나 스트레스를 억제시킬 수가 있으므로 상기 금속 배선을 열처리시키더라도 상기 금속 배선의 패턴을 형성하기 위한 건식 식각공정에서 발생한 플라즈마 식각 손상과 스트레스를 최소화시킴과 상기 금속 배선 내에 보이드가 발생하는 것을 방지할 수 있다.Therefore, the present invention can suppress the corrosion and stress of the metal wiring by protecting the metal wiring with a SiON film, so that plasma etching damage generated in the dry etching process for forming the pattern of the metal wiring even when the metal wiring is heat treated. It is possible to minimize overstress and to prevent voids from occurring in the metal lines.

따라서, 상기 금속 배선의 신뢰성을 향상시키고 나아가 반도체 소자의 신뢰성을 향상시킬 수가 있다.Therefore, the reliability of the said metal wiring can be improved, and also the reliability of a semiconductor element can be improved.

알루미늄층, 금속 배선, SiON막, 부식, 보이드Aluminum layer, metal wiring, SiON film, corrosion, void

Description

반도체 소자의 제조 방법{Method For Manufacturing Semiconductor Device} Method for manufacturing semiconductor device {Method For Manufacturing Semiconductor Device}             

도 1은 종래 기술에 의한 반도체 소자를 나타낸 단면 구조도.1 is a cross-sectional structural view showing a semiconductor device according to the prior art.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 단면 공정도.2A to 2C are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더욱 상세하게는 금속 배선 내에 보이드(void)가 발생하는 것을 방지함으로써 금속 배선의 신뢰성을 향상시키도록 한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing the generation of voids in a metal wiring to improve the reliability of the metal wiring.

일반적으로, 반도체 소자의 금속 배선은 알루미늄(Al)과 같은 재질로 형성된다. 상기 금속 배선은 순수 알루미늄 재질로 형성되거나, 상기 금속 배선의 전기적 이동(Electromigration) 및 스파이킹(Spiking)을 억제하기 위해 상기 순수 알루미늄에 구리(Cu) 또는 실리콘(Si)을 첨가시킨 알루미늄 합금 재질로 형성될 수 있다.In general, the metal wiring of the semiconductor device is formed of a material such as aluminum (Al). The metal wire may be formed of pure aluminum, or may be made of aluminum alloy in which copper (Cu) or silicon (Si) is added to the pure aluminum in order to suppress electromigration and spiking of the metal wire. Can be formed.

종래의 반도체 소자는 도 1에 도시된 바와 같이, 반도체 기판(10) 상에 금속 배선(11)이 형성되고, 상기 금속 배선(11)을 포함하여 상기 반도체 기판(10)의 전역 상에 층간 절연막(13)이 적층된다.In the conventional semiconductor device, as shown in FIG. 1, the metal wiring 11 is formed on the semiconductor substrate 10, and the interlayer insulating film is formed on the entire region of the semiconductor substrate 10 including the metal wiring 11. (13) is laminated.

그런데, 종래에는 상기 금속 배선(11)의 패턴을 형성하기 위한 건식 식각공정을 진행한 후 상기 반도체 기판(10)을 세정액, 예를 들어 솔벤트(solvent)를 이용한 세정액에 의해 세정한다. 그리고 나서, 상기 층간 절연막(13)의 적층 전 또는 상기 층간 절연막(13)의 적층 후에 상기 금속 배선(11)을 열처리(sintering) 공정에 의해 처리하여 준다. 이는 상기 금속 배선(11)의 형성을 위한 건식 식각공정을 진행할 때, 상기 금속 배선(11)에 발생한 플라즈마 식각 손상이나 스트레스, 예를 들어 일렉트로마이그레이션 스트레스 (electrimigration stress) 등을 완화시키기 위함이다.However, conventionally, after performing a dry etching process for forming a pattern of the metal wiring 11, the semiconductor substrate 10 is cleaned with a cleaning liquid, for example, a cleaning liquid using a solvent. Then, the metal wiring 11 is treated by a sintering process before laminating the interlayer insulating film 13 or after laminating the interlayer insulating film 13. This is to alleviate plasma etching damage or stress, for example, electromigration stress, generated in the metal wire 11 when the dry etching process for forming the metal wire 11 is performed.

그러나, 종래에는 상기 금속 배선(11)의 형성 후에 상기 반도체 기판(10)을 상기 세정액에 의해 세정하므로 상기 금속 배선(11)의 부식, 예를 들어 갈바닉(Galvanic) 부식이 발생할 수 있다. 또한, 상기 금속 배선(11)에 플라즈마 식각 손상과 스트레스가 존재한다.However, conventionally, since the semiconductor substrate 10 is cleaned by the cleaning liquid after the formation of the metal wiring 11, corrosion of the metal wiring 11, for example, galvanic corrosion, may occur. In addition, plasma etching damage and stress exist in the metal line 11.

이러한 상태에서 상기 층간 절연막(13)의 열처리공정을 진행하고 나면, 상기 금속 배선(11) 내에 빈공간, 즉 보이드(void)가 발생하므로 상기 금속 배선(11)의 신뢰성이 저하되고 나아가 반도체 소자의 신뢰성이 저하된다.In this state, after the heat treatment process of the interlayer insulating layer 13 is performed, an empty space, ie, void, is generated in the metal wiring 11, so that the reliability of the metal wiring 11 is lowered. The reliability is lowered.

또한, 상기 열처리공정의 공정조건에 대한 여유도(margin)를 높이는데 한계가 있다.In addition, there is a limit to increase the margin (margin) for the process conditions of the heat treatment process.

따라서, 본 발명의 목적은 금속 배선의 플라즈마 식각 손상을 완화함으로써 상기 금속 배선 내에 보이드가 발생하는 것을 방지하는데 있다.Accordingly, an object of the present invention is to prevent the occurrence of voids in the metal wiring by alleviating the plasma etching damage of the metal wiring.

본 발명의 다른 목적은 금속 배선의 열적 스트레스를 완화시킴으로써 상기 금속 배선 내에 보이드가 발생하는 것을 방지하는데 있다.Another object of the present invention is to prevent the generation of voids in the metal wiring by relieving thermal stress of the metal wiring.

본 발명의 또 다른 목적은 금속 배선의 신뢰성을 향상시키고 나아가 반도체 소자의 신뢰성을 향상시키는데 있다.
Another object of the present invention is to improve the reliability of the metal wiring and further improve the reliability of the semiconductor device.

이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조 방법은The semiconductor device manufacturing method according to the present invention for achieving the above object is

반도체 기판 상에 알루미늄층의 금속 배선을 형성하는 단계; 상기 금속 배선을 세정액에 의해 세정하는 단계; 상기 금속 배선 내에 보이드가 발생하는 것을 방지하기 위해 상기 금속 배선을 포함하여 상기 반도체 기판의 전역 상에 SiON막의 보호막을 형성하는 단계; 상기 보호막 상에 층간 절연막을 적층하는 단계; 및 상기 금속 배선을 열처리시키는 단계를 포함하는 것을 특징으로 한다.Forming a metal wiring of an aluminum layer on the semiconductor substrate; Cleaning the metal wires with a cleaning liquid; Forming a protective film of a SiON film on the entire region of the semiconductor substrate including the metal wiring to prevent voids from occurring in the metal wiring; Stacking an interlayer insulating film on the protective film; And heat-treating the metal wires.

바람직하게는, 상기 SiON막을 200~800Å의 두께로 적층할 수 있다. 또한, 상기 SiON막을 플라즈마 강화 화학 기상 증착 공정에 의해 적층할 수 있다.Preferably, the SiON film can be laminated to a thickness of 200 to 800 kPa. In addition, the SiON film can be laminated by a plasma enhanced chemical vapor deposition process.

따라서, 본 발명은 상기 금속 배선 내에 보이드가 발생하는 것을 방지할 수 있으므로 상기 금속 배선의 신뢰성을 향상시킬 수가 있다.Therefore, the present invention can prevent the occurrence of voids in the metal wiring, so that the reliability of the metal wiring can be improved.

이하, 본 발명에 의한 반도체 소자의 제조 방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다. 종래의 부분과 동일한 구성 및 동일한 작용을 갖는 부분에는 동일 부호를 부여한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part which has the same structure and the same action as the conventional part.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 단면 공정도이다.2A to 2C are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.

도 2a를 참조하면, 먼저, 예를 들어 스퍼터링공정 등을 이용하여 반도체 기판(10) 상에 알루미늄층과 같은 도전층을 5000~6000Å의 두께로 적층한다. 이때, 상기 알루미늄층은 순수 알루미늄, 또는 소량의 구리를 포함한 합금, 즉 알루미늄-구리의 합금 또는 알루미늄-구리-실리콘의 합금으로 형성될 수 있다.Referring to FIG. 2A, first, a conductive layer such as an aluminum layer is laminated on the semiconductor substrate 10 to a thickness of 5000 to 6000 kV, for example, using a sputtering process or the like. In this case, the aluminum layer may be formed of pure aluminum, or an alloy containing a small amount of copper, that is, an alloy of aluminum-copper or an alloy of aluminum-copper-silicon.

이어서, 상기 알루미늄층의 금속 배선 형성 영역 상에 감광막(미도시)의 패턴을 형성하고, 상기 감광막의 패턴을 식각 마스크층으로 이용하여 상기 알루미늄층을 건식 식각공정, 예를 들어 반응성 이온 식각 공정에 의해 제거시킴으로써 상기 알루미늄층으로 이루어진 금속 배선(21)을 형성한다. 이때, 상기 금속 배선(21)에는 상기 건식 식각공정에 의한 플라즈마 식각 손상이나 스트레스가 많이 발생한다.Subsequently, a pattern of a photoresist film (not shown) is formed on the metal wiring formation region of the aluminum layer, and the aluminum layer is subjected to a dry etching process, for example, a reactive ion etching process, using the pattern of the photoresist film as an etching mask layer. The metal wiring 21 made of the aluminum layer is formed by removing the same. In this case, plasma etching damage or stress caused by the dry etching process are generated in the metal lines 21.

그런 다음, 상기 감광막의 패턴을 제거한 후 상기 반도체 기판(10)과 금속 배선(21) 상에 잔존하는 폴리머 등과 같은 감광막 잔존물 등을 제거하기 위해 상기 반도체 기판(10)을 솔벤트와 같은 세정액 등에 의해 세정한다. Then, after removing the pattern of the photoresist film, the semiconductor substrate 10 is cleaned with a cleaning solution such as a solvent to remove photoresist residue such as polymer remaining on the semiconductor substrate 10 and the metal wiring 21. do.

한편, 도면에 도시하지 않았으나 상기 반도체 기판(10)에는 반도체 소자를 위한 요소, 예를 들어 소자 분리막, 게이트 절연막, 게이트 전극, 소스/드레인 영 역, 커패시터, 하층 금속 배선 등이 형성될 수 있으며, 상기 반도체 기판(10)의 최상부에 층간 절연막이 형성될 수 있다.Although not shown in the drawings, elements for semiconductor devices, for example, device isolation layers, gate insulating layers, gate electrodes, source / drain regions, capacitors, and lower metal wirings, may be formed in the semiconductor substrate 10. An interlayer insulating layer may be formed on the top of the semiconductor substrate 10.

도 2b를 참조하면, 이후, 상기 금속 배선(21)을 포함한 반도체 기판(10)의 전역 상에 플라즈마 강화 화학 기상 증착 공정(plasma enhanced chemical vapor deposition: PECVD) 공정 등에 의해 보호막, 예를 들어 무기질 반사방지막과 같은 SiON막(23)을 사용할 수 있다. Referring to FIG. 2B, a protective film, for example, an inorganic reflection, may be formed on the entire surface of the semiconductor substrate 10 including the metal wiring 21 by a plasma enhanced chemical vapor deposition (PECVD) process or the like. A SiON film 23 such as a prevention film can be used.

여기서, 상기 SiON막(23)은 상기 금속 배선(21)의 보호막으로서의 역할을 하기 위한 두께, 예를 들어 200~800Å의 얇은 두께로 적층하는 것이 바람직한데, 이는 상기 SiON막(23)의 적층 공정 시간을 최소화시키기 위함이다.Here, the SiON film 23 is preferably laminated to a thickness, for example, a thin thickness of 200 to 800 kPa, to serve as a protective film of the metal wiring 21, which is the lamination process of the SiON film 23 This is to minimize the time.

또한, 상기 SiON막(23)이 수분 방지막의 역할을 하므로 후속 공정에서의 수분이 상기 금속 배선(21) 내에 침투하는 것을 방지하므로 상기 금속 배선(21)의 부식, 예를 들어 갈바닉 부식을 억제할 수가 있다.In addition, since the SiON film 23 serves as a moisture barrier, moisture in a subsequent process may be prevented from penetrating into the metal interconnect 21, thereby preventing corrosion of the metal interconnect 21, for example, galvanic corrosion. There is a number.

도 2c를 참조하면, 그런 다음, 상기 금속 배선(21) 사이의 오목부를 매립함과 표면 평탄화를 위해 상기 SiON막(23) 상에 층간 절연막(25)을 적층한다. 여기서, 설명의 편의상, 상기 층간 절연막(25)을 1개 층으로 구성한 것처럼 도시하였지만, 실제로는 상기 층간 절연막(25)을 1개보다 많은 복수층으로 구성하는 것도 가능하다.Referring to FIG. 2C, an interlayer insulating film 25 is then deposited on the SiON film 23 for filling the recesses between the metal lines 21 and for planarization of the surface. Here, for the sake of convenience, the interlayer insulating film 25 is shown as being composed of one layer, but in practice, the interlayer insulating film 25 may be formed of more than one layer.

이후, 열처리공정을 이용하여 상기 금속 배선(21)을 열처리함으로써 상기 금속 배선(21)의 형성을 위한 건식 식각공정을 진행할 때 상기 금속 배선(21)에 발생한 플라즈마 식각 손상이나 스트레스를 최소화시킬 수가 있다. 이때, 상기 열처리 공정은 통상적으로 400℃의 온도와, 질소(N2) 가스의 분위기에서 30분 동안 진행한다.Thereafter, the metal wire 21 may be heat-treated using a heat treatment process to minimize plasma etching damage or stress generated in the metal wire 21 when the dry etching process for forming the metal wire 21 is performed. . In this case, the heat treatment process is typically carried out for 30 minutes in a temperature of 400 ℃, nitrogen (N2) gas.

따라서, 본 발명은 상기 금속 배선(21)의 부식을 방지하고 상기 금속 배선(21)의 플라즈마 식각 손상이나 스트레스를 억제한 상태에서 상기 열처리공정을 진행함으로써 상기 층간 절연막(25)에 보이드가 발생하는 것을 방지할 수 있으므로 상기 금속 배선(21)의 신뢰성을 향상시키고 나아가 반도체 소자의 신뢰성을 향상시킬 수가 있다.Accordingly, in the present invention, the voids are generated in the interlayer insulating layer 25 by performing the heat treatment process in a state of preventing corrosion of the metal wiring 21 and suppressing plasma etching damage or stress of the metal wiring 21. Since it can prevent that, the reliability of the said metal wiring 21 can be improved, and also the reliability of a semiconductor element can be improved.

또한, 상기 열처리공정에 대한 공정 여유도(margin)를 높여줄 수가 있으므로 상기 열처리공정을 용이하게 진행할 수가 있다.In addition, since the process margin for the heat treatment process can be increased, the heat treatment process can be easily performed.

한편, 상기 열처리공정을 상기 층간 절연막(25)의 적층 후에 진행하거나 상기 층간 절연막(25)의 적층 전에 진행하는 것도 가능하다.In addition, the heat treatment process may be performed after the lamination of the interlayer insulating film 25 or before lamination of the interlayer insulating film 25.

이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자의 제조 방법은 반도체 기판 상에 알루미늄층의 금속 배선을 형성하고, 상기 금속 배선을 세정액에 의해 세정하고, 상기 금속 배선을 포함하여 상기 반도체 기판 상에 SiON막과 같은 보호막을 적층하고, 상기 SiON막 상에 층간 절연막을 적층한다.As described above, in the method for manufacturing a semiconductor device according to the present invention, a metal wiring of an aluminum layer is formed on a semiconductor substrate, the metal wiring is washed with a cleaning liquid, and the metal wiring is formed on the semiconductor substrate. A protective film such as a SiON film is laminated, and an interlayer insulating film is laminated on the SiON film.

따라서, 본 발명은 상기 금속 배선을 SiON막으로 보호함으로써 상기 금속 배선의 부식이나 스트레스를 억제시킬 수가 있으므로 상기 금속 배선을 열처리시키더라도 상기 금속 배선의 패턴을 형성하기 위한 건식 식각공정에서 발생한 플라즈마 식각 손상과 스트레스를 최소화시킴과 상기 금속 배선 내에 보이드가 발생하는 것을 방지할 수 있다.Therefore, the present invention can suppress the corrosion and stress of the metal wiring by protecting the metal wiring with a SiON film, so that plasma etching damage generated in the dry etching process for forming the pattern of the metal wiring even when the metal wiring is heat treated. It is possible to minimize overstress and to prevent voids from occurring in the metal lines.

따라서, 상기 금속 배선의 신뢰성을 향상시키고 나아가 반도체 소자의 신뢰성을 향상시킬 수가 있다.Therefore, the reliability of the said metal wiring can be improved, and also the reliability of a semiconductor element can be improved.

한편, 본 발명은 도시된 도면과 상세한 설명에 기술된 내용에 한정하지 않으며 본 발명의 사상을 벗어나지 않는 범위 내에서 다양한 형태의 변형도 가능함은 이 분야에 통상의 지식을 가진 자에게는 자명한 사실이다.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (3)

반도체 기판 상에 알루미늄층의 금속 배선을 형성하는 단계;Forming a metal wiring of an aluminum layer on the semiconductor substrate; 상기 금속 배선을 세정액에 의해 세정하는 단계;Cleaning the metal wires with a cleaning liquid; 상기 금속 배선 내에 보이드가 발생하는 것을 방지하기 위해 상기 금속 배선을 포함하여 상기 반도체 기판의 전역 상에 SiON막의 보호막을 형성하는 단계;Forming a protective film of a SiON film on the entire region of the semiconductor substrate including the metal wiring to prevent voids from occurring in the metal wiring; 상기 보호막 상에 층간 절연막을 적층하는 단계; 및Stacking an interlayer insulating film on the protective film; And 상기 금속 배선을 열처리시키는 단계를 포함하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device comprising the step of heat-treating the metal wiring. 제 1 항에 있어서, 상기 SiON막을 200~700Å의 두께로 적층하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the SiON film is laminated to a thickness of 200 to 700 GPa. 제 1 항 또는 제 2 항에 있어서, 상기 SiON막을 플라즈마 강화 화학 기상 증착 공정에 의해 적층하는 것을 특징으로 하는 반도체 소자의 제조 방법.The semiconductor device manufacturing method according to claim 1 or 2, wherein the SiON film is laminated by a plasma enhanced chemical vapor deposition process.
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