KR100560301B1 - Driving circuit for non volitile dram using nonconductor to trap electron and its method - Google Patents

Abstract

An object of the present invention is to provide a driving circuit and method for facilitating control of a nonvolatile DRAM using a trappable insulator.

The nonvolatile DRAM driving circuit using the trappable insulator according to the first invention of the present application generates a plurality of internal voltages by receiving an external power source when driving a cell transistor arrayed in the nonvolatile DRAM using the trappable insulator. Internal power generating means for; Mode control means for generating a mode control signal to control the nonvolatile DRAM for each mode; Voltage level selection means for switching a plurality of voltages required by the core of the nonvolatile DRAM according to the mode from the internal power generation means; And row decoding means for applying a voltage output from the voltage level selecting means to a core of the nonvolatile DRAM.

Nonvolatile DRAM, Insulator, Nitride, Trap, Hole Injection

Description

DRIVING CIRCUIT FOR NON VOLITILE DRAM USING NONCONDUCTOR TO TRAP ELECTRON AND ITS METHOD}             

1 is a cross-sectional view of the NVDRAM according to the prior art,

2A is a cross-sectional view of an NVDRAM in accordance with an embodiment of the present invention;

2B is a circuit diagram of an NVDRAM according to an embodiment of the present invention;

3 is an overall block diagram of an NVDRAM according to the present invention;

4 is an essential part configuration diagram for applying a voltage to the NVDRAM core of the present invention;

5 is an explanatory diagram for applying a word line voltage of the present invention;

6 is an explanatory diagram for each mode of a cell transistor in an NVDRAM of the present invention;

FIG. 7 is a waveform diagram illustrating a change in a threshold voltage over time of a cell transistor in an NVDRAM of the present invention. FIG.

Description of the main parts of the drawing

310: internal power generation unit 320: mode control unit

330: voltage level selection unit 340: low decoding unit

350: DRAM core 360: column decoding unit

370: sense amplifier 380: temporary memory block

311: bit line precharge voltage generator 313: cell plate voltage generator

315: positive voltage generator 317: negative voltage generator

The present invention relates to a nonvolatile DRAM driving circuit and method using an insulator such as a nitride film capable of trapping electrons.

Semiconductor memories that are widely used to date can be roughly classified into random access memory (RAM) such as DRAM and SRAM, and read only memory (ROM) such as mask ROM, EPROM, and EEPROM. The DRAM and the SRAM can write and read at high speed, but when the power supply to the memory is cut off, the contents stored in the memory are lost. On the other hand, the mask ROM, EPROM and EEPROM can retain the stored contents even after the power supply to the memory is cut off, but there is one piece per stage which takes a long time even if the stored contents cannot be changed or changed.

For this reason, non-volatile dynamic random access memory (NVDRAM) has been proposed, which allows data to be written to or read from the memory at high speed and that stores the stored contents even when the power is cut off.

As an example, US Pat. No. 4,471,471 discloses a nonvolatile DRAM which requires a dual electron injector structure (DEIS) between the floating gate and the transfer gate. However, the DEIS stack structure disclosed in the above patent is located on the bit line side of the cell so that data cannot be transferred from the DRAM to the floating gate in parallel to all cells. In order to solve this problem, "NON VOLATILE DRAM CELL" of US Pat. No. 5,331,188 uses a floating gate formed of the first layer 18 and the second layer 20 to form the first layer 18 close to the p + region. Concentrated on a thin insulating film. However, as shown in FIG. 1, US Pat. No. 5,331,188 forms an electric field with only the word line voltage and the bit line voltage while the plate line voltage of the cell capacitor is fixed to the ground voltage. Therefore, since the floating gate is formed of two layers, the area of the cell is increased, and the manufacturing process is complicated. In addition, relatively high word line and bit line voltages are applied compared to nonvolatile DRAMs that can adjust the plate line voltage, thereby increasing power consumption in the NVDRAM.

Accordingly, the present applicant has applied for a nonvolatile DRAM driving circuit and a driving method thereof capable of driving with a low internal voltage by applying different voltages to the plate with the patent application No. 10-2003-58300 of August 22, 2003. However, since the present invention is suitable for the floating gate type NVDRAM, electrons can be injected from the source side into the floating gate of the conductor indefinitely so that the SRC process (Stress-Refresh-Check Process) is performed a number of times during the cell threshold voltage normalization mode. There was a problem that the control operation is complicated because it must be repeated. In addition, there is a problem in that the control operation becomes complicated because the threshold voltage Vth continuously increases as long as electrons are injected into the floating gate.

In order to solve the above problems, an object of the present invention is to provide a driving circuit and a method for facilitating the control of a nonvolatile DRAM using a trappable insulator.

The nonvolatile DRAM driving circuit using the trappable insulator according to the first invention of the present application generates a plurality of internal voltages by receiving an external power source when driving a cell transistor arrayed in the nonvolatile DRAM using the trappable insulator. Internal power generating means for; Mode control means for generating a mode control signal to control the nonvolatile DRAM for each mode; Voltage level selection means for switching a plurality of voltages required by the core of the nonvolatile DRAM according to the mode from the internal power generation means; And row decoding means for applying a voltage output from the voltage level selecting means to a core of the nonvolatile DRAM.

Preferably, the internal power generation means, the bit line precharge voltage generator for generating a plurality of voltages required in the bit line; A cell plate voltage generator for generating a plurality of voltages required by the cell plate; A positive voltage generator for generating a positive voltage required in a word line; And a negative voltage generator for generating a negative voltage required by the word line.

Preferably, the level voltage selecting means includes: a bit line precharge voltage switching unit configured to receive and switch a plurality of voltages required in the bit line from the bit line precharge voltage generator; A cell plate line voltage switching unit configured to receive and switch a plurality of voltages required by the cell plate line from the cell plate voltage generator; A positive voltage switching unit configured to receive and switch a plurality of positive voltages required by the word line from the positive voltage generator; And a negative voltage switching unit for switching the negative voltage required by the word line from the negative voltage generator.

Preferably, said different plurality of internal voltages are within ± 5 volts.

Preferably, the mode control means can control to have an erase mode for erasing information stored in the nitride film in the cell by increasing the threshold voltage of the cell transistor in the cell array.

Preferably, the mode control means may control to have a recall mode for transferring information stored in the nitride film in the cell to the cell capacitor when power is applied.

Preferably, the mode control means may control to have a program mode for transferring data information stored in the cell capacitor to the nitride film in the cell when the power is cut off.

Preferably, the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-oxide-silicon cell transistors.

Preferably, the cell transistors arranged in the nonvolatile DRAM are metal-oxide-nitride-oxide-silicon cell transistors.

Preferably, the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-nitride2-silicon cell transistors.

According to a second aspect of the present invention, a program mode driving method includes: a first step of refreshing a cell transistor arrayed in a nonvolatile DRAM using a trappable insulator; And a second step of applying a voltage appropriate for causing local hot hole injection or tunneling of electrons to the cell capacitor side including the cell data in the " H " state.

According to a third aspect of the present invention, a method of driving a recall mode includes: a first step of emptying a storage node of the cell transistor in driving an array of cell transistors in a nonvolatile DRAM using a trappable insulator; The drain (part connected to the bit line) voltage is relatively higher than the source (part connected to the cell capacitor) voltage applied to the cell transistor so that different voltages are allowed on the storage node according to the logic state stored in the nitride film of the cell transistor. A second step of raising to; And a third step of re-leashing the cell transistor.

According to a fourth aspect of the present invention, an erase mode driving method includes a first step of backing up data stored in a cell capacitor in a cell transistor in driving a cell transistor arrayed in a nonvolatile DRAM using a trappable insulator; A second step of raising the threshold voltage of the cell transistor as a whole through F-N tunneling of electrons in the nitride film of the cell transistor; And a third step of writing the backup data to the cell capacitor.

The nonvolatile DRAM according to the present invention includes a nitride film (Nitride) which is an insulator capable of trapping electrons. That is, the cell transistor of the nonvolatile DRAM (NVDRAM) according to an embodiment may be configured by adding a capacitor to the SONOS type flash memory structure, as shown in FIG. 2. According to another embodiment, a capacitor may be added to the MONOS type flash memory structure. According to another embodiment, a capacitor may be added to the SON1N2S type flash memory structure. Trapable nitride films of the SONOS type and MONOS type can be obtained by chemical vapor deposition (CVD), for example, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), and hafnium oxide ( HfO ₂ ) can be obtained by evaporation in an atmosphere, and the SON1N2S type N2 nitride film can be obtained by heating by heating at a temperature.

3 is an overall block diagram for driving an NVDRAM cell array according to the present invention. The NVDRAM core 350 is divided into banks (BANK0 to 3) and blocks (BLOCK0 to 7) for each bank. It can be arranged in an array form.

The NVDRAM according to the present invention generally includes an internal power generator 310 for generating a plurality of internal voltages by receiving an external power source in addition to the components required to drive the DRAM, and a mode controller for controlling each mode of the NVDRAM. In operation 320, a voltage level selector 330 and a voltage level selector 330 for receiving and switching a plurality of voltages required by the NVDRAM core 350 from the internal power generator 310 according to each mode. And a row decoding unit 340 for applying the selected voltage output from the NVDRAM core 350. Since the column decoding unit 360 and the sense amplifier 370 are the same as those used in the DRAM, a separate description will be omitted.

The internal power generator 310 may include a bit line precharge voltage generator 311 for generating a plurality of voltages required by a bit line, and a cell plate voltage generator for generating a plurality of voltages required by a cell plate. 313, a positive voltage generator 315 for generating a positive voltage required by the word line, and a negative voltage generator 317 for generating a negative voltage required by the word line.

The voltage level selector 330 includes first to eighth voltage level selectors LEVEL SELECTOR 0 to 7 to generate a plurality of voltages required by the first to eighth blocks BLOCK 0 to 7, respectively. The input is switched from the unit 310.

4 is a block diagram illustrating main parts for applying a voltage to the NVDRAM core 350 of the present invention.

The first voltage level selector 410 and the row decoder 420 are a voltage level selector 330 and a row decoder 340 corresponding to the first block 430 in the NVDRAM core 350. The first voltage level selector 410 is required by the bit line precharge voltage switching unit 411 and the cell plate line to switch a plurality of voltages required in the bit line from the bit line precharge voltage generator 311. The cell plate line voltage switching unit 413 for switching the plurality of voltages to be input from the cell plate voltage generation unit 313 and the plurality of positive voltages required for the word line from the positive voltage generation unit 315 for switching. The negative voltage switching unit 415 and the negative voltage required for the word line may be input from the negative voltage generation unit 317 to include a negative voltage switching unit 417 for switching.

5 is an explanatory diagram for applying a voltage to a word line according to the present invention.

The row decoder 420 uses the voltage applied from the positive voltage switching unit as the drain voltage VDD and the voltage applied from the negative voltage switching unit as the source voltage VSS.

Hereinafter, the operation of the NVDRAM cell shown in FIG. 6 will be described.

In order to use the NVDRAM according to the present invention as a nonvolatile memory when the power is cut off and as a volatile DRAM when the power is applied, the following four modes are required. That is, the NVDRAM according to the present invention may have (1) DRAM mode, (2) program mode, (3) RECALL MODE, and (4) erase mode. have.

DRAM mode is the process in which NVDRAM behaves like DRAM. The program mode is a process of transferring data information stored in the cell capacitor 209 to the nitride film 203 when the NVDRAM is powered off. The recall mode is a process of transferring data information in the nitride film 203 to the cell capacitor 209 when power is applied to the NVDRAM. The erase mode is a process of erasing the stored information by filling the nitride film 203 of all the cell arrays with the same amount of electrons. Hereinafter, each mode will be described in detail.

DRAM mode

NVDRAM according to the present invention is the same as the operation of the general DRAM in the DRAM mode. However, in the conventional DRAM, the gate oxide film of the cell transistor is used, but in the NVDRAM of the present invention, since the insulator capable of trapping electrons is used, the refresh characteristics of the device are improved.

That is, in the cell transistor in which the information stored in the nitride film is erased, electrons are trapped, so that the substrate doping concentration of the cell transistor is the same as that of a general DRAM using a gate oxide film. The threshold voltage of the cell transistor according to the invention is higher than the threshold voltage of the DRAM. Therefore, by lowering the substrate doping concentration in the manufacture of the cell transistor, it is possible to maintain the threshold voltage of the cell transistor according to the present invention to approximately the threshold voltage of a general DRAM. As a result, the refresh period characteristic of the NVDRAM according to the present invention, which is one of the main parameters of the DRAM, is greatly improved than the general DRAM. This is because, when the substrate doping concentration of the cell transistor is low, a low electric field is formed between the junction of the cell transistor connected to the cell capacitor and the substrate, and the junction leakage is reduced due to the low electric field. to be.

PROGRAM mode

When a power failure is detected or the power is cut off, a program mode for transferring data information stored in the cell capacitor to the nitride film 203 is performed.

(1) Refresh all the arrayed cells in DRAM mode to execute the program mode. This clarifies the logic state of the data stored in the cell capacitor.

② The data of "H" state stored in the cell capacitor is used to cause local hot hole injection or F-N tunneling of electrons so that the cell capacitor side nitride film is partially turned on. Here, which of the injection of holes and the F-N tunneling of electrons occur more is influenced by the thickness of the oxide layer. On the other hand, it is difficult to attract hot holes only by the voltage included in the cell (up to 2.5 volts).

Thus, a voltage is applied to generate a potential difference of approximately 5.5 volts between the word line and the cell plate. For example, a negative voltage of -3 volts may be applied to a word line and 2.5 volts may be applied to a cell plate. Then, for a cell capacitor that stores "H" data, the voltage difference between the storage node voltage of 5 volts and the gate voltage of (-) 3 volts due to cell coupling partially subtracts the threshold voltage, as shown in FIG. Enough to get down. However, for a cell capacitor that stores "L" data, the voltage difference between the storage node voltage of 2.5 volts and the gate voltage of (-) 3 volts is too small to drive hot hole injection. Using plate boosting technology inherently blocks programming disturbances and allows low power, high reliability operation to be achieved.

③ On the other hand, if the capacitance of the cell capacitor is small and the hole is not sufficiently injected from the cell capacitor into the nitride film or the FN tunneling of the electron is insufficient, the refresh process of ① and the stress process of ② must be repeated. There is.

RECALL mode

① Apply voltage that can empty storage node to word line and bit / bit bar line. For example, two volts can be applied to all word lines and zero volts to all bit / bitbar lines.

(2) After that, apply 3 volts to the bit / bit bar line while maintaining the word line voltage. If the data stored in the nitride film is " H ", the source voltage (storage node side) threshold voltage Vth of the cell transistor is lowered, but the threshold voltage Vth of the drain side (bit line side) of the cell transistor is set by programming. Not affected Because of the relatively high drain voltage, the surface voltage on the drain side is lowered, which allows a voltage transfer of approximately 2 volts. On the other hand, if the data stored in the nitride film is " L ", the DRAM threshold voltage set so that the saturation value of the nonvolatile DRAM using the nitride film is 1.2 volts is precisely controlled in the manufacturing process, and only allows 0.8 volt on the storage node. .

③ If the data stored in the cell is "H" 2 volts, "L" is 0.8 volts, the cell can be sensed based on the bit line precharge voltage 1.25 volts. When sensing, the selected word line applies 4 volts, and the unselected word line applies (−) 3 volts, respectively.

(4) It is necessary to refresh to clarify the state of the data stored in the cell capacitors.

ERASE mode

In order to switch to DRAM mode after performing the RECALL mode, it is necessary to match the threshold voltages of the cell transistors in the same block.

① To this end, first, data of one block is refreshed, and all data stored in the cell capacitors of each of the arrayed cells are backed up to the temporary memory block 380. The manner of backing up data may vary according to the size of the temporary memory block 380, according to one embodiment. According to another embodiment, it may be decided depending on whether to use all or part of the temporary memory block 380. For example, if the size of the temporary memory block 380 is the same as the individual block constituting the bank, and the entire temporary memory block is used for backup, the temporary memory block 380 can be backed up for each block in the bank. Alternatively, if the size of the temporary memory block corresponds to one bank of the NVDRAM memory blocks 350 having four banks, and the entire temporary memory block is used for data backup, each bank may be backed up. Alternatively, if the temporary memory block 380 is the same as the NVDRAM memory block 350 composed of four banks, and the entire temporary memory block is used for data backup, the data of the NVDRAM memory block 350 may be backed up at a time. . The cell structure of the temporary memory block 380 is preferably the same as the structure of the arrayed cells according to the present invention, in terms of manufacturing convenience and economics, but is not necessarily the same structure. That is, a structure capable of storing data for a predetermined time is sufficient. The word line voltage Vwl, the bit line precharge voltage Vblp, and the plate line voltage Vcp applied to the temporary memory block need to be appropriately adjusted according to the backup method of the data. It is only a matter that is obvious to those who have, and beyond the essence of the present invention will not be mentioned anymore.

② Apply about 5 volts to the word line voltage Vwl of the cell transistor and about -3 volts to the bit line precharge voltage Vblp and the body voltage Vbb. The channel is then inverted throughout the cell transistor. In this state, F-N tunneling (Fowler Nordheim Tunnelling) occurs in all channels, and as the electrons are trapped in the nitride film, the threshold voltage is increased as a whole. In this process, the previously programmed threshold voltage is cleared. Since the number of traps of the nitride film is limited, saturation occurs when F-N tunneling occurs over a predetermined amount. That is, if the data stored in the nitride film was "L", there would be almost no electrons tunneled, but if the data stored in the nitride film was "H", the storage node side would have a partly low threshold voltage, and the concentration of electrons in this area would be concentrated. Tunneling will occur and saturate. As a result, all of the arrayed cells may have a threshold voltage, that is, 1 ± 0.2V, required to operate as a DRAM.

③ Finally, write the data backed up to the cell.

The sub-voltages for each operation state of the nonvolatile DRAM according to the present invention are summarized as follows.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of the claims to be described.

According to the configuration as described above, the present invention can drive the nonvolatile DRAM with only a low internal voltage compared to the known technology by applying a different voltage to the cell plate.

In addition, due to the use of such a driving method, the structure of the nonvolatile DRAM is not significantly different from that of a conventional DRAM, and thus it can be manufactured without addition of manufacturing equipment or construction of a new manufacturing line. Therefore, the manufacturing cost can be lowered. In particular, it is easier to control than the floating gate type NVDRAM, and the time required to perform the program mode required at power-off can be significantly reduced.

In addition, when operating the NVDRAM according to the present invention in the DRAM mode, the refresh (Refersh Period) characteristics are significantly improved compared to the general DRAM. As a result, power consumption can be significantly reduced compared to general DRAM.

Claims (37)

A nonvolatile DRAM comprising a cell transistor having an insulator capable of trapping charge between a substrate and a gate, and a core in which the cell transistor is arrayed. Internal power generating means for receiving an external power and generating a plurality of internal voltages; Mode control means for generating a mode control signal to control the nonvolatile DRAM for each mode; Voltage level selection means for switching a plurality of voltages required by the core of the nonvolatile DRAM according to the mode from the internal power generation means; And Row decoding means for applying a voltage output from the voltage level selecting means to a core of the nonvolatile DRAM Nonvolatile DRAM driving circuit comprising a. The method of claim 1, wherein the internal power generating means, A bit line precharge voltage generator for generating a plurality of voltages required by the bit line; A cell plate voltage generator for generating a plurality of voltages required by the cell plate; A positive voltage generator for generating a positive voltage required by the word line; And Negative voltage generator for generating negative voltage required on word line Nonvolatile DRAM driving circuit using a trappable non-conductor comprising a. The method of claim 2, wherein the level voltage selection means, A bit line precharge voltage switching unit configured to receive and switch a plurality of voltages required by the bit line from the bit line precharge voltage generator; A cell plate line voltage switching unit configured to receive and switch a plurality of voltages required by the cell plate line from the cell plate voltage generator; A positive voltage switching unit configured to receive and switch a plurality of positive voltages required by the word line from the positive voltage generator; And Negative voltage switching unit for switching the negative voltage required in the word line from the negative voltage generator Nonvolatile DRAM driving circuit using a trappable non-conductor comprising a. The method of claim 1, And said different plurality of internal voltages are within ± 5 volts. The method of claim 1, wherein the mode control means, And controlling to have an erase mode for erasing information stored in the nitride film in the cell by increasing the threshold voltage of a cell transistor in the cell array. The method of claim 5, wherein the mode control means, The nonvolatile DRAM driving circuit using a trappable non-conductor, characterized in that the control mode to further have a recall mode for transferring information stored in the nitride film in the cell to the cell capacitor when power is applied. According to claim 5, The mode control means, When the power is cut off, non-volatile DRAM driving circuit using a trappable insulator characterized in that it further controls to have a program mode for transferring data information stored in the cell capacitor to the nitride film in the cell. The method of claim 7, wherein Power monitoring means for early detection of an interruption of power applied to the nonvolatile DRAM; And Battery for operating the nonvolatile DRAM for a predetermined time even when the power is cut off Nonvolatile DRAM driving circuit using a trappable insulator further comprises. The method of claim 1, Temporary memory block for backing up data stored in each arrayed cell Nonvolatile DRAM driving circuit using a trappable insulator further comprises. The method of claim 9, The amount of data per backup for backing up the data stored in each of the arrayed cells to the temporary memory block is determined by the size of the temporary memory block to which power supply voltage can be independently applied. Nonvolatile DRAM driving circuit. The method of claim 10, And a size of the temporary memory block is the same as one of a plurality of banks constituting the nonvolatile DRAM core. The method according to any one of claims 1 to 11, And the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-oxide-silicon cell transistors. The method of claim 12, wherein the nitride film, A nonvolatile DRAM driving circuit using a trappable insulator, which is deposited in an atmosphere of any one of aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), and hafnium oxide (HfO ₂ ). The method according to any one of claims 1 to 11, And the cell transistors arranged in the nonvolatile DRAM are metal-oxide-nitride-oxide-silicon cell transistors. The method of claim 14, wherein the nitride film, A nonvolatile DRAM driving circuit using a trappable insulator, which is deposited in an atmosphere of any one of aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), and hafnium oxide (HfO ₂ ). The method according to any one of claims 1 to 11, The cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-second nitride-silicon-type cell transistors. DRAM drive circuit. The method of claim 16, The second nitride film is a nonvolatile DRAM driving circuit using a trappable insulator, characterized in that to grow by heating the temperature. In driving a cell transistor having an insulator capable of trapping charge between a substrate and a gate, Refreshing the cell transistor; And A second step in which data of the "H" state in the cell capacitor causes localized hot hole injection or tunneling of electrons to apply an appropriate voltage for the insulator to be partially turned on in the cell capacitor Program mode driving method comprising a. The method of claim 18, wherein the second step, And applying a word line voltage and a cell plate voltage such that the potential difference between the word line and the cell plate of the cell transistor is approximately 5.5 volts. The method of claim 18 or 19, And the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-oxide-silicon cell transistors. The method of claim 18 or 19, The cell transistor arrayed in the nonvolatile DRAM is a metal-oxide-nitride-oxide-silicon-type cell transistor. The method of claim 18 or 19, The cell transistor arrayed in the nonvolatile DRAM is a silicon-oxide-first nitride-second nitride-silicon (Silicon-Oxide-Nitride1-Nitride2-Silicon) type cell transistor. The method of claim 18, And if the logical states of the data are unclear by the amount of charge stored in the nitride film, repeating the first and second steps. In driving a cell transistor having an insulator capable of trapping charge between a substrate and a gate, A first step of emptying the storage node of the cell transistor; A second step of raising a drain voltage relatively to a source voltage applied to the cell transistor so that a different voltage is allowed on the storage node according to a logic state stored in the insulator of the cell transistor; And A third step of refreshing the cell transistor Recall mode driving method comprising a. The method of claim 24, wherein the first step is And applying a word line voltage and a bit / bit bar line voltage such that the word line of the cell transistor maintains a potential difference of approximately two volts higher than the bit / bit bar line. The method of claim 25, wherein the second step, And while maintaining the word line voltage, applying the word line voltage and the bit / bit bar line voltage such that the bit / bit bar line of the cell transistor maintains a potential difference of approximately 1 volt higher than the word line. How to operate the recall mode. The method of claim 24, wherein the second step, If data stored in the nitride film of the cell transistor is "H", a voltage of approximately 2 volts is applied to the storage node of the cell transistor. If data stored in the nitride film of the cell transistor is "L", the data is stored on the storage node. And a voltage of approximately 0.8 volts. The method of claim 24, To detect the state of data stored in the cell transistor, the bit line precharge voltage of the cell transistor is 1.25 volts, the word line voltage of the cell transistor is 4 volts, and the unselected word line voltage is negative (-). Fourth Step Applying 3 Volts Each Recall mode driving method further comprising. The method according to any one of claims 24 to 28, And the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-oxide-silicon cell transistors. The method according to any one of claims 24 to 28, And the cell transistors arranged in the nonvolatile DRAM are metal-oxide-nitride-oxide-silicon cell transistors. The method according to any one of claims 24 to 28, And the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-second nitride-silicon transistors. In driving a cell transistor having an insulator capable of trapping charge between a substrate and a gate, Backing up data stored in a cell capacitor in the cell transistor; A second step of raising the threshold voltage of the cell transistor as a whole through F-N tunneling of electrons in the nitride film of the cell transistor; And A third step of writing the backup data to the cell capacitor Erasing mode driving method comprising a. The method of claim 32, wherein the second step, And applying approximately 5 volts to the word line voltage of the cell transistor and approximately (-) 3 volts to the bit line precharge voltage and the body voltage. 33. The method of claim 32, And the threshold voltage after performing the second step is 1 ± 0.2 volts. The method of any one of claims 32 to 34, wherein And the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-oxide-silicon cell transistors. The method of any one of claims 32 to 34, wherein The cell transistors arranged in the nonvolatile DRAM are metal-oxide-nitride-oxide-silicon cell transistors. The method of any one of claims 32 to 34, wherein And the cell transistors arranged in the nonvolatile DRAM are silicon-oxide-nitride-nitride-silicon-type cell transistors.

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