KR100557052B1 - Apparatus for generating a writing pulse - Google Patents

Abstract

The present invention discloses a recording pulse generator capable of precisely controlling recording pulses in accordance with a pattern of an NRZI signal to improve recording characteristics.

The present invention outputs time delay data according to an address value determined by a combination of a mark and a space of NRZI, converts the NRZI signal into six window signals, and delays these six window signals according to the time delay data. And then combine to generate write pulses.

Optical Disc, Recording Pulse, LD Power, Pickup, Pulse Generator

Description

Recording pulse generator {APPARATUS FOR GENERATING A WRITING PULSE}             

1 is a block diagram of a general optical disc recording and reproducing apparatus.

2 is a diagram showing an output waveform of a recording pulse generator according to each length of a mark and a space according to a standard;

3 is a block diagram of a recording pulse generator according to a preferred embodiment of the present invention.

4 is a timing diagram of the NRZI pattern analyzer in FIG.

FIG. 5 is a table illustrating time delay data according to an address stored in a write strategy RAM in FIG. 3. FIG.

FIG. 6 is a detailed configuration diagram of a time delay signal selector in FIG. 3. FIG.

7 is a timing diagram of the phase controller DLL in FIG.

8 is a block diagram of the window signal generator in FIG.

9 is a block diagram of the pulse generator in FIG.

10 is a timing diagram for the first pulse in FIG.

FIG. 11 is a timing diagram for multiple pulses in FIG. 9; FIG.

12 is a timing diagram for an erase pulse in FIG.

13 is an overall timing diagram of a recording pulse generating apparatus according to a preferred embodiment of the present invention.

<Name of the code for the main part of the drawing>

10: NRZI pattern analyzer 11: window signal generator

12: pulse generator 13: write strategy RAM

14: time delay signal selector 20 to 27: flip-flop

30,31,32: AND gate 33: NAND gate

40: OR gate 50: phase controller

51, 52, 53, 54: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disc recording and reproducing system, and more particularly, to a recording pulse generating apparatus which improves recording characteristics by precisely controlling the time of a recording pulse.

An optical disc recording and reproducing system is a system for recording data on an optical disc and reproducing the recorded data. There are two formats for recording: CD (R or RW) format or DVD (-R, + R, -RW, + RW) format.

1 shows a block diagram of a general optical disc recording and reproducing apparatus. Referring to Fig. 1, the optical disc recording and reproducing apparatus includes a recording DSP 1, a recording pulse generator 2, an LD driver 3, a pickup 4, an RF amplifier 5 (Amp), and a reproduction DSP 6 It is composed of

The recording DSP 1 receives data to be recorded from a host such as a PC, converts the data into a format suitable for a disk to be recorded, and outputs the data.

The write pulse generator 2 receives the format from the write DSP 1, generates a write pulse, and outputs the write pulse to the LD driver 3.

The LD driver 3 converts the write pulse into LD power and outputs it to the pickup 4.

The pickup 4 turns on / off the laser light in accordance with the LD power, thereby recording data on the disc.

On the other hand, the data read from the disk is converted into an RF signal and output to the RF amplifier 5.

The RF amplifier 5 amplifies the RF signal according to the length of the mark and space of the data recorded on the disk, then equalizes the waveform, and then converts the RF signal into digital data of a predetermined form. And output to the reproduction DSP6.

The reproduction DSP 6 decodes the converted digital data and outputs the same to the host.

As described above, the recording pulse generator 2 controls the laser light to be output by delaying the laser light for a predetermined time from the reference time point according to the condition in order to improve the disc recording characteristics when the laser light is output to the disk. . This is called a pattern adaptive recording method (aka write strategy).

2 shows an output waveform of a recording pulse generator according to each length of a mark and a space according to a standard. As shown in Fig. 2, the write pulse generator 2 outputs the WRPULSE signal and the ERPULSE signal to the LD driver 3, respectively. The LD driver 3 outputs LD power to the pickup 4 by using the WRPULSE signal and the ERPULSE signal.

The LD power is composed of three levels of write power to write to the disc, erase power to erase the disc, and read power to reproduce the disc. That is, LD power has WPULSE signal of 1 and ERPULSE signal of 0, write power (P _O ), WRPULSE signal of 0, and ERPULSE signal of 0, read power (P _B ), WRPULSE signal of 0, and ERPULSE signal of 1 In this case, the erase power P _E is output.

Accordingly, the LD power can control different power levels by varying the positions of the rising edge and the falling edge of the WRPULSE signal and the ERPULSE signal corresponding to the length of the mark and the space.

As described above, it is the role of the write strategy to control the positions of the rising edge and the falling edge of the WRPULSE signal and the ERPULSE signal corresponding to the length of the mark and the space.

Such a write strategy is for generating accurate recording marks by suppressing distortion of recording marks due to thermal interference when recording data on a phase change disk.

In general, in the case of recording on a high density optical disc, recording interference occurs in which the mark edge is moved by the conditions before and after the mark to be recorded. A write strategy is proposed to solve such write interference.

According to this write strategy, a multi-pulse waveform as long as the recording mark length is made to reduce the distortion of the mark recorded on the disk, and the edge position of the recording pulse is changed in correspondence with the space length before and after the recording mark. That is, when the length of the space before the mark to be recorded is short, the mark edge to be recorded increases due to the influence of the heat when the mark before the space is recorded. In order to correct this, the position of the recording mark edge is determined by delaying the start position of the recording pulse relatively much in advance. On the contrary, if the length of the space before the mark to be recorded is long, the mark edge to be recorded becomes short due to the influence of heat when the mark before the space is recorded. In order to correct this, the start position of the recording pulse to be recorded in advance is relatively less delayed. At this time, the correction amount is changed according to the space length before and after the mark to be recorded and the length of the mark to be recorded.

As described above, in the conventional optical recording / reproducing system, data can be recorded by irradiating the disk with the recording power converted in accordance with the recording pulse generated from the recording pulse generator.

However, conventionally, only the data recording by irradiating the LD power to the disk is known, and the method of generating the recording pulse for generating the LD power is not known yet.

An object of the present invention is to solve the above problems.

Accordingly, one object of the present invention is to provide a write pulse for generating LD power.

Another object of the present invention is to improve the recording characteristics of a recording medium by controlling the recording pulse more precisely by using a write strategy.

According to a preferred embodiment of the present invention for achieving the above object, the recording pulse generating apparatus counts the length of the mark and the space in the NRZI signal, respectively, and then outputs an address value by combining the counted values, respectively, An NRZI pattern analyzer for outputting an NRZI signal obtained by delaying the NRZI signal for a predetermined time; A window signal generator for outputting a plurality of window signals for producing a write pulse using the delayed NRZI signal, and for outputting a plurality of window signals for producing an erase pulse; A memory in which time delay data according to a plurality of address values is stored in a table so that time delay data corresponding to an address value output from the NRZI pattern analyzer is output; A time delay signal selector for respectively selecting delay clock signals corresponding to time delay data output from the memory corresponding to the address value among a plurality of delay clock signals having different clock delays; And a pulse generator for latching a plurality of signals output from the window signal generator according to delay clock signals selected by the time delay signal selector, and then combining the latched signals to generate a write pulse and an erase pulse. do.

The delayed NRZI signal is the same as the NRZI signal before the length of the mark and space is delayed.

The time delay data may include first time delay data for determining a rising edge of the first pulse, second time delay data for determining a falling edge of the first pulse, and first width delay data for determining the width of the multi-pulse. It is divided into time delay data for recording pulse generation including three time delay data and time delay data for erasing pulse generation for determining the rising edge of the erase pulse.

When the address value is determined by a combination of a count value for the length of the mark and a count value for the space before the mark, time delay data for generating a recording pulse is selected and output.

When the address value is determined by a combination of a count value for the length of the mark and a count value for the space after the mark, time delay data for erasing is selected and output.

The plurality of window signals for generating the write pulse may be a predetermined signal one cycle ahead in a section in which the delayed NRZI signal generates a pulse having a predetermined width in synchronization with the section 1 and the delayed NRZI signal is 1 section. A second signal for generating a pulse having a width, a third signal for generating a pulse every even period in a period where the delayed NRZI signal is 1, and one period for the third signal in a period where the delayed NRZI signal is 1 It consists of a 4th signal which produces the pulse which delays gradually.

The plurality of window signals for generating the erase pulse include a fifth signal generating the same waveform as the delayed NRZI signal and a sixth signal generated one cycle earlier in the same waveform as the NRZI signal.

The time delay signal selector may include: a phase controller configured to generate a plurality of delay clock signals obtained by differently time delaying the clock signals; And a multiplexer for selecting and outputting the plurality of delayed clock signals using the time delay data.

The pulse generator may include a plurality of flip-flops for latching the first to sixth signals, respectively; A plurality of AND gates for ANDing each of the first to fourth signals latched in the flip-flop; An OR gate for ORing the first to fourth signals calculated at the AND gate; And a NAND gate configured to perform an NAND operation on the fifth and sixth signals latched in the flip-flop to generate an erase pulse.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 shows a block diagram of a recording pulse generating apparatus according to a preferred embodiment of the present invention. Referring to FIG. 3, the recording pulse generator includes an NRZI pattern analyzer 10 which outputs an address value and a delayed NRZI signal from an NRZI signal and a length of a mark from the delayed NRZI signal. A window signal generator 11 for generating six signals, a write strategy RAM 13 for storing a plurality of address values and time delay data values corresponding to the plurality of address values, and outputted from the NRZI pattern analyzer 10. A time delay signal selector 14 for selecting delay clock signals corresponding to time delay data values corresponding to an address value, and the window signal generator 11 according to delay clock signals output from the time delay signal selector 14. And a pulse generator 12 for latching each of the six signals outputted from &lt; RTI ID = 0.0 &gt;

The NRZI pattern analyzer 10 counts the mark length and the space length from the NRZI signal, respectively. That is, as shown in Fig. 4, the NRZI pattern analyzer 10 calculates a mark_count value for counting the length of the mark and a space_count value for counting the length of the space, respectively. The address values are determined by combining the counted values.

That is, the NRZI pattern analyzer 10 determines the ls_addr value by combining a mark_count value that counts the length of the mark to be recorded and a space_count value that counts the length of the leading space. The ts_addr value is determined by combining the mark_count value counting the length of the mark to be recorded and the space_count value counting the length of the trailing space. The ls_addr and ts_addr values thus determined are output to the write strategy RAM 13 as wsram_addr signals.

In the write strategy RAM 13, time delay values td1, td2, td3, and td4 previously obtained in advance are stored. In other words, a plurality of write experiments are performed on a disk to obtain jitter characteristics having the best recording characteristics, that is, time delay values having the least jitter, and are stored in the write strategy RAM 13 as a table. Here, td1 represents the position value of the rising edge of the first pulse of the write pulse WRPULSE, and td2 represents the position value of the falling edge of the first pulse. In addition, td3 represents the width of the multi-pulse of the write pulse. The rising edge of the multi-pulse is in phase with the rising edge of the clock signal ref_clk and the width is varied by changing the position of the falling edge. td4 represents a position value of the rising edge of the erase pulse ERPULSE. Therefore, the first pulse of the recording pulse is determined by td1 and td2, the multi-pulse of the recording pulse is determined by td3, and the erase pulse is determined by td4.

5 is a table showing a relationship between time delay data and an address.

Therefore, when the address value is the ls_addr value by combining the ms_count value counting the length of the mark to be recorded by the NRZI pattern analyzer 10 and the space_count value counting the length of the preceding space, td1 corresponding to the corresponding address value, td2 and td3 are output, respectively.

If the address value is the ts_addr value by combining the ms_count value that counted the length of the mark and the space_count value that counted the length of the subsequent space, td4 corresponding to the address value is output. As a result, time delay data (td1, td2, td3) for generating a recording pulse is output using the ms_count value counting the length of the mark to be written and the space_count value counting the length of the space before it, and the length of the mark is output. The time delay data td4 for generating an erase pulse is output using the ms_count value counting and the space_count value counting the length of the subsequent space.

For example, if the mark to be written is 8T, the space before it is 3T, and the space after it is 3T, the ms_count value is 8 and the space_count value is 4 and 3, respectively. . At this time, the ls_addr value determined by combining the length of the mark to be recorded and the space length before it becomes LS4M8. Accordingly, the address value becomes 14, and the td1, td2, and td3 values corresponding to the address value 14 are respectively output.

In addition, the ts_addr value determined by combining the length of the mark to be recorded and the space length thereafter is M8TS3. Therefore, the address value is determined, and the td4 value corresponding to the address value is output.

At this time, the time delay data stored in the write strategy RAM 13 is loaded by the microcomputer interface. In addition, the microcomputer interface stores the time delay data in the write strategy RAM 13 to correspond to an address in a table.

As shown in Fig. 5, the write strategy RAM 13 has 81 addresses and is composed of td1, td2, td3, and td4, each of which is allocated 5 bits. Here, the number of addresses 81 is that the length of the mark and the length of the space can be 3T to 11T, respectively, so the combination of the length of the mark and the length of the space is 81, and the combined values are the respective address values Because it corresponds to.

As described above, the NRZI pattern analyzer 10 outputs, to the window signal generator 11, a signal nrzi_ref obtained by delaying the NRZI signal for a predetermined time.

At this time, the delayed signal nrzi_ref preferably has the same waveform as the NRZI signal. That is, if the NRZI signal consists of a mark of 8T and a space of 3T, the delayed signal nrzi_ref also consists of a mark of 8T and a space of 3T.

As such, delaying the NRZI signal for a predetermined time is to synchronize the NRZI signal with the wsram_addr signal. The NRZI signal must be synchronized with the wsram_addr signal so that the pulse generator 12 writes the write pulse WRPULSE and the erase pulse for the corresponding NRZI signal by the clock signals delayed using the data output from the write strategy RAM 13. ERPULSE).

Accordingly, the NRZI pattern analyzer 10 outputs the delayed signal nrzi_ref to the window signal generator 11 at the time when the wsram_addr signal is output.

As illustrated in FIG. 6, the time delay signal selector 14 includes a plurality of delay clocks dll_clk [generated for each of the time delay data td1, td2, td3, and td4 output from the write strategy RAM 13. 0], dll_clk [1], dll_clk [2], ..., dll_clk [31]) Delay clock signals corresponding to the respective time delay data (td1, td2, td3, td4) one by one (td1_clk, td2_clk) , td3_clk, td4_clk) are selected and output to the pulse generator 12.

Here, the plurality of delayed clock signals are signals obtained by differently delaying a clock ref_clk signal. This is done by a phase controller (DLL: Delay Locked Loop, 50). The delay amount at this time is (n / N) Tw. Here, N is the number of delayed clock signals to be output, Tw is the period of the clock signal, n is the clock signal. For example, as shown in FIG. 7, when the number of delayed clock signals to be output is 32, 1 / 32Tw delayed dll_clk [0], 1 / 32Tw delayed dll_clk [1], ... of the clock signal ref_clk. And dll_clk [31] delayed by 32 / 32Tw are output.

The 32 output delay clock signals are input to four multiplexers 51, 52, 53, and 54, respectively. Here, four multiplexers are used because four time delay data td1, td2, td3, and td4 output from the write strategy RAM 13 are output. The time delay data value may be one of 0 to 31. Therefore, if td1, td2, td3 and td4 are 2, 27, 17 and 10, respectively, in the multiplexers 51, 52, 53 and 54 to which td1, td2, td3 and td4 are input, td1_clk corresponding to dll_clk [1], td2_clk corresponding to dll_clk [26], td3_clk corresponding to dll_clk [16], and td4_clk corresponding to dll_clk [9] are outputted to the pulse generator 12, respectively.

On the other hand, the window signal generator 11, as shown in Figure 8, the four window signals (fp_win1, fp_win2, mp_win1, mp_win3) and the erase pulse (for generating the write pulse (WRPULSE) signal from the delayed signal (nrzi_ref)) Two window signals ep_win1 and ep_win2 for generating ERPULSE are output to the pulse generator 12, respectively.

Here, the four window signals for generating the recording pulse are the first to generate a pulse having a constant width (2T) in synchronization with the interval of the delayed NRZI signal (nrzi_ref) 1, as shown in Figs. The second signal (fp_win2) for generating a pulse having a predetermined width (2T) one cycle ahead of the signal fp_win1, the delayed NRZI signal (nrzi_ref) 1, and the delayed NRZI signal (nrzi_ref) is 1 A third signal mp_win1 for generating a pulse at every even period in a section and a fourth signal for generating a pulse for delaying the third signal mp_win1 by one period in a section in which the delayed NRZI signal nrzi_ref is 1; (mp_win3).

In addition, the two window signals for generating the erase pulse ERPULSE are the fifth signal ep_win1 and the NRZI signal nrzi_ref which generate the same waveform as the delayed NRZI signal nrzi_ref, as shown in FIG. 12. ) And the sixth signal ep_win2 generated one cycle before.

As such, the six signals fp_win1, fp_win2, mp_win1, mp_win3, ep_win1, and ep_win2 generated from the window signal generator 11 are output to the pulse generator 12.

The pulse generator 12 latches the six signals in accordance with the delay clock selected from the time delay signal selector 14, and then combines the latched signals to generate a write pulse.

The pulse generator 12 will be described in detail with reference to FIG. 9. As shown in FIG. 9, the pulse generator 12 includes a plurality of flip-flops 20 to 27 for latching the first to sixth signals, respectively, and latched in the plurality of flip flops 20 to 27, respectively. A plurality of AND gates 30, 31 and 32 for ANDing the first to fourth signals, and an OR gate 40 for ORing the first to fourth signals calculated at the AND gates 30, 31, and 32. And a NAND gate 33 for NAND-operating the fifth and sixth signals latched in the plurality of flip-flops 20 to 27, respectively.

Here, a first clock fp_win1 and a delayed clock signal td1_clk corresponding to td1 are input to the first flip-flop 20, and a second signal fp_win2 and td2 corresponding to the second flip-flop 21. The delay clock signal td2_clk is input. A third clock mp_win1 and a delayed clock signal td3_clk corresponding to td3 are input to the third flip-flop 22, and a third signal mp_win1 and a clock signal ref_clk are input to the fourth flip-flop 23. Is entered. The fourth flip-flop 24 receives the fourth signal mp_win3 and the delayed clock signal td3_clk corresponding to td3, and the sixth flip-flop 25 receives the fourth signal mp_win3 and the clock signal ref_clk. ) Is entered. In addition, a delayed clock signal td1_clk corresponding to the fifth signal ep_win1 and td1 is input to the seventh flip-flop 26, and a sixth signal ep_win2 and td4 corresponds to the eighth flip-flop 27. The delay clock signal td4_clk is input.

First, the first flip-flop 20 and the second flip-flop 21 will be described with reference to FIG. 10. As described above, the first signal fp_win1 and the second signal fp_win2 are generated in the window signal generator. As shown in FIG. 10, the first flip-flop 20 latches the first signal fp_win1 by td1 according to the delay clock signal td1_clk and outputs the first delay signal fp_win1_lat. The second flip-flop 21 latches the second signal fp_win2 by td2 according to the delay clock signal td2_clk and outputs a second delay signal fp_win2_lat. The first and second delay signals fp_win1_lat and fp_win2_lat respectively output from the first flip-flop 20 and the second flip-flop 21 are ANDed by the first AND gate 30 to perform a first pulse ( first_pulse) is output.

The third to sixth flip-flops 22 to 25 will be described with reference to FIG. 11. As illustrated in FIG. 11, the third flip-flop 22 latches the third signal mp_win1 by td3 according to the delay clock signal td3_clk and outputs a third delay signal mp_win1_lat. The fourth flip-flop 23 latches the third signal mp_win1 for one period according to the clock signal ref_clk to output the fourth delay signal mp_win2_lat. The third delay signal mp_win1_lat, the fourth delay signal mp_win2_lat, and the delayed signal nrzi_ref are respectively inputted to the second AND gate 31 to perform an AND operation when the delayed signal nrzi_ref is 1, thereby multiplying the multipulse. Generate.

The fifth flip-flop 24 latches the fourth signal mp_win3 by td3 according to the delay clock signal td3_clk to output the fifth delay signal mp_win3_lat. The sixth flip-flop 25 latches the first signal mp_win3 for one period according to the clock signal ref_clk to output the sixth delay signal mp_win4_lat. The fifth delayed signal (mp_win3_lat), the sixth delayed signal (mp_win4_lat), and the delayed signal (nrzi_ref) are input to the third AND gate 32, respectively, and are ANDed when the delayed signal nrzi_ref is 1 to generate multipulse. Let's do it.

One multi-pulse is completed by adding the output of the second AND gate 31 and the output of the third AND gate 32.

Accordingly, a write pulse WRPULSE is generated by ORing each output of the first AND gate 30, the second AND gate 31, and the third AND gate 32 using the OR gate 40. That is, the first pulse of the write pulse is generated by the first AND gate 30, and the multi-pulse is generated by the second and third AND gates 31 and 32.

Next, the seventh flip-flop 26 and the eighth flip-flop 27 will be described with reference to FIG. 12. As illustrated in FIG. 12, the seventh flip-flop 26 latches the fifth signal ep_win1 by td1 according to the delay clock signal td1_clk and outputs the seventh delay signal ep_win1_lat. The eighth flip-flop 27 latches the sixth signal ep_win2 by td4 according to the delay clock signal td4_clk to output the eighth delay signal ep_win2_lat.

The seventh delay signal ep_win1_lat and the eighth delay signal ep_win2_lat are NAND-operated by the NAND gate 33 to generate an erase pulse ERPULSE.

As such, a timing diagram showing each pulse as one is shown in FIG. 13. As shown in Fig. 13, by appropriately determining the time delay data td1, td2, td3, and td4, an optimal recording pulse can be generated within the mark range. These time delay data are set in advance to have the best jitter characteristics through experiments.

Accordingly, the present invention outputs the time delay data according to an address value determined by combining the length of the mark and the space from the NRZI signal, thereby delaying the window signal generated within the mark range from the NRZI signal by this time delay data. A precise recording pulse can be generated.

As described above, according to the recording pulse generator of the present invention, the recording characteristics can be improved by precisely controlling the start and the end of the recording pulse according to the pattern of the NRZI signal based on the preset time delay data. .

Claims (10)

A recording pulse generator for recording data on a recording medium, An NRZI pattern analyzer for counting the lengths of marks and spaces in the NRZI signal, and outputting an address value determined by combining the counted values, respectively, and outputting an NRZI signal obtained by delaying the NRZI signal for a predetermined time; A window signal generator for outputting a plurality of window signals for producing a write pulse using the delayed NRZI signal, and for outputting a plurality of window signals for producing an erase pulse; A memory in which time delay data according to a plurality of address values is stored in a table so that time delay data corresponding to an address value output from the NRZI pattern analyzer is output; A time delay signal selector for respectively selecting delay clock signals corresponding to time delay data output from the memory corresponding to the address value among a plurality of delay clock signals having different clock delays; And A pulse generator for latching a plurality of window signals output from the window signal generator in accordance with the delay clock signals selected by the time delay signal selector, and then combining the latched signals to generate a write pulse and an erase pulse; Recording pulse generating device comprising a. The recording pulse generating apparatus of claim 1, wherein the delayed NRZI signal is the same as the NRZI signal before the length of the mark and the space is delayed. The recording pulse generating apparatus of claim 1, wherein the recording pulse comprises a first pulse and a multi-pulse. The method of claim 1, wherein the time delay data comprises: First time delay data for determining the rising edge of the first pulse, second time delay data for determining the falling edge of the first pulse, and third time delay data for determining the width of the multi-pulse. Time delay data for generating a recording pulse; Time delay data for erasing pulse generation to determine the rising edge of the erase pulse Recording pulse generating device, characterized in that divided into. The recording pulse generation time delay data is selected and output when the address value is determined by a combination of a count value for the length of the mark and a count value for the space before the mark. Recording pulse generator. The erasure generation time delay data is selected and output when the address value is determined by a combination of a count value for the length of the mark and a count value for the space after the mark. Recording pulse generator. The method of claim 1, wherein the plurality of window signals for generating the recording pulse, A first signal synchronized with the delayed NRZI signal in a section 1 to generate a pulse having a predetermined width; A second signal for generating a pulse having a predetermined width one cycle before the delayed NRZI signal is 1; A third signal for generating a pulse every even period in the interval where the delayed NRZI signal is 1; And a fourth signal for generating a pulse for delaying the third signal by one period in a section in which the delayed NRZI signal is one. The method of claim 1, wherein the plurality of window signals for generating the erase pulse, A fifth signal generating the same waveform as the delayed NRZI signal; And a sixth signal generated one cycle before the same waveform as the NRZI signal. The method of claim 1, wherein the time delay signal selector, A phase controller for generating a plurality of delayed clock signals with different time delays of the clock signals; And  A multiplexer for selecting and outputting the plurality of delayed clock signals using the time delay data Recording pulse generating device comprising a. The method of claim 1, wherein the pulse generator, A plurality of flip-flops each latching the first to sixth signals; A plurality of AND gates for ANDing each of the first to fourth signals latched in the flip-flop; An OR gate for ORing the first to fourth signals calculated at the AND gate; And A NAND gate performing NAND operation on the fifth and sixth signals latched in the flip-flop to generate an erase pulse Recording pulse generating device comprising a.

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