JP3737023B2 - Pulse width control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pulse width control circuit that corrects an EFM signal when data is written to a recordable optical disk, and a disk recording apparatus in which the recording timing of pit marks can be adjusted using the pulse width control circuit.
[0002]
[Prior art]
In a recordable optical disc, data that is EFM-modulated is used when data is written. This write data is called an EFM signal and is a signal synchronized with the channel clock. The channel clock is 4.3218 MHz at the standard speed, 8.6436 MHz at the double speed, and 34.5744 MHz at the 8 speed.
[0003]
The EFM signal is formed with a pit pattern of 3 to 11T (1T is one channel clock), but even if the 3 to 11T write pulse is irradiated as it is, the signal recorded on the disc is read as a good quality signal during playback. I can't put it out.
[0004]
For this reason, it is possible to obtain a reproduction signal having an optimum quality by irradiating the light pulse of 3 to 11T after correcting the light pulse by the write strategy described in the so-called orange book.
[0005]
In addition, since the recording state changes when the type of media on which data is recorded and the rotational speed of the disc are different, it is necessary to perform write strategy correction corresponding to each. For each, it is necessary to delay the leading edge of the EFM signal by an appropriate amount, shorten the pulse width, and make the pit mark on the medium appropriate.
[0006]
In general, as a method of realizing write strategy correction for an EFM signal, there is a method of generating a strategy clock that is a clock faster than the channel clock and delay-shifting the EFM signal by a D flip-flop that operates based on this strategy clock. As the strategy clock, n times the channel clock is often used. If n = 8, the strategy clock is 8 times the channel clock and the resolution is 1/8. Further, if both edges of the strategy clock are used, control can be performed at 1/16. When the writing speed is 8 ×, the channel clock is 34.5744 MHz, and the strategy clock is 276.5952 MHz.
[0007]
However, when the writing speed is increased, the channel clock cycle is shortened, and the error in recording state becomes large. Therefore, it is necessary to control the write strategy correction with high resolution. In order to realize this, a higher speed clock may be used as a strategy clock. However, when a higher speed clock is used, the circuit scale increases due to an increase in the number of shift stages by D flip-flops and an increase in select circuits. In addition, the power consumption is increased due to the use of a high-speed clock.
[0008]
Japanese Patent Laid-Open No. 11-273253 proposes a method for realizing high-accuracy pulse width control without using a high-speed clock for strategy correction of the EFM signal.
[0009]
This method realizes a resolution below the channel clock by using a plurality of stages of delay cells, and the resolution is determined by the number of stages used. For example, when 16 stages are used, the resolution is 1 / 16T. However, in this case, it is necessary to increase the number of stages of delay cells in order to increase the resolution, and the circuit scale increases.
[0010]
[Problems to be solved by the invention]
Further, the duty of the strategy clock is more likely to collapse as the cycle becomes shorter (high-speed writing). In this case, the method using both edges of the strategy clock has a problem that the write strategy correction cannot be applied to the EFM signal at equal intervals.
[0011]
Furthermore, in order to appropriately perform the write strategy correction according to various recording states, it is necessary to be able to individually set the strategy amount for each pit length of 3T to 11T of the EFM signal. It is also necessary to be able to change the strategy amount depending on the space length before and after the pit.
[0012]
The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to realize highly accurate pulse width control with a simple circuit configuration. That is, it is an object to control the write strategy with a resolution that is twice that which can be realized with a circuit that uses only a strategy clock.
[0013]
[Means for Solving the Problems]
According to the present invention, a first delay circuit that delays an EFM signal for a predetermined period according to a strategy clock that is n times a channel clock (where n is a positive integer) , and an output signal from the first delay circuit that Write strategy correction amount information by inputting a second delay circuit for delaying corresponding to a delay time of ¼ period, an output signal from the first delay circuit, and an output signal from the second delay circuit. And a selection circuit that selects and outputs one of them according to the above.
[0014]
As described above, a combination of the first delay circuit that delays the strategy clock for a predetermined time and the second delay circuit that has a delay time corresponding to 1/4 cycle of the strategy clock realizes the circuit using only the strategy clock. The write strategy can be controlled with a resolution that is twice as high as possible.
[0015]
According to the present invention, the first delay circuit includes a first D flip-flop that operates at the rising edge of the strategy clock, a second D flip-flop that operates at the falling edge of the strategy clock, and the first and second And a selection circuit that inputs an output signal from two D flip-flops and selects and outputs one of the signals in accordance with the information of the write strategy correction amount.
[0016]
In the present invention, the write strategy correction amount information is generated for 3T to 11T pits or spaces of the EFM signal.
[0017]
By configuring as described above, the second delay circuit can be controlled for the 3T to 11T pits or spaces of the EFM signal. This is because a select signal for controlling a delay cell can be obtained with the same configuration and method as a circuit that achieves high resolution only with a conventional strategy clock, and the strategy correction amount is set for each pit or space length. Since it can be set, an appropriate EFM signal can be recorded.
[0018]
Further, the present invention is characterized in that the second delay circuit delay amount corresponding to a plurality of writing speed is configured to be selected, it may be configured to select the delay amount in accordance with the writing speed.
[0019]
As described above, by making the delay amount of the second delay circuit selectable, it becomes possible to set an appropriate delay amount (quarter cycle of the strategy clock) according to the writing speed. That is, when the writing speed is different, the strategy clock, which is n times the channel clock, changes as the channel clock changes. Therefore, by selecting a plurality of delay amounts of the delay cells, it is possible to select an appropriate delay amount with respect to the writing speed.
[0020]
Further, according to the present invention, the second delay circuit is configured to be able to select a delay amount of 1/4, 2/4, 3/4 period of the strategy clock, and the first delay circuit is configured at the rising edge of the strategy clock. It can be composed of a first D flip-flop that operates.
[0021]
By selecting a delay amount of 2/4 period of the strategy clock, it is not necessary to use a D flip-flop that operates at the falling edge of the strategy clock, and the above problem can be avoided.
[0022]
Further, the disk recording apparatus of the present invention comprises any one of the pulse width control circuits described above, and a selection signal corresponding to the type of media and / or the rotation speed is given to the selection circuit and corresponds to the EFM signal. The present invention is characterized in that an output signal is sent to a recording device for recording pit marks on a disc so that the recording timing of the pit marks can be adjusted.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a pulse width control circuit of the present invention. The present invention controls a write strategy with high resolution using a strategy clock and a delay circuit.
[0024]
The EFM signal synchronized with the channel clock becomes an EFM signal delayed by a setting amount expected by a shift circuit composed of a D flip-flop (not shown) that operates at the rising edge of the strategy clock. The EFM signal is shown in FIG. This is applied to the pulse width control circuit of the present invention. The EFM signal is input as data of the D flip-flop 11 as a first delay circuit that operates at the rising edge of the strategy clock.
[0025]
The input EFM signal is latched as data of the D flip-flop 11 that operates at the rising edge of the strategy clock. The signal (a) output from the D flip-flop 11 is supplied to the D flip-flop 12 as the first delay circuit that operates at the falling edge of the strategy clock and also to the selector 13. The output (b) from the D flip-flop 12 is also given to the selector 13.
[0026]
The outputs of both the D flip-flop 11 operating at the rising edge and the D flip-flop 12 operating at the falling edge are input to the selector 13. As will be described later, the selector 13 selects one output from a select signal SEL1 based on the information on the write strategy correction amount. The output (c) of the selector 13 is then divided into a path that does not pass through the delay circuit 14 as the second delay circuit and a path that does not pass through the path, and signals (c) and (d) that pass through both paths are input to the selector 15. The This delay circuit 14 has a delay time of a quarter cycle of the strategy clock. As will be described later, the selector 15 selects one output from the signal SEL0 based on the write strategy correction amount information, and outputs a signal (e).
[0027]
The signals having different strategy amounts are selected by the select signals SEL0 and SEL1 of the selectors 13 and 14, respectively. When SEL1 is “0”, the selector 13 selects and outputs the signal (a) of the D flip-flop 11, and when SEL1 is “1”, the selector 13 outputs the signal (b) of the D flip-flop 12. ) Is selected and output. Further, when SEL0 is “0”, the selector 15 selects and outputs the signal (c) of the selector 13, and when SEL0 is “1”, the selector 15 outputs the signal (d) of the delay circuit 14. Select to output. Thus, the waveform output by the combination of the selectors 13 and 15 is as shown in FIG. 2, and it can be seen that the resolution is doubled by using the delay circuit 14.
[0028]
Here, it is assumed that the strategy clock is eight times the channel clock and the strategy correction for the current pit is applied by the previous space length and the current pit length. The strategy correction amount can be set for each pit / space length. When the previous space length is 4T and the current pit length is 5T, the strategy correction amount for these lengths is 3 / 32T, If the setting of / 32T is given, the total strategy setting amount is 7 / 32T.
[0029]
When the setting value is given as shown in FIG. 3, the circuit for calculating the strategy setting amount inside the circuit takes the sum of the binary numbers and is as follows.
0011 + 0100 = 0111
[0030]
This means that the lower 2 bits are the select signals of SEL1 and SEL0, respectively, and the select signal can be easily obtained.
[0031]
As a conventional method, when only the strategy clock is used, the least significant bit of the strategy setting value and the selector 15 can be omitted, and the circuit configuration remains as it is. By combining the delay circuit 14 in this manner, the resolution can be doubled by adding a few circuits while maintaining the same circuit configuration as when the circuit is configured only with the conventional strategy clock.
[0032]
If it is desired to correct the write strategy for the trailing edge of the EFM signal, another circuit similar to that shown in FIG. 1 is prepared, and the final EFM signal is obtained by ANDing or ORing both corrected EFM signals. be able to.
[0033]
FIG. 4 shows an embodiment of a delay circuit 14 as a second delay circuit . The delay circuit 14 can take a delay amount of a quarter cycle of the strategy clock. However, since the strategy clock changes in accordance with the writing speed, it is necessary to be able to set the delay quantity in accordance with each speed. . Here, the delay circuit 14 has delay elements 141 to 14n having a delay amount in accordance with each speed. The path of the delay circuit is selected by the selector circuit 14a according to the select signal given by the register, and an appropriate delay amount can be taken.
[0034]
In consideration of the case where the duty of the strategy clock is lost, it is preferable to correct the delay amount at each of the above double speeds.
[0035]
In addition, a configuration in which the delay amount slightly increases as a path inside the delay circuit 14 (for example, the delay amount increases in increments of 0.15n by the select signal), and a necessary delay amount is selected at each double speed. It can also be configured to do.
[0036]
If the delay amount of 2/4 or 3/4 cycle of the strategy clock can be selected, a simple circuit change is sufficient if SEL1 and SEL0 in FIG. 1 are used as select signals. In this case, since it is not necessary to use a D flip-flop that operates at the falling edge of the strategy clock, it is not necessary to worry about the duty of the strategy clock.
[0037]
Next, an example in which the pulse width control circuit described above is applied to a CD-R disc recording control circuit will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of the entire CD-R disc recording apparatus. Data to be written on the disc 50 is first modulated into an EFM signal by the EFM encoder 51, and the pulse width control circuit shown in FIG. 52 is supplied together with the strategy clock. The disk recording control circuit 54 includes the pulse width control circuit 52, a register 53, and an arithmetic circuit 54a. An output signal of the pulse width control circuit 52 is supplied to a laser device 55 such as a laser pickup, and the disk corresponds to an EFM signal. A pit mark is recorded. Further, information indicating the media type and rotation speed of the disc to be used is input to the microcomputer 56 that controls the entire disk recording apparatus, and the table 57 connected to the microcomputer 56 indicates the media type and rotation speed, respectively. Correspondingly, the rising delay amount and the falling delay amount are stored in advance.
[0038]
When the media type and the rotation speed are specified, the microcomputer reads the corresponding rising and falling delay amounts from the table and sets the numerical values in the register 53. The arithmetic circuit 54 a outputs select signals SEL 0, 1, etc. to the pulse width control circuit 52 based on the delay amount set in the register 53.
[0039]
Therefore, in the pulse width control circuit 52, the pulse width of the EFM signal input as described above is controlled to a desired pulse width by SEL0, 1, and the signal whose pulse width is controlled is controlled to a desired phase. Can do. Since this output signal is sent to the laser device 55, the laser device 55 adjusts the recording timing of the EFM signal according to the type and rotation speed of the medium, and records an appropriate pit mark.
[0040]
【The invention's effect】
As described above, the present invention provides a circuit configuration by combining the first delay circuit that delays the strategy clock for a predetermined time and the second delay circuit that has a delay amount corresponding to a quarter period of the strategy clock. The write strategy correction can be applied to the EFM signal with a resolution that is double the resolution realized only by the strategy clock without greatly changing the circuit scale.
[0041]
Further, according to the present invention, the control of the second delay circuit can be controlled for the 3T to 11T pits or spaces of the EFM signal. This is because a select signal for controlling a delay cell can be obtained with the same configuration and method as a circuit that achieves high resolution only with a conventional strategy clock, and the strategy correction amount is set for each pit or space length. Since it can be set, an appropriate EFM signal can be recorded.
[0042]
In the present invention, the delay amount of the second delay circuit can be changed by the selector circuit, and the selector signal can be set by the register, so that an appropriate delay amount according to the writing speed (1/1 of the strategy clock) is set. 4 cycles) can be set.
[0043]
Furthermore, since the second delay circuit can be used in place of the D flip-flop operating at the falling edge of the strategy clock, no problem occurs even if the duty of the strategy clock is lost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a pulse width control circuit of the present invention.
FIG. 2 is a timing chart in this embodiment.
FIG. 3 is a diagram illustrating a definition example of a setting value of a strategy correction amount.
FIG. 4 is a block diagram showing an embodiment of a delay circuit according to the present invention.
FIG. 5 is a block diagram showing an example in which the pulse width control circuit of the present invention is applied to a CD-R disc recording control circuit.
[Explanation of symbols]
11 D flip-flop 12 D flip-flop 13 Selector 14 Delay circuit 15 Selector

Claims (6)

A first delay circuit that delays the EFM signal for a predetermined period according to a strategy clock that is n (where n is a positive integer) times the channel clock, and an output signal from the first delay circuit is a quarter cycle of the strategy clock A delay circuit corresponding to the delay time of the first delay circuit , an output signal from the first delay circuit, and an output signal from the second delay circuit are input in accordance with the information on the write strategy correction amount. A pulse width control circuit comprising: a selection circuit that selects and outputs one of the two. The first delay circuit includes a first D flip-flop that operates at the rising edge of the strategy clock, a second D flip-flop that operates at the falling edge of the strategy clock, and the first and second D flip-flops. 2. A pulse width control circuit according to claim 1, further comprising: a selection circuit that receives the output signal and selects and outputs one of the output signals according to the write strategy correction amount information.   3. The pulse width control circuit according to claim 1, wherein the write strategy correction amount information is generated for 3T to 11T pits or spaces of an EFM signal. It said second delay circuit is a delay amount corresponding to a plurality of writing speed is configured to be selected, according to claim 1 to 3, characterized in that the delay amount in accordance with the write speed is selected according to any one Pulse width control circuit. It said second delay circuit is a delay of 1 / 4,2 / 4,3 / 4 cycle strategies clock is configured to be selected, said first delay circuits includes a first operating at the rise of the strategy clock The pulse width control circuit according to claim 1, comprising: a D flip-flop.   6. A pulse width control circuit according to claim 1, wherein a selection signal corresponding to the type and / or rotation speed of a medium is given to the selection circuit, and a pit mark corresponding to the EFM signal is recorded on the disc. A disc recording apparatus characterized in that an output signal is sent to a recording apparatus for adjusting the recording timing of pit marks.

Images