KR100534661B1 - Device of Control Pulse Generation for Optical Disc and The Method - Google Patents

Abstract

The present invention provides a signal pattern analyzer for receiving a signal of a predetermined format required for a disc to be recorded, counting marks and space lengths, specifying an address of a memory from the combination thereof, and delaying the signal to be recorded for a predetermined time and outputting the signal; A memory unit having a delay time value determined according to a combination of a mark and a space length, and outputting a delay time value of a designated address from the signal pattern analyzer; A window signal generator which receives a signal output from the signal pattern analyzer and a delay time value output from a memory and generates predetermined window signals for generating a recording pulse string having a plurality of pulses at a mark of an input signal; A delay clock generation unit receiving the delay time value and generating a delay clock for latching each window signal; And a pulse generator for latching each of the window signals according to the input delay clock and combining the window signals to output a control pulse and a method of generating the control pulse.

Description

Device and control pulse generation device for optical disc {Device of Control Pulse Generation for Optical Disc and The Method}

The present invention relates to an optical disk control pulse generating apparatus, and more particularly, to start and stop recording pulses to suppress distortion of recording marks due to thermal interference in order to generate accurate recording marks when recording data on a phase conversion disk. The present invention relates to a control pulse generator capable of efficiently controlling the end time.

The recording and reproducing apparatus of the optical disc records data on the optical disc and reproduces the recorded disc. The recording format is currently recorded on a disc in CD (R or RW) format or DVD (-R, + R, -RW, + RW, etc.) format.

Conventionally, when recording predetermined data onto a disc using an optical disc recording and reproducing apparatus, a method of recording a new signal while erasing an existing signal by modulating laser power between two powers, a recording level and an erasing level, has been used. However, the above recording method has a problem in that the recording mark shape is deformed into a teardrop shape rather than symmetry before and after recording. In the case of recording this as a signal waveform, the arrival temperature of the recording film is shown to be low at the leading end and higher as the closer to the end due to the thermal effect. Such deformation of the recording mark is connected to the reproduction waveform deformation, which causes an increase in jitter. As a means to solve this problem, Japanese Patent Laid-Open No. 63-266632 and Japanese Patent Laid-Open No. 63-279431 have been proposed.

Japanese Patent Laid-Open Nos. 63-266632 and 63-279431 disclose that recording waveforms for forming one recording mark are formed by a pulse train consisting of short pulses of the same shape to reduce the shape deformation of the recording mark. I suggest that.

However, according to the conventional technique as described above, when recording data on the phase conversion disk, the time of the start and end of the recording pulse can be efficiently controlled to suppress the distortion of the recording mark due to thermal interference in order to generate accurate recording marks. It is very difficult to control.

SUMMARY OF THE INVENTION The present invention has been made to overcome the limitations of the prior art, and its object is to record to suppress distortion of recording marks due to thermal interference in order to generate accurate recording marks when recording data on a phase conversion disk. The present invention provides a recording pulse generator capable of efficiently controlling the time of start and end of a pulse.

Another object of the present invention includes a window signal generator further comprising a window signal delay unit for delaying window signals according to at least two clock signals according to an input delay time value to output a setup time and / or a hold time violation. An optical disk recording pulse generating device is provided.

It is another object of the present invention to efficiently control the start and end times of recording pulses to suppress distortion of recording marks due to thermal interference in order to generate accurate recording marks when recording data on a phase conversion disk. It is to provide a recording pulse generation method.

In order to achieve the above object, the present invention receives a signal of a predetermined format required for a disc to be recorded, counts a mark and a space length, specifies a memory address from a combination thereof, and delays the signal to be recorded for a predetermined time. An output signal pattern analyzer; A memory unit having a delay time value determined according to a combination of a mark and a space length, and outputting a delay time value of a designated address from the signal pattern analyzer; A window signal generator which receives a signal output from the signal pattern analyzer and a delay time value output from a memory and generates predetermined window signals for generating a recording pulse string having a plurality of pulses at a mark of an input signal; A delay clock generation unit receiving the delay time value and generating a delay clock for latching each window signal; And a pulse generator for latching each of the window signals according to the input delay clock and combining the window signals to output a control pulse.

The present invention preferably provides an optical disc control pulse generating apparatus including a window signal generator further comprising a window signal delay unit for delaying and outputting window signals according to at least two clock signals according to an input delay time value.

The present invention preferably provides an optical disc control pulse generating apparatus, characterized in that the signal input to the signal pattern analyzer is a signal of NRZI data format.

The present invention comprises the steps of: receiving a signal of a predetermined format required for a disc to be recorded, counting marks and space lengths, and addressing a memory from a combination thereof; Reading out the delay time value determined from a combination of a mark and a space length from a memory; Generating predetermined window signals for generating a recording pulse string having a carpenter pulse at a mark of an input signal from the delay time value and an input signal; Generating a delay clock for latching each window signal from the delay time value; And latching each of the window signals according to a delay clock and combining the window signals to output a control pulse.

The present invention preferably provides a method for generating an optical disc control pulse, wherein the window signals are delayed according to at least two clock signals according to a delay time value.

The present invention preferably provides a method for generating an optical disc control pulse, wherein the input signal is a signal of an NRZI data format.

The present invention preferably provides a method for generating an optical disc control pulse, wherein the pulse width of the head pulse of the recording pulse string is larger than the pulse width of each pulse of the subsequent pulse string.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

1 shows a block diagram of an optical disc recording and reproducing apparatus. Referring to FIG. 1, data to be recorded is received from a host, converted into a format required for a disc to be recorded by the recording DSP 1, and output to the control pulse generating apparatus 2. After generating the control pulse in the control pulse generator 2, the control pulse is input to an LD driver (Laser Diode Driver) (3). The output of the LD driver 3 is input to a pick up 4, and the pick-up 4 irradiates a laser light to the disk. Data is recorded on the disc by turning on and off the laser light according to the data to be recorded. When reproducing data from the disc, the laser reflected light according to the length of the mark and the space of the disc is amplified by the RF amplifier 5, equalized, and converted into digital data of a certain form. 6). The playback DSP 6 decodes the data of the disc in accordance with the format of the disc and outputs it to the host.

The control pulse generator 2 according to the present invention receives the data to be recorded on the disc from the recording DSP 1 in a predetermined format and outputs the control pulse to the LD driver 3. The role of the control pulse generating device 2 is to control the laser beam to be output by delaying the laser light for a predetermined time from the reference time point in accordance with conditions so as to improve the disc recording characteristics when the pickup outputs the laser light to the disc. This is called a write strategy (also called a pattern adaptive recording method).

As shown in FIG. 2, the control pulse generator 2 according to the present invention generates the input signal as a write pulse (indicated by WRPULSE) and an erase pulse (indicated by ERPULSE) to control the LD driver 3. The waveform output from the LD driver 3 to the pickup 4 is an LD power signal of FIG. 2 and is composed of three levels. That is, the recording power P _o recorded on the disc, the erase power P _e for erasing the disc, and playback power P _b for reproduction. In order to produce such a LD power signal, the control pulse generator 2 outputs two control signals, a recording pulse and an erase pulse, to the LD driver 3, and the LD driver 3 has a write pulse of 1 and erases the signal. When the pulse is 0, the recording power (Po) signal is output.When the recording pulse is 0, when the erasing pulse is 0, the reproduction power (Pb) is used, and when the recording pulse is 0 and the erasing pulse is 1, the erasing power (Pe) is output. Output to pickup 4. The recording strategy is to control the positions of each rising edge and falling edge of the recording pulse and the erasing pulse corresponding to the length of the mark and the space.

The purpose of the recording strategy is to produce an accurate recording mark by suppressing distortion of the recording mark due to thermal interference when recording data on the phase change disk. In high-density optical disc recording, recording interference occurs in which mark edges move depending on conditions before and after recording. Therefore, a pattern (or mark) adaptive recording compensation scheme has been proposed to prevent degradation of the recording signal. In order to reduce the distortion of the mark recorded on the disk, a multi-pulse waveform is formed by the length of the recording mark, and the edge position of the recording pulse is changed in correspondence with the space length before and after the recording mark. The principle of this is that when the space in front of the mark to be recorded is short, the mark edge to be recorded increases due to the influence of heat when recording the previous mark, and in order to correct this, the start position of the recording pulse is delayed before recording. Determine the position of the mark edge. If the space before the mark to be recorded is long, the influence of heat when recording the preceding mark is reduced, so the position of the recording mark edge is set by pulling forward the start position of the pulse to be recorded in advance. The correction amount depends on the space length before or after the mark to be recorded and the length of the mark to be recorded.

In the present invention, as shown in Fig. 2, in order to delay the LD power signal, the mark length of a predetermined signal which attempts to record the position of the rising edge of the first pulse of the recording pulse and the position of the falling edge of the leading pulse on the current disk. And the previous space length are combined to determine the delayed value according to the combination condition. In the multipulse string of the recording pulses, the width of the pulse is determined according to the mark length of the signal to be recorded. The position of the rising edge of the erase pulse is the same as the position of the rising edge of the head pulse of the recording pulse, and the position of the falling edge is determined by the combination of the mark length of the signal to be written to the disc and the length of the space behind it. The time delay values of the rising and falling edge positions of the recording and erasing pulses can be obtained experimentally. In other words, by performing a number of recording experiments on a disk, the time delay value can be obtained by obtaining the (smallest jitter) experimental value having the best jitter characteristic. In FIG. 2, td1 is a position value of the rising edge of the first pulse, and td2 is a position value of the falling edge of the first pulse. td3 is the length of the multi-pulse. The falling edge of the multi-pulse is in phase with the rising edge of the reference clock signal ref_clk and controls the length of the multi-pulse by changing the position of the rising edge. td4 represents a value that makes the erase pulse 1 after a certain time from the polling edge of the multi-pulse.

3 is a block diagram of a control pulse generator as a preferred embodiment according to the present invention. The apparatus of the present invention includes an input signal pattern analyzer 10, a window signal generator 11, a pulse generator 12, a memory unit 13 for implementing a write strategy, a delay clock generator 14 and a microcomputer interface ( 15).

Hereinafter, the signal input to the signal pattern analyzer will be described using the NRZI format as an example. A control for controlling write power, erase power, and read power to the LD driver 3 by receiving a signal corresponding to the format of each disc from the recording DSP 1 in the NRZI format. Output a pulse. The NRZI pattern analyzer 10 analyzes the length of the mark and space of the NRZI to determine the address of the write strategy memory unit (RAM) 13, and the memory unit 13 is a data having a time delay value. The td1, td2, td3, and td4 values are outputted to the delay clock generation unit 14. The window signal generator 11 also outputs a window signal corresponding to the size of the mark to be recorded to the pulse generator 12. The pulse generator 12 latches each window signal output from the window signal generator 11 according to a latch clock output from the delay clock generator 14 and passes through a gate to generate a write pulse string. Hereinafter, the function of each device will be described in more detail.

The NRZI pattern analyzer 10 counts the lengths of marks and spaces from the input NRZI signal. The address of the memory unit 13 is determined by combining a mark_count that counts the length of the mark to be written and a space count that counts the length of the preceding space. The data of the memory unit 13 is composed of five bits td1, td2, td3, and td4, respectively. td1 is delay time data for determining the rising edge of the head pulse of the recording pulse among the control pulses, and td2 is delay time data for determining the polling edge of the head pulse. And td3 is data for determining the width of the subsequent pulse train. Finally, td4 is data that determines the delay time of the erase pulse among the control pulses. At this time, preferably, the pulse width of the head pulse is larger than the pulse width of each pulse of the subsequent pulse string, which is effective in reducing deformation of the recording mark.

The delay time data td1, td2, td3, and td4 stored in the memory unit 13 are loaded using the microcomputer interface 15. The delay time data can be determined experimentally, and the determined time delay data is stored in the memory in advance by the microcomputer interface 15 before writing to the disk. In addition, the NRZI pattern analyzer 10 preferably outputs NRZI, which is an input signal, with a delay for a predetermined period of time. (Delayed signal is indicated by nrzi_ref). The reason for delaying the NRZI for a certain period is to synchronize the NRZI signal with the address output from the pattern analyzer 10. That is, the window signal generator 11 can generate the window signal for each pulse by delaying and outputting the NRZI signal at a time when the address is output.

4 shows a window signal generator 11 according to the invention. The window signal generator 11 receives the delay signal nzri_ref and the delay time data td1 to td4 and generates a window signal for generating a recording pulse string in a state where the delay signal is 1 (mark). The window signal generator 11 is preferably implemented to be divided into two parts functionally. One is a combinational logic circuit 21 for generating a plurality of window signals for generating a recording pulse string, and the other is a signal of two clocks (clock 1) according to the delay time value of the signals from the combinational logic circuit 21. It can be implemented as the window signal delay circuit unit 22 which delays and outputs a half clock, one clock or one clock half using the clock 2). The output signals of the window signal delay circuit section 22 are input to the pulse generator 12 and output as a control pulse which is the final output.

10 shows timing diagrams for two window signals (fp_win1 for generating a rising edge and fp_win2 for generating a falling edge) for generating a leading pulse among recording pulse sequences, and in FIG. 11 and FIG. 12, subsequent pulses in the recording pulse sequence, respectively. A timing diagram of two window signals mp_win1 and mp_win2 for generating an in-multipulse and two window signals ep_win1 and ep_win2 for generating an erase pulse among control pulses are shown.

The window signal delay circuit section 22 preferably delays the output of the combined logic circuit section 21 in accordance with the delay time value. This is because when the pulse generator 12 latches the output signal of the window signal generator 11 by using the latch clocks td1_clk, td2_clk, td3_clk, and td4_clk according to the delay time value, the window signal generator 11 If the output signal and latch clock signal are in phase or the time difference is less than margin of setup time or hold time, the setup time or hold time violation is eliminated.

In FIG. 7, clock 1, clock 2, and reference clock ref_clk are shown. Clock 1 is a half clock delay of the reference clock, and clock 2 is a clock in phase with the reference clock. The combinational logic circuit 21 of the window signal generator 11 outputs the window signals using the reference clock. If the window output signal is output to the pulse generator 12 without passing through the window signal delay circuit 22, There is a possibility of a setup time and hold time violation. As described above, since the window signal fp_win1_1 for generating the rising edge of the leading pulse is made of the reference clock, it is in phase with the reference clock. However, when the signal is selected by the pulse generator 12 as the latch clock (indicated by td1_clk [0]) according to the delay time td1, the start pulse window signal and the latch clock are in phase and a setup time violation occurs. Therefore, in order to avoid this, if the start pulse window signal is delayed by a half clock using the clock 1 signal, the setup time violation can be eliminated.

6 illustrates a specific implementation of the window signal delay circuit unit 22 according to the present invention. The first pulse window signal fp_win1_1 is half-clock delayed using the clock 1 in the D F / F 31, and the clock is delayed by the clock 2 in the D F / F 32 again. Also, the output signal of the D F / F 32 is delayed by one clock half from the original signal by using the D F / F 33. The 3x1 multiplex (denoted as 3-1Mux) 34 selects one of the A, B, and C signals according to the value of td1. If td1 is 0 to 7, the first pulse window signal is latched among the latch clocks corresponding to td1 (indicated as td1_clk [0] to td1_clk [7], respectively). . According to this, in the D F / F 60 (FIG. 9) of the pulse generator 12, there is room for a setup time of at least 1/2 clock. If td1 is from 8 to 23, the first pulse window signal is latched from the latch clocks (td1_clk [8] to td1_clk [23]) corresponding to td1, so that the B signal having delayed the window signal by one clock is selected. According to this, the D F / F 60 of the pulse generator 12 has a setup time of at least 1/4 clock. If td1 is 24 to 31, the first pulse window signal is latched among the latch clocks (denoted by td1_clk [24] to td1_clk [31]) according to td1, so that the C signal having delayed the clock signal by one clock half is selected. . According to this, the D F / F 60 of the pulse generator 12 has a setup time of at least 1/4 clock. The other window signals fp_win2_1, mp_win1_1, mp_win3_1, ep_win1_1, and ep_win2_1 also select signals A, B, and C in the 3x1 multiplexer, respectively, according to the delay time values as described in the head pulse window signal.

8 is a timing diagram for what has been described above. Select T signal from 3x1 multiplexer if Td is 0 ~ 7, select B signal from 3x1 multiplexer if Td is 8 ~ 23, select C signal from 3x1 multiplexer if Td is 24 ~ 31 do.

The recording pulse string among the control pulses can be generated by dividing into two pulses. Pulses are generated by dividing the pulse into the first and subsequent pulses. First, to generate the leading pulse (indicated by first_pulse), a window signal (fp_win1_1) for generating the rising edge of the leading pulse having a length of 2T is delayed by one clock than the output signal (nrzi_ref) of the NRZI pattern analyzer. A polling edge generation window signal fp_win2_1 of the leading pulse having a length of 2T and synchronized with the output signal from the NRZI pattern analyzer is generated.

9 shows a block of pulse generator 12. 9, signals of fp_win1 and fp_win2 are transmitted to the input of the pulse generator 12, and the pulse generator 12 delays the signals fp_win1 and fp_win2 by the latch clocks td1_clk and td2_clk by td1 and td2, respectively. Generates fp_win1_lat and fp_win2_lat signals. The fp_win1 signal is latched by td1_clk for a time delay of td1 in the D F / F 60 to generate fp_win1_lat. In addition, the fp_win2 signal is latched to td2_clk in order to delay the time of td2 in the D F / F 61 to generate fp_win2_lat. A timing diagram for this is shown in FIG. 10. The signal fp_win1_lat latched by the D F / F 60 is transferred to the input of the two input AND gate 70. In addition, the signal fp_win2_lat latched by the D F / F 61 is transferred to the other input of the two-input AND gate 70. The output of the two-input AND gate 70 is generated with a leading pulse as shown in FIG. In other words, a signal obtained by delaying the fp_win1 signal by td1_clk by td1 and a signal by delaying the fp_win2 signal by td2_clk by td2 is generated as a leading pulse by passing through the AND gate 70.

In order to generate a multipulse, which is a subsequent pulse, the window signal generator 11 generates and outputs the mp_win1 and mp_win3 signals, and a timing diagram thereof is shown in FIG. 11. Referring to FIG. 11, the mp_win1 signal is 1 in the second clock period when the output signal of the NRZI pattern analyzer is 1, and becomes 0 in the third clock period. Therefore, the mp_win1 signal becomes 1 only in the even-numbered clock period of the section in which the output signal from the NRZI pattern analyzer is 1, and the rest becomes 0. mp_win2 generates mp_win1 as a delayed signal. The mp2_win signal also generates a pulse only when the output signal from the NRZI pattern analyzer is 1. In the pulse generator 12, the mp_win1 and mp_win3 signals are used as td3_clk and reference clock (ref_clk) using DF / F (62), DF / F (63), DF / F (64) and DF / F (65), respectively. Latch. The mp_win1 signal is delayed by td3_clk by td3 and latched by the D F / F 62 to generate a delay signal mp_win1_lat, which is transmitted to the input of the three-input AND gate 71. The mp_win1 signal is delayed by one clock as a reference clock and latched by the D F / F 63 to generate a delay signal mp_win2_lat and transferred to the other input of the three-input AND gate 71. The output signal from the NRZI pattern analyzer is input to the remaining inputs of the three-input AND gate 71 so that the multi-pulse is generated only when the output signal is one. The mp_win3 signal is delayed by td3_clk by td3 and latched by the D F / F 64 to generate a delay signal mp_win3_lat, which is transmitted to the input of the three-input AND gate 72. Then, the mp_win3 signal is delayed by one clock as a reference clock and latched by the D F / F 65 to generate the delay signal mp_win4_lat and transferred to the other input of the three-input AND gate 72. The output signal from the NRZI pattern analyzer is input to the remaining inputs of the three-input AND gate 72 so that the multi-pulse is generated only when the output signal is one.

As shown in FIG. 11, the O-ring of the delayed signals mp_win1_lat and mp_win2_lat, and the output signal from the NRZI pattern analyzer and the gated signal of the delayed signals mp_win3_lat and mp_win4_lat and the NRZI pattern analyzer are ORed. (Oring) generates a subsequent pulse, multipulse. Finally, the 2-input AND gate 70 output, the 3-input AND gate 71 output, and the 3-input AND gate 72 output are connected to the inputs of the 3-input OR gate 74, respectively, to generate a write pulse string. Description of this is shown in the recording pulse timing diagram of FIG.

In order to generate the erase pulse ERPULSE, the window signals ep_win1 and ep_win2 are generated by the window signal generator 11. The window signal ep_win1 is a signal obtained by delaying the output signal of the NRZI pattern analyzer by one cycle. The window signal ep_win2 is generated with the same waveform as the output signal from the NRZI pattern analyzer. As shown in the pulse generator 12 of FIG. 9, the window signal ep_win1 is delayed and latched by td1_clk by td1 using the D F / F 66, and then a delay signal ep_win1_lat is generated. The window signal ep_win2 is delayed and latched by td4_clk by td1 using the D F / F 67, and then a delay signal ep_win2_lat is generated. ep_win1_lat and ep_win2_lat are delivered to respective inputs of the two-input NAND gate 73 to generate an erase pulse. A timing diagram for this is shown in FIG. 12.

FIG. 13 is a diagram for generating a recording pulse by O-ring the above-described leading pulse and multipulse. In addition, the relationship between the recording pulse and the erasing pulse is shown in FIG.

14 shows a block diagram of the delay clock generator 14. The delay clock generator 14 may be implemented as a DLL (Delay Locked Loop) 80 and a plurality of 32x1 multiplexers. The function of the DLL 80 is to generate several clock signals that are synchronized with the signals from the reference clock signal and have a constant delay. At this time, preferably, the delay amount of each of the multiple clocks is n / N Tw (Tw: clock cycle). That is, if the number of clocks to be output is N, the delay amount of the n th clock is n / N Tw. Figure 13 illustrates this. In the preferred embodiment of the present invention, an example of generating 32 clock signals with respect to the reference clock is shown. As shown in FIG. 15, dll_clk [0] having a phase delay of 1 / 32Tw and dll_clk [1] having a phase delay of 2 / 32Tw and 3 / 32Tw of the phase delay with respect to the reference clock. Dll_clk [2], which has a phase delay of 31 / 32Tw, produces a clock signal dll_clk [31] in phase with the reference clock. In the 32x1 Mux 81, one of the 32 dll_clk [31: 0] is selected by td1 [4: 0] and output to the latch clock td1_clk. In order to delay the rising edge of the leading pulse from the write pulse by td1, td1 is read from the memory 13 and the clock delayed by td1 is selected using the 32x1 MUX 81. By using the selected latch clock td1_clk, the first latch is latched to the D F / F 60 to generate a leading pulse whose delaying edge is delayed by td1. Similarly, in order to delay the falling edge of the leading pulse from the write pulse by td2, td2 is read from the memory 13 and the clock delayed by td2 is selected using the 32x1 MUX 82. By using the selected latch clock td2_clk, the latch is latched to the D F / F 61 to generate a leading pulse whose delaying edge is delayed by td2. In order to delay the polling edge of the multi-pulse in the write pulse string by td3, td3 is read from the memory 13 and the clock delayed by td3 is selected using the 32x1 MUX 83. By using the selected latch clock td3_clk it is latched to the D F / F (62), D F / F (64) to generate a multi-pulse delayed polling edge by td3. Finally, in order to delay the rising edge of the erase pulse by td4, td4 is read from the memory 13 and the clock delayed by td4 is selected using the 32x1 MUX 84. By using the selected latch clock td4_clk, the latch is latched to the D F / F 67 to generate an erase pulse having a rising edge delayed by td4.

According to the present invention, it is possible to efficiently control the time of the start and end of the recording pulse so as to suppress the distortion of the recording mark due to thermal interference when generating data on the phase conversion disk. When the data is recorded on the phase change disk, the recording pulse is changed in accordance with the pattern of the input signal, whereby the recording characteristics can be improved. The present invention is applied to a CD recorder or a DVD recorder to improve recording characteristics.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be appreciated that it can be changed.

1 is a block diagram of a recording / playback apparatus of an optical disc.

2 is an output waveform diagram of a control pulse generator.

3 is a block diagram of a control pulse generator according to the present invention.

4 is a block diagram of a window signal generator according to the present invention.

5 is a detailed block diagram of a window signal generator according to the present invention.

6 is a detailed block diagram of a window signal delay unit constituting the window signal generator according to the present invention.

7 is a timing diagram of a clock for generating a window signal.

8 is a diagram illustrating a relationship between an output timing of a window signal delay unit and a delay time according to the present invention.

9 is a block diagram of a pulse generator according to the present invention.

10 is a timing diagram of a window signal for generating a leading pulse among recording pulse strings according to the present invention.

11 is a timing diagram of a window signal for generating a multipulse string among recording pulse strings according to the present invention.

12 is a timing diagram of a window signal for generating an erase pulse string according to the present invention.

13 is a timing diagram of a control pulse according to the present invention.

14 is a block diagram of a delay clock generation unit according to the present invention.

15 is a timing diagram of a delay clock generation unit according to the present invention.

<Code Description of Main Parts of Drawing>

10: Signal Pattern Analyzer 11: Window Signal Generator

12: pulse generator 13: memory section

14: delay clock generation unit 15: microcomputer interface

Claims (9)

A signal pattern analyzer for receiving a signal of a predetermined format required for a disc to be recorded, counting a mark and a space length, specifying an address of a memory from the combination thereof, and outputting the signal to be recorded with a delay for a predetermined time; A memory unit having a delay time value determined according to a combination of a mark and a space length, and outputting a delay time value of a designated address from the signal pattern analyzer; A window signal generator which receives a signal output from the signal pattern analyzer and a delay time value output from a memory and generates predetermined window signals for generating a recording pulse string having a plurality of pulses at a mark of an input signal; A delay clock generation unit receiving the delay time value and generating a delay clock for latching each window signal; And a pulse generator for latching each window signal according to an input delay clock and combining the window signals to output a control pulse. The apparatus of claim 1, wherein the window signal generator further comprises a window signal delay unit configured to delay and output window signals according to at least two clock signals according to an input delay time value. 3. The optical disc control pulse generator according to claim 2, wherein the clock signal is delayed by a half clock of the reference clock and in phase with the reference clock. The apparatus of claim 1, wherein the signal input to the signal pattern analyzer is a signal of NRZI data format. Receiving a signal of a predetermined format required for the disc to be recorded, counting the mark and the space length, and specifying an address of the memory from the combination thereof; Reading out the delay time value determined from a combination of a mark and a space length from a memory; Generating predetermined window signals for generating a recording pulse string having a carpenter pulse at a mark of an input signal from the delay time value and an input signal; Generating a delay clock for latching each window signal from the delay time value; And latching each window signal according to a delay clock and combining the window signals to output a control pulse. The method of claim 5, wherein the window signals are delayed according to at least two clock signals according to a delay time value. 7. The method of generating an optical disc control pulse according to claim 6, wherein the clock signal is a clock delay delayed by a reference clock and two clocks which are in phase with the reference clock. 6. The method of claim 5, wherein the input signal is a signal of NRZI data format. 6. The method of generating an optical disc control pulse according to claim 5, wherein the pulse width of the head pulse of the recording pulse string is larger than the pulse width of each pulse of the subsequent pulse string.