KR100546183B1 - Micro pattern formation method of semiconductor device - Google Patents
Micro pattern formation method of semiconductor device Download PDFInfo
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- KR100546183B1 KR100546183B1 KR1020030048359A KR20030048359A KR100546183B1 KR 100546183 B1 KR100546183 B1 KR 100546183B1 KR 1020030048359 A KR1020030048359 A KR 1020030048359A KR 20030048359 A KR20030048359 A KR 20030048359A KR 100546183 B1 KR100546183 B1 KR 100546183B1
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- pattern
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- oxide
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 230000007261 regionalization Effects 0.000 title 1
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- 239000005368 silicate glass Substances 0.000 claims description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- VMTCKFAPVIWNOF-UHFFFAOYSA-N methane tetrahydrofluoride Chemical compound C.F.F.F.F VMTCKFAPVIWNOF-UHFFFAOYSA-N 0.000 description 1
- UNRFQJSWBQGLDR-UHFFFAOYSA-N methane trihydrofluoride Chemical compound C.F.F.F UNRFQJSWBQGLDR-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 반도체기판 상부에 폴리실리콘막, 산화막, 질화막 및 포토레지스트막을 순차적으로 형성하는 단계와, 상기 포토레지스트막을 선택적으로 노광 및 현상하여 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 마스크로 하부의 질화막 및 산화막을 식각하여 질화막 패턴 및 산화막 패턴을 형성하는 단계와, 상기 결과물의 산화막 패턴을 선택적으로 식각하여 패턴 크기가 감소된 산화막 패턴을 형성하는 단계와, 상기 결과물로부터 질화막 패턴을 제거하는 단계와, 상기 패턴의 크기가 감소된 산화막 패턴을 식각 마스크로 하부의 폴리실리콘막을 식각하는 단계를 포함하는 반도체소자의 미세패턴 형성방법을 개시한다.The present invention relates to a method for forming a micropattern of a semiconductor device, comprising the steps of sequentially forming a polysilicon film, an oxide film, a nitride film and a photoresist film on a semiconductor substrate, and selectively exposing and developing the photoresist film to form a photoresist pattern. Forming a nitride layer pattern and an oxide layer pattern by etching the lower nitride layer and the oxide layer using the photoresist pattern as an etch mask; and selectively etching the resultant oxide layer pattern to form an oxide layer pattern having a reduced pattern size. A method of forming a fine pattern of a semiconductor device, the method comprising: forming a layer; removing a nitride layer pattern from the resultant; and etching a lower polysilicon layer using an oxide layer pattern having a reduced size of the pattern as an etch mask. .
Description
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체소자의 미세패턴 형성방법을 도시하는 단면도.1A to 1H are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
10 : 반도체기판 12 : 폴리실리콘막10
14 : 산화막 16 : 질화막14
18 : 포토레지스트막 20 : 노광 마스크18
22 : 포토레지스트 패턴 24 : 질화막 패턴22
26 : 산화막 패턴 28 : 게이트라인 패턴26: oxide film pattern 28: gate line pattern
30 : 산화막30: oxide film
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 더욱 상세하게는 포토레지스트 패턴의 하부에 형성되는 산화막 패턴을 선택적으로 식각하여 산화막 패턴의 크기를 감소시킨 후에, 이를 식각 마스크로 사용하여 하부의 폴리실리콘막 을 식각함으로써, 폴리실리콘으로 형성되는 미세화된 게이트라인 패턴을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, by selectively etching the oxide pattern formed on the lower portion of the photoresist pattern to reduce the size of the oxide layer pattern, and using it as an etching mask By etching the polysilicon film, a method for forming a fine gate line pattern formed of polysilicon.
반도체소자 제조공정에서 집적도가 증가하면서 최소 패턴의 크기가 점점 줄어들고 있다. 이때 줄어드는 정도가 현재 사용하고 있는 노광장비의 해상능력 한계를 넘어서고 있어, 보다 작은 미세패턴을 형성하기 위해서는 해상능력이 좋은 짧은 파장의 광원을 갖는 장비를 사용해야만 한다.As the degree of integration increases in the semiconductor device manufacturing process, the size of the minimum pattern is gradually decreasing. At this time, the degree of reduction exceeds the limit of the resolution capability of current exposure equipment, and in order to form a smaller fine pattern, a device having a short wavelength light source having a good resolution capability must be used.
예컨대, I-라인(365nm) 노광 장비의 해상능력 한계가 일반적으로 0.35㎛이기 때문에, 이보다 작은 패턴을 형성하기 위하여 KrF(248nm) 노광 장비를 사용해야 하고, KrF(248nm)의 해상능력 한계가 일반적으로 0.13㎛이기 때문에, 이보다 작은 패턴을 형성하기 위하여 ArF(193nm) 노광 장비를 사용해야 한다.For example, since the resolution limit of I-line (365 nm) exposure equipment is typically 0.35 μm, KrF (248 nm) exposure equipment should be used to form smaller patterns, and the resolution limit of KrF (248 nm) is generally Since it is 0.13 mu m, ArF (193 nm) exposure equipment must be used to form a smaller pattern.
또한, I-라인 포토리소그래피 공정과 비교하여 KrF 포토리소그래피 공정의 원가는 대략 5배 이상이고, KrF 포토리소그래피 공정과 비교하여 ArF 포토리소그래피 공정의 원가는 대략 10배 정도의 차이를 보인다. 이러한 원가의 증가는 현재 어쩔 수 없는 공정 능력상의 한계로 인식되고 있는 실정이다.In addition, the cost of the KrF photolithography process is about 5 times or more compared to the I-line photolithography process, and the cost of the ArF photolithography process is about 10 times that of the KrF photolithography process. Such an increase in cost is currently recognized as an inevitable process capacity limitation.
따라서, 해상능력 한계의 장비를 이용하여 보다 작은 패턴을 형성할 수 있다면 상당한 원가 절감의 효과를 볼 수 있어, 기존의 장비를 최대한 사용하여 해상능력 한계를 넓히려는 연구가 계속적으로 이루어지고 있다.Therefore, if a smaller pattern can be formed by using the equipment of the limit of the resolution, significant cost savings can be obtained, and studies to expand the limit of the resolution by using the existing equipment are continuously conducted.
본 발명의 목적은 ArF 노광장비를 이용하는 것이 아니라 KrF 노광장비를 이용하여 0.13㎛ 이하의 미세 패턴을 형성하는 방법을 제공하는 것이다.An object of the present invention is to provide a method of forming a fine pattern of 0.13㎛ or less by using the KrF exposure equipment, rather than using the ArF exposure equipment.
상기 목적을 달성하기 위하여 본 발명에서는 In the present invention to achieve the above object
(a) 반도체기판 상부에 폴리실리콘막, 산화막, 질화막 및 포토레지스트막을 순차적으로 형성하는 단계;(a) sequentially forming a polysilicon film, an oxide film, a nitride film and a photoresist film on the semiconductor substrate;
(b) 상기 포토레지스트막을 선택적으로 노광 및 현상하여 포토레지스트 패턴을 형성하는 단계;(b) selectively exposing and developing the photoresist film to form a photoresist pattern;
(c) 상기 포토레지스트 패턴을 식각 마스크로 사용하여 하부의 질화막 및 산화막을 식각하여 질화막 패턴 및 산화막 패턴을 형성하는 단계;(c) etching the lower nitride film and the oxide film using the photoresist pattern as an etching mask to form a nitride film pattern and an oxide film pattern;
(d) 상기 결과물의 산화막 패턴을 선택적으로 불산(HF)을 포함하는 용액을 사용하는 습식 방법으로 식각하여 패턴 크기가 감소된 산화막 패턴을 형성하는 단계;(d) etching the resultant oxide pattern by a wet method using a solution containing selectively hydrofluoric acid (HF) to form an oxide pattern having a reduced pattern size;
(e) 상기 결과물로부터 질화막 패턴을 제거하는 단계; 및(e) removing the nitride film pattern from the resultant product; And
(f) 상기 산화막 패턴을 식각 마스크로 사용하여 하부의 폴리실리콘막을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 미세패턴 형성방법을 제공한다.(f) using the oxide film pattern as an etching mask to etch a lower polysilicon film to provide a method of forming a fine pattern of a semiconductor device.
상기 단계를 포함하는 본 발명에 따른 반도체소자의 미세패턴 형성방법에 있어서, 상기 산화막은 BPSG(boron phosphorous silicate glass) 산화막, PSG (phosphorous silicate glass) 산화막, TEOS(tetraethyl ortho silicate) 산화막, PE-TEOS(plasma enhanced-tetraethyl ortho silicate) 산화막, O3-TEOS(O3-tetraethyl ortho silicate) 산화막, HDP(high density plasma) 산화막, APL (advanced planarization layer) 산화막, USG(undoped silicate glass) 산화막 또는 이들의 혼합물로 이루어진 군으로부터 선택되는 것을 특징으로 한다.In the method of forming a fine pattern of a semiconductor device according to the present invention comprising the above step, the oxide film is a BPSG (boron phosphorous silicate glass) oxide film, PSG (phosphorous silicate glass) oxide film, TEOS (tetraethyl ortho silicate) oxide film, PE-TEOS (plasma enhanced-tetraethyl ortho silicate) oxide, O 3 -TEOS (O 3 -tetraethyl ortho silicate) oxide, high density plasma (HDP) oxide, advanced planarization layer (APL) oxide, undoped silicate glass (USG) oxide or their It is characterized in that it is selected from the group consisting of mixtures.
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이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체소자의 미세패턴 형성방법을 도시하는 단면도이다.1A to 1H are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체기판(10) 상부에 폴리실리콘막(12), 산화막(14) 및 질화막(16)을 순차적으로 형성한다.Referring to FIG. 1A, the
이때 폴리실리콘막(12)은 2000 내지 2500Å의 두께로 증착되는 것이 바람직하고, 산화막(14)은 2000 내지 3000Å의 두께로 증착되는 것이 바람직하며, 질화막 (16)은 300 내지 500Å의 두께로 증착되는 것이 바람직하다.In this case, the
또한, 산화막(14)은 BPSG(boron phosphorous silicate glass) 산화막, PSG (phosphorous silicate glass) 산화막, TEOS(tetraethyl ortho silicate) 산화막, PE-TEOS(plasma enhanced-tetraethyl ortho silicate) 산화막, O3-TEOS(O3-tetraethyl ortho silicate) 산화막, HDP(high density plasma) 산화막, APL (advanced planarization layer) 산화막 또는 USG(undoped silicate glass) 산화막인 것이 바람직하다.In addition, the
도 1b를 참조하면, 질화막(16) 상부에 1000 내지 3000Å 두께의 포토레지스트막(18)을 증착한 다음, KrF(248nm)를 노광원으로 하고 노광 마스크(20)를 사용하여 포토레지스트막(18)을 선택적으로 노광함으로써, 노광영역(미도시)을 형성한다.Referring to FIG. 1B, a
이때, 포토레지스트막(18)의 하부에 질화막(16) 및 산화막(14)이 형성되기 때문에 기존의 포토레지스트막(18)만을 형성하여 패턴을 형성시킬 때보다 포토레지스트막(18)의 두께를 작게 할 수 있다.In this case, since the
도 1c를 참조하면, 상기 결과물을 현상하여 상기 노광영역을 제거함으로써 포토레지스트 패턴(22)을 형성한다. 여기서는 포지티브 포토레지스트를 사용하여 패턴을 형성한 경우에 해당하는 것으로, 빛에 의해 노광된 노광영역이 현상공정에 의해 제거되기 때문에 포지티브 타입의 패턴이 형성된 것을 도시한다.Referring to FIG. 1C, a
이때 포토레지스트 패턴(22)은 해상능력 한계가 0.13㎛인 KrF(248nm)를 노광원으로 사용하여 형성하였기 때문에, 0.13㎛ 이상의 크기를 갖는다.At this time, since the
도 1d를 참조하면, 포토레지스트 패턴(22)을 식각 마스크로 사용하여 하부의 질화막(16) 및 산화막(14)을 식각하여 질화막 패턴(24) 및 산화막 패턴(26)을 형성한 다음, 식각 마스크로 사용된 포토레지스트 패턴(22)을 통상의 방법으로 제거한다.Referring to FIG. 1D, the
도 1e를 참조하면, 상기 결과물의 최상부에 위치하는 질화막 패턴(24)은 그대로 두고 산화막 패턴(26)만을 선택적으로 식각하여 패턴 크기가 0.13㎛ 이하로 감소된 산화막 패턴(26)을 형성한다.Referring to FIG. 1E, only the
이때 불산(HF)을 포함하는 용액을 사용하여 습식각 공정을 수행하거나, 삼불화메탄(CHF3) 가스, 사불화메탄(CF4) 가스 또는 이들의 혼합 가스를 사용하여 건식각 공정을 수행함으로써, 산화막 패턴(26) 상부의 질화막 패턴(24)은 식각되지 않고 산화막 패턴(26)만이 선택적으로 식각된다.At this time, by performing a wet etching process using a solution containing hydrofluoric acid (HF), or by performing a dry etching process using a methane trifluoride (CHF 3 ) gas, methane tetrafluoride (CF 4 ) gas or a mixture thereof The
도 1f를 참조하면, 상기 결과물로부터 질화막 패턴(24)을 인산을 이용한 습식각으로 제거하여 0.13㎛ 이하의 크기를 갖는 산화막 패턴(26)이 최상부에 노출되도록 한다.Referring to FIG. 1F, the
도 1g를 참조하면, 0.13㎛ 이하의 크기를 갖는 산화막 패턴(26)을 식각 마스크로 사용하여 하부의 폴리실리콘막(12)을 식각하여 0.13㎛ 이하의 크기를 갖는 게이트라인 패턴(28)을 형성한다.Referring to FIG. 1G, the
도 1h를 참조하면, 상기 결과물의 전체표면 상부에 산화막(30)을 증착한다.Referring to FIG. 1H, an
이때, 게이트라인 패턴(28) 형성한 다음, 식각 마스크로 사용된 산화막 패턴 (26)을 제거한 후에 산화막(30)을 증착할 수도 있고, 산화막 패턴(26)을 그대로 남긴 후에 산화막(30)을 증착할 수도 있다.In this case, after the
이상에서 살펴본 바와 같이, 본 발명에서는 KrF(248nm)를 노광원으로 사용하여 0.13㎛ 이상의 크기를 갖는 포토레지스트 패턴을 형성한 후에, 그 하부에 형성된 산화막 패턴을 선택적으로 식각하여 0.13㎛ 이하의 크기로 만들어 이를 식각 마 스크로 사용함으로써, 결국 KrF 노광장비를 사용하여 0.13㎛ 이하의 크기를 갖는 게이트라인 패턴을 형성할 수 있어 상당한 원가 절감의 효과를 볼 수 있고, 추가적인 고가 장비 투자를 최소화함으로써 가격 경쟁력을 가질 수 있다. 아울러, 본 발명에서는 ArF 노광장비를 이용하는 경우, 해상능력 한계 이하의 패턴을 구현하기 위해 사용해야 하는 F2(157nm) 노광장비, EUV(13nm) 노광장비 또는 전자빔 노광장비 등의 더 고가 장비에 대한 투자 없이 ArF 노광장비를 이용하여 초미세 패턴을 형성할 수도 있다.As described above, in the present invention, after forming a photoresist pattern having a size of 0.13 μm or more using KrF (248 nm) as an exposure source, the oxide film pattern formed on the lower portion thereof is selectively etched to a size of 0.13 μm or less. By using it as an etch mask, it is possible to form a gate line pattern having a size of 0.13 μm or less by using KrF exposure equipment, which can realize significant cost savings and minimize the cost of additional expensive equipment. Can have In addition, in the present invention, when using ArF exposure equipment, investment in more expensive equipment such as F 2 (157 nm) exposure equipment, EUV (13 nm) exposure equipment or electron beam exposure equipment that should be used to implement a pattern below the resolution limit It is also possible to form an ultrafine pattern using ArF exposure equipment.
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