KR100546171B1 - Dual damascene pattern formation method - Google Patents

Abstract

The present invention relates to a method for forming a dual damascene pattern of a semiconductor device, and more particularly, a first step of sequentially stacking a via dielectric layer, a trench dielectric layer, an antireflective coating layer, and a negative tone via photoresist layer on a semiconductor substrate; A second step of forming a via hole pattern in the negative tone via photoresist layer by using a mask to expose the antireflective coating layer; Forming a negative tone trench photoresist layer on the via hole pattern and the negative tone via photoresist layer; Selectively removing only the negative tone trench photoresist using a mask to simultaneously form a trench pattern and the via hole pattern to expose the antireflective coating layer; And a fifth step of forming a via hole in the via dielectric layer by forming an isotropic angle while maintaining the trench pattern and the via hole pattern, and forming a trench in the trench dielectric layer to expose the substrate. As a result, the metal line forming process of the semiconductor device can be significantly simplified, and the like.

Description

Method for manufacturing dual damascene pattern {Method for Manufacturing Dual Damascene Pattern}

1 to 7 is a process chart of the dual damascene pattern forming method according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

10 substrate 20 via dielectric layer

30: first stopper layer 40: trench dielectric layer

50: second stopper layer 60: organic lower antireflection coating layer

70: via photoresist layer 72: via hole pattern

80 trench photoresist layer 82 trench pattern

The present invention relates to a method of forming a double damascene pattern of a semiconductor device, and more particularly, to a method of forming a double damascene pattern by simultaneously forming a double negative tone photoresist layer and simultaneously etching via holes and trenches.

In order to improve the speed of CMOS logic devices, we have relied mainly on reducing the gate length. However, as the device is integrated, the resistance capacitance delay caused by the metallization of the back end of line (BEOL) determines the speed of the semiconductor device. In order to reduce the RC delay, a dual damascene method is used in which low-resistance copper is used as a metal and low-k dielectric material is used to simultaneously form via holes and metal interconnects.

There are several ways to form such a dual damascene pattern, but in general, Via first scheme for forming a dual damascene pattern by first forming a via hole which is most advantageous in terms of photo mask alignment and then forming a trench (Via First) Scheme).

However, in this case, in order to prevent the barrier layer under the via hole from being etched by the trench etching process, the via hole is buried using a planar type organic bottom arc (ARRC) and a resist as the etch stop layer. However, in the conventional dual damascene pattern forming method, the via hole and the trench are formed by separate etching processes, and the overall process step is complicated, and the density of the via hole pattern is embedded in the via hole. Since the height of the etch stop layer is different for each via hole, the trench pattern is easily distorted during the etching of the trench, and it is difficult to set the etching conditions. In other words, the content hole under the stopper layer between the trench and the via hole becomes wider to form voids.

The present invention is to solve the above problems, by using a double photoresist layer of negative tone to form a trench and via holes at the same time to simplify the metal line forming process, a double defect does not occur by the via hole filling process Its purpose is to provide a method for forming a damascene pattern.

In order to achieve the above object, a first step of sequentially depositing a via dielectric layer, a trench dielectric layer, an antireflective coating layer, and a negative tone via photoresist layer on a semiconductor substrate according to the present invention; A second step of forming a via hole pattern in the negative tone via photoresist layer by using a mask to expose the antireflective coating layer; Forming a negative tone trench photoresist layer on the via hole pattern and the negative tone via photoresist layer; Selectively removing only the negative tone trench photoresist using a mask to simultaneously form a trench pattern and the via hole pattern to expose the antireflective coating layer; And a fifth step of forming a via hole in the via dielectric layer by forming an isotropic angle while maintaining the trench pattern and the via hole pattern, and forming a trench in the trench dielectric layer to expose the substrate. do.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 illustrate each step of the dual damascene pattern forming method according to the embodiment of the present invention.
A method of forming a dual damascene pattern according to the present invention will be described with reference to FIG. 1, on the semiconductor substrate 10, a via dielectric layer 20, a trench dielectric layer 40, an antireflective coating layer 60, and a negative tone via photo. A first step of sequentially laminating the resist layer 70 is performed. At this time, the negative tone via photoresist layer 70 is laminated to a thickness sufficient to form the via hole pattern 72. The antireflective coating layer 60 may be either a conformal type lower antireflective coating layer BARC or a planar type lower antireflective coating layer BARC. In the conventional dual damascene pattern forming method, a planar type in which the thickness of the lower reflective coating layer is thickly applied at a low level and thinly applied at a high level in order to prevent via attack on the via hole during trench etching. Although only the via is used in the present invention, since no via attack occurs, not only the planar type but also the conformal type lower reflective coating layer that maintains the same thickness regardless of the lower step may be used. Therefore, in the present invention, regardless of the type of the antireflective coating layer, there is an advantage of selecting an antireflective coating layer having excellent performance.

Preferably, as shown, a second stopper layer 50 is disposed between the first stopper layer 30 and the trench dielectric layer 40 and the antireflective coating layer 60 between the via dielectric layer 20 and the trench dielectric layer 40. Further stacking may be used to adjust the via hole etching rate and the trench etching rate during etching.

Next, as shown in FIG. 2, a second step of exposing the antireflective coating layer 60 by forming a via hole pattern 72 in the negative tone via photoresist layer 70 using a mask is performed. As shown in FIG. 3, a third step of forming the negative tone trench photoresist layer 80 on the via hole pattern 72 and the via photoresist layer 70 is performed. In this case, the negative tone trench photoresist layer 80 may be formed to fill the via hole pattern 72 and cover all of the via photoresist layer 70.
In this case, when the positive tone photoresist is used during the via hole patterning, the via photoresist layer may be a negative tone photoresist because light may enter the via photoresist layer during the trench exposure, resulting in resist loss and pattern deformation. It is desirable to.

Next, as shown in FIG. 4, a fourth step of selectively removing only the negative tone trench photoresist using a mask to simultaneously form a trench pattern 82 and a via hole pattern 72 to expose an antireflective coating layer. Is carried out. In order to distinguish the exposure process in the fourth step from the exposure process in the second step, the second exposure step causes the reaction to occur only in the negative tone trench photoresist in the second exposure step and not in the negative tone via photoresist. And photoresist should be selected. Accordingly, the negative tone trench photoresist filled in the via hole pattern 72 is removed through the second exposure process, and the via hole pattern 72 formed in the negative tone via photoresist layer 70 in the first exposure process is again. The trench pattern 82 is newly formed in the trench photoresist layer 80. The wavelength of the exposure light source used in the first exposure process and the second exposure process is preferably one of 365 nm (I_line), 248 nm (Krf) and 193 nm (Arf), respectively.

Next, as shown in FIGS. 5 to 7, when the isotropic angle is maintained while maintaining the trench pattern 82 and the via hole pattern 72, via holes are eventually formed in the via dielectric layer 20. A trench is formed in the dielectric layer 40 to complete the dual damascene pattern.

As described above, according to the method of forming a dual damascene pattern according to the present invention, since the via hole pattern and the trench pattern are first generated in the photoresist layer, the dual damascene pattern is formed by conformal conformation while maintaining the pattern. In addition, the metal line forming process of the semiconductor device can be significantly simplified, and since there is no need to bury the etch stop layer in the via hole, the BARC filling defect in the via hole, the fencing phenomenon after the trench etching, The content hole under the stopper layer between the trench and the via hole is wider to provide a remarkable effect of forming a dual damascene pattern without the problem of forming voids.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (5)

Sequentially depositing a via dielectric layer, a trench dielectric layer, an antireflective coating layer, and a negative tone via photoresist layer on the semiconductor substrate; A second step of forming a via hole pattern in the negative tone via photoresist layer by using a mask to expose the antireflective coating layer; Forming a negative tone trench photoresist layer on the via hole pattern and the negative tone via photoresist layer; Selectively removing only the negative tone trench photoresist using a mask to simultaneously form a trench pattern and the via hole pattern to expose the antireflective coating layer; And A fifth step of forming a via hole in the via dielectric layer by forming an isotropic angle while maintaining the trench pattern and the via hole pattern, and forming a trench in the trench dielectric layer to expose the substrate Dual damascene pattern forming method comprising a. delete The method of claim 1, The first step is a method for forming a dual damascene pattern, further comprising a stopper layer between the via dielectric layer and the trench dielectric layer and between the trench dielectric layer and the antireflective coating layer. The method of claim 1, The anti-reflective coating layer is a dual damascene pattern forming method, characterized in that any one of a conformal (type) bottom anti-reflective coating layer or planar type bottom anti-reflective coating layer. The method of claim 1, The second and fourth steps of the dual damascene pattern forming method using any one of the wavelength of 365 nm (I_line), 248 nm (Krf), 193nm (Arf) as the exposure light source.

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