KR100540664B1 - Apparatus and method for detecting binary data - Google Patents

Abstract

Disclosed are a binary data detection apparatus and method. A device for detecting binary data according to the present invention, comprising: an AD converter for converting binary data from an input analog signal; At least one binarizer for converting the digital signal into binary data; A Viterbi decoder for performing binary Viterbi decoding to detect binary data from the digital signal; And at least two or more binary data of the digital signal and the output binary data of the Viterbi decoder or the output binary data of the at least one binarization unit, the at least two binary data values corresponding to each other on a time axis. And a level detector for detecting and outputting a level value for the Viterbi decoding from the digital signal when the predetermined number coincides with each other. According to the present invention, binary data can be detected more accurately from an analog signal. In particular, binary data can be detected more accurately from an optical disk on which data is recorded at a higher density.

Description

Apparatus and method for detecting binary data}

1 is a block diagram of a binary data detection apparatus according to an embodiment of the present invention;

2A is a diagram illustrating a 3T signal normally detected in the case of a (2,10) code;

2B is a diagram showing a normally detected 2T signal in the case of a (1,7) code;

3A is a diagram illustrating an example of a 3T signal distorted due to noise in the case of a (2,10) code;

3B is a view illustrating another example of a 3T signal distorted due to noise in the case of a (2,10) code;

4 is a reference diagram for explaining an example of a signal correction method;

5 is an example of a flowchart of a run-length compensation method;

6 is a block diagram of an FIR filter 14 in accordance with an embodiment of the present invention.

7 is a block diagram of a level detector 18 according to an embodiment of the present invention;

FIG. 8A illustrates an objective channel filter 200 of the type (a, b, a) according to an embodiment of the present invention.

8B is a diagram illustrating an objective channel filter 200 of the type (a, b, b, a) according to an embodiment of the present invention.

8C is a diagram illustrating an objective channel filter 200 of the type (a, b, c, b, a) according to an embodiment of the present invention.

9 is a flowchart for explaining an operation of the selection signal generator 201;

10A is a diagram illustrating an input RF signal,

10b is a diagram illustrating a sampling signal from which a DC offset is removed;

10C is a diagram showing an output signal of the FIR filter 14,

10D illustrates binary data output from the Viterbi decoder 16;

10E illustrates levels output from the destination channel filter 200;

10F is a diagram illustrating an input signal to the switch 202.

The present invention relates to a binary data detection apparatus and method, and more particularly, to a binary data detection apparatus and method capable of more accurately detecting binary data from an analog signal.

There is an optical disc as a data storage medium. The optical disc drive generates an electrical signal proportional to the intensity of light reflected from the optical disc. An electrical signal proportional to the intensity of light reflected from the optical disk is called a radio frequency (RF) signal. The drive detects binary data recorded on the optical disk from the RF signal.

Although binary data is recorded on the optical disk, the RF signal has the characteristics of an analog signal due to the disk characteristics and optical characteristics. Therefore, one of the binarization means for detecting binary data from an analog signal is a Viterbi decoder.

In general, Viterbi decoders are known to have better detection performance of binary data than simple sign detection circuits or run-length correction schemes. For a more detailed description of a detector with a Viterbi decoder, see Korean Patent Application No. 2000-0056149, "Selective Disturbance Compensation Device and 3T Correction Method for Reproducing Optical Recording Media," and Korean Patent Application No. 1998-0049542, "Data Reproduction." Device ".

However, as the data recording density becomes higher to record more data on the optical disk, there is a problem that the quality of the reproduced signal becomes worse when detecting binary data from the RF signal using the prior art. In addition, since the shape of the pits (or marks) recorded on the optical disc may vary depending on the quality of the optical disc, there is a problem that a reproduction deviation occurs for each optical disc.

Accordingly, an aspect of the present invention is to provide a binary data detection apparatus capable of detecting binary data more accurately from an analog signal.

Another object of the present invention is to provide a binary data detection method capable of detecting binary data more accurately from an analog signal.

In order to achieve the above object, the binary data detection apparatus according to an aspect of the present invention,

An apparatus for detecting binary data from an input analog signal, comprising: an AD converter for converting the input analog signal into a digital signal; At least one binarizer for converting the digital signal into binary data; A Viterbi decoder for performing binary Viterbi decoding to detect binary data from the digital signal; And at least two or more binary data of the digital signal and the output binary data of the Viterbi decoder or the output binary data of the at least one binarization unit, the at least two binary data values corresponding to each other on a time axis. And a level detector for detecting and outputting a level value for the Viterbi decoding from the digital signal when the predetermined number coincides with each other.

The level detector may include at least one delay unit for synchronizing the at least two binary data.

The level detector may include a switch configured to receive the digital signal and switch the digital signal according to a level to which each digital value of the digital signal belongs; A destination channel filter configured to receive one of the at least two binary data and output a level value of a predetermined type; And a selection signal generator for controlling the switch based on the predetermined type of level value received from the target channel filter.

In addition, the level detector may perform NXOR operation on each corresponding value of the at least two or more binary data to determine whether the at least two or more synchronized binary data values coincide with each other by a predetermined number or more. It is preferable to include at least one NXOR operator.

The level detector may further include an OR operator configured to perform an OR operation by receiving an output value of the at least one NXOR operator, and the selection signal generator may perform the switching control operation according to an output signal of the OR operator. Do.

Further, the destination channel filter is more preferably the same type of filter as the Viterbi decoder.

The Viterbi decoder may be a Viterbi decoder of type (a, b, a), a Viterbi decoder of type (a, b, b, a) or a Viterbi type of (a, b, c, b, a) It is preferably one of the decoders.

In order to achieve the above another object, the binary data detection method according to an aspect of the present invention,

CLAIMS 1. A method for detecting binary data from an input analog signal, comprising: converting the input analog signal into a digital signal; Binarizing the digital signal into first binary data; A Viterbi decoding step of performing Viterbi decoding to detect second binary data from the digital signal; When the digital signal, the first binary data and the second binary data are input, and the first binary data and the second binary data values corresponding to each other on the time axis coincide with each other for a predetermined number or more, from the digital signal. Detecting a level value for the Viterbi decoding.

The method may further include synchronizing the first binary data and the second binary data.

The level value detecting step for Viterbi decoding may include: outputting a predetermined type of level value from one of the first binary data and the second binary data; And switching the digital signal according to a level to which each digital value of the digital signal belongs based on the predetermined type of level value.

In addition, the level value detecting step for Viterbi decoding includes NXOR corresponding respective values of the at least two or more binary data to determine whether the at least two or more synchronized binary data values coincide with each other by a predetermined number or more. (Not eXclusive OR) preferably comprises the step of.

The detecting of the level value for decoding Viterbi may include performing an OR operation by receiving an output value of the at least one NXOR operator, and switching the digital signal by the OR operation result signal. It is desirable to perform a switching control operation.

In order to achieve the above another object, the binary data detection method according to another aspect of the present invention,

CLAIMS 1. A method for detecting binary data from an input analog signal, comprising: converting the input analog signal into a digital signal; Binarizing the digital signal into first binary data; Binarizing the digital signal into second binary data; If the first binary data and the second binary data values corresponding to each other on the time axis correspond to each other by a predetermined number or more, the digital signal, the first binary data and the second binary data may be inputted. Detecting from said digital signal a level value to be used for Viterbi decoding; And a Viterbi decoding step of detecting output binary data from the digital signal using the detected level value.

The method may further include synchronizing the first binary data and the second binary data.

The level value detecting step for Viterbi decoding may include: outputting a predetermined type of level value from one of the first binary data and the second binary data; And switching the digital signal according to a level to which each digital value of the digital signal belongs based on the predetermined type of level value.

In addition, the level value detecting step for Viterbi decoding includes NXOR corresponding respective values of the at least two or more binary data to determine whether the at least two or more synchronized binary data values coincide with each other by a predetermined number or more. (Not eXclusive OR) preferably comprises the step of.

The detecting of the level value for decoding Viterbi may include performing an OR operation by receiving an output value of the at least one NXOR operator, and switching the digital signal by the OR operation result signal. It is desirable to perform a switching control operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an embodiment of a digital data detection apparatus according to the present invention. Referring to FIG. 1, an apparatus for detecting digital data includes an analog-to-digital converter (ADC) 11, a DC offset canceler 12, a first binarizer 13, an FIR filter 14, It includes a two binarization unit 15, a Viterbi decoder 16, a PLL 17 and a level detector 18.

The ADC 11 converts the RF signal into a digital signal. The digital signal that is the output of the ADC 11 is not a binary signal, but a signal obtained by sampling an RF signal at a predetermined period.

The DC offset remover 12 receives a digital signal output from the ADC 11 and removes the DC offset value. The signal from which the DC offset value has been removed is input to the first binarization unit 13, the FIR filter 14, and the PLL 17.

In the present embodiment, the DC offset removing unit 12 removes the DC offset present in the digital signal that is the output of the ADC 11 by using the principle that data is generated such that the digital sum value (DSV) of the input signal becomes 0. .

PLL 17 generates a system clock. In more detail, the digital signal, which is the output of the ADC 11 from which the DC offset is removed, is input, obtains a phase error with the current system clock, and then changes the system clock so that the phase error becomes 0. Synchronize the system clock with the digital signal output from

The first binarizer 13 outputs binary data 3 from the digital signal that is the output of the ADC 11 from which the DC offset is removed. The second binarizer 13 outputs binary data 2 from the output signal of the FIR filter 14.

The first binarizing unit 13 or the second binarizing unit 13 may be implemented in various ways. For example, a run-length compensator may be used as the first binarization unit 13 or the second binarization unit 13. The run-length compensator is a compensator for compensating for the violation of the code rule when an input signal is received and outputting a signal conforming to the code rule. Commonly used codes for optical discs are (2,10) and (1,7) codes. For (2,10) codes, 3T (T is unit period or pit length) signal, which is three times the basic pit period. Becomes the shortest signal. In the case of the (1,7) code, the 2T signal, which is twice the basic pit period, becomes the shortest signal.

Therefore, when data is normally recorded on the optical disk, 2T or 1T signals smaller than 3T cannot be detected in the case of an optical disk using the (2,10) code. Similarly, in the case of an optical disk using the (1,7) code, a 1T signal smaller than 2T cannot be detected.

2A is a diagram showing 3T signals normally detected in the case of (2, 10) codes. Whether or not it is a 3T signal is determined using the sign of the average value between the sampled signals. Referring to FIG. 2A, 21, 22, 23, and 24 represent sampling points, and portions indicated by triangles correspond to average values of both sampling points. Since the mean value of sampling points 21 and 22, the mean value of 22 and 23, and the sign of the mean value of 23 and 24 are both positive, the signal shown in FIG. 2A can be determined as a 3T signal.

2B is a diagram showing a normally detected 2T signal in the case of the (1,7) code. As described above, it is determined whether the signal is a 2T signal by using the sign of the average value between the sampled signals. That is, since the sign of the mean value of the sampling points 25 and 26 and the mean value of the 26 and 27 are both positive, the signal shown in FIG. 2B can be determined as a 2T signal.

However, noise is added to the input signal, which causes a large amount of distortion in the sampled signal, thereby causing error in signal detection.

3A is a diagram illustrating an example of a 3T signal distorted due to noise in the case of a (2,10) code. Referring to FIG. 3A, since the average values of sampling points 31 and 32 are negative signs, the average values of 32 and 33 are positive signs, and the average values of 33 and 34 are positive, the signal shown in FIG. 3A is incorrectly determined as a 1T signal.

3B is a diagram illustrating another example of a 3T signal distorted due to noise in the case of a (2,10) code. Referring to FIG. 3B, since the average value of sampling points 35 and 36 is a positive sign, the average value of 36 and 37 is a positive sign, and the average value of 37 and 38 is negative, the signal shown in FIG. 3B is incorrectly determined as a 2T signal.

In order to properly detect a signal from the distorted signals shown in FIGS. 3A and 3B, it is necessary to correct the distorted signal. An example of a method of correcting a distorted signal will be described. Correction of the signal defines how the operation is to be performed on the sampling points that need correction.

4 is a reference diagram for explaining an example of a signal correction method. Referring to FIG. 4, when a sampling point requiring correction is a and c is another sampling point, an average value b of a and c is determined by Equation 1 below.

At this time, the sign of b serves as a criterion for determining the signal T. If the sign of b is incorrectly determined, the sign of b should be changed. There are several ways to change the sign of b. One example is simply to reverse the sign of b. That is, if b 'having a sign opposite to b is substituted for b in Equation 1, a value to be corrected can be newly obtained by Equation 2 below.

5 is an example of a flowchart of a run-length compensation method. Referring to FIG. 5, the first binarizing unit 13 or the second binarizing unit 13 performing a run-length compensation method checks T of an input signal (S51). The inspection method uses the sign of an average value between sampling points as described above.

As a result of examining the T of the input signal, it is determined whether a signal shorter than the shortest signal is detected (S53). If a signal shorter than the shortest signal is detected, the signal to be corrected is selected (S55), and then corrected in the manner described above (S57).

However, if no signal shorter than the shortest signal is detected, no correction is performed.

Meanwhile, the first binarizing unit 13 or the second binarizing unit 13 may use other binarization means other than the run-length compensator. For example, simple binarization means may be used or both the run-length compensator and the output of the binarization means may be used. The simple binarization means is a binarization means for obtaining an average value between two input signals and then obtaining a sign of the average value and outputting only the code bits as binary data. The first binarizing unit 13 or the second binarizing unit 13 according to the present embodiment may be a means for detecting and outputting binary data from an input signal, regardless of which method is used.

Referring again to FIG. 1, the FIR filter 14 improves the frequency characteristic of the signal to produce a signal having a characteristic suitable for the Viterbi decoder to process.

6 is a diagram illustrating an embodiment of the FIR filter 14. Referring to FIG. 6, the FIR filter 14 includes a plurality of delayers 141 to 143, a plurality of multipliers 144 to 147, and a plurality of multipliers 144 to 147 that delay an input signal by a unit clock (system clock). An adder 148 that adds the outputs. The constants a1 to an of the multipliers 144 to 147 have a range of real numbers including zeros. In this embodiment, the constants a1 to an of the plurality of multipliers 144 to 147 are varied in order to obtain the output signal of the optimal FIR filter 14.

Viterbi decoder 16 detects the optimal binary data using the statistical characteristics of the input signal. To this end, the Viterbi decoder 16 has to define a level suitable for the characteristics of the input signal. The Viterbi decoder 16 has a structure that obtains a binary signal with less error by determining the statistical characteristic of the input signal using the level.

The binary data detection apparatus according to the present embodiment further includes a level detector 18 to provide an optimal level value to the Viterbi decoder 16. The level detector 18 determines what level the input signal is currently in, and then transfers the average value of each level to the Viterbi decoder 16.

The level detector 18 is configured differently according to the type of code of the input signal and the type of Viterbi decoder 16. There are two main types of codes for input signals: (2,10) code series and (1,7) code series. In the case of the (1,7) code, the shortest period is present from the 2T signal having twice the fundamental period, and in the case of the (2,10) code, the shortest period is present from the 3T signal having three times the fundamental period.

The Viterbi decoder 16 uses different types according to the statistical characteristics of the input signal. Generally, the (a, b, a) type Viterbi decoder, (a, b, b, a) type Viterbi decoder and (a There is a, b, c, b, a) type Viterbi decoder.

The binary data detection apparatus according to the present invention includes a level detector 16 for more accurately determining a level value required for the operation of the Viterbi decoder 16. The level detector 16 receives at least two types of binary data detected from an input analog signal, selects two types of binary data, and synchronizes the two types of binary data. If the two kinds of binary data values corresponding to each other on the time axis coincide with each other by a predetermined number or more, a level value to be provided to the Viterbi decoder 16 is detected from the signal to be input to the Viterbi decoder 16.

If the two types of binary data are the same when compared in the time axis, the two types of binary data can be considered to be highly reliable data, and thus the operation of obtaining a level value to be provided to the Viterbi decoder 16 is performed. The level value thus obtained can be said to be highly reliable, and the Viterbi decoder 16 can detect binary data more accurately.

7 is a block diagram of the level detector 18 according to an embodiment of the present invention. Referring to FIG. 7, a signal input to the Viterbi decoder 16 is also input to the level detector 16. The signal input to the Viterbi decoder 16 is delayed for a predetermined time by a plurality of delays 181, 182, and 183 for synchronization, and then transmitted to the switch 202. Multiple delays 181, 182, and 183 can be implemented with D-flipflop.

The first signal selector (signal # 1) 184 and the second signal selector (2) 190 select the binary data, which is the output of the Viterbi decoder 16, of the first binarizer 13. Binary Data3, which is an output, and Binary Data2, which is an output of the second binarization unit 13, are input. The first signal selector 184 selects and outputs one binary data among binary data, binary data 2, and binary data 3 according to a selection signal output from a microcomputer (not shown). The output of the first signal selector 184 is called binary data n1.

Similarly, the second signal selector 190 also selects and outputs one binary data among binary data, binary data 2 and binary data 3 according to a selection signal output from a microcomputer (not shown). When the output of the second signal selector 184 is called binary data n2, the binary data n2 is preferably different from the binary data n1.

In the present embodiment, Binary Data, which is the output of the Viterbi decoder 16, Binary Data3, and the second value, which are outputs of the first binarization unit 13, are transmitted to the first signal selector 184 and the second signal selector 190. FIG. Binary Data 2, which is an output of the fire unit 13, is input, but is not limited thereto. That is, two types of binary data to be compared with each other may be output from the first signal selector 184 and the second signal selector 190, respectively, to determine whether to activate the selection signal generator 201. .

Therefore, as shown in the present embodiment, the binary data that is the output of the Viterbi decoder 16, the binary data 3 that is the output of the first binarization unit 13, and the binary data 2 that is the output of the second binarization unit 13 are all made. It does not need to be input to the first signal selector 184 and the second signal selector 190. For example, only Binary Data, which is an output of the Viterbi decoder 16, is input to the first signal selector 184, and only Binary Data3, which is an output of the first binarizer 13, is input to the second signal selector 190. It may be. In this case, the binary data detection apparatus according to the present embodiment may not include the second binarization unit 13.

Preferably, the binary data n1 output from the first signal selector 184 selects a signal having the smallest error rate. Therefore, it is preferable to select the output signal of the Viterbi decoder 16 as Binary Data n1, but this is not a requirement.

Binary Data n2, which is the output of the second signal selector 190, preferably selects a signal having the highest error rate, but is not a requirement. Binary Data n1 passes through a plurality of delays 185 and 186, and Binary Data n2 also passes through a plurality of delays 191 and 192. The reason is to synchronize the binary data n1 and the binary data n2.

The logic devices 196, 197, and 198 receive NXOR operations by receiving respective data values corresponding to the synchronized Binary Data n1 and Binary Data n2. Table 1 below shows a result of NXOR (Not eXclusive OR) operation.

x y x NXOR y 0 0 One 0 One 0 One 0 0 One One One

As shown in Table 1, when two input values are the same, the result of NXOR operation is "1". Therefore, when the output values of the plurality of logic elements 196, 197 and 198 are all "1", the output of the OR logic element 199 performing the OR operation becomes "1" to enable the selection signal generator 201. .

Binary Data n1 is input to the target channel filter 200. If the binary data n1 and the binary data n2 have the same number or more of data values, the selection signal generator 201 may determine that the binary data n1 input to the target channel filter 200 is highly reliable. Enable level to perform level detection.

The destination channel filter 200 uses the same type of channel filter as the Viterbi decoder 16. 8A-8C illustrate embodiments of the destination channel filter 200.

FIG. 8A shows an objective channel filter 200 of type (a, b, a), and FIG. 8B shows an objective channel filter 200 of type (a, b, b, a), and FIG. 8C shows (a, b, c, b, a) type target channel filter 200 is shown. In general, when reproducing data recorded on an optical disc, the target channel filters mainly used are (a, b, a) type, (a, b, b, a) type and (a, b, c, b, a). Type. When the type of the destination channel filter 200 is determined, the circuit type of the Viterbi decoder 16 is determined. Where constants defined as a, b and c are real numbers greater than or equal to zero. 8A to 8C will be described later with respect to the destination channel filters 200.

When the binary data is input to the destination channel filter 200, some predetermined level values are output according to the code type of the input signal and the type of the destination channel filter 200. The selection signal generator 201 controls the switch 202 after generating the selection signal according to the level value output from the target channel filter 200.

When the output of the target channel filter 200 corresponds to a specific level, the selection signal generator 201 outputs a selection signal corresponding to the level to the switch 202.

9 is a flowchart for explaining an operation of the selection signal generator 201. Referring to FIG. 9, the selection signal generator 201 determines whether "signal valid" is "0" (S71). "signal valid" indicates the output of the OR logic element 199. Therefore, when "signal valid" is "0", since the binary data n1 is inferior in reliability, the selection signal generator 201 generates the selection signal "0" and outputs it to the switch 202 (S72). The switch 202 receiving the selection signal "0" does not detect a level from the signal input to the Viterbi decoder 16.

If "signal valid" is not "0", the selection signal generator 201 determines which level the output of the target channel filter 200 corresponds to, and outputs a selection signal corresponding to the level to the switch 202. do.

The level is defined differently according to the type of the destination channel filter 200 and the type of code. If the type of the destination channel filter 200 is the type (a, b, a) shown in FIG. 8A, in the case of the (1,7) code or the (2,10) code, the destination channel filter 200 may have P1 = 2a +. Output four levels of values: b, P2 = b, P3 = -b, and P4 = -2a-b. The above four level values are determined according to the values input to the multipliers 403 to 405. For example, the level value P1 is the output of the adder 406 when all "1" s are input to the multipliers 403-405. The level value P2 is " 1 " to the multiplier 404 with the multiplication constant " a ", " 1 " 1 is inputted, or " -1 " to multiplier 404 with multiplication constant " a ", " 1 " to multiplier 404 with multiplication constant " b " Is the output of the adder 406 when " 1 "

When the type of the destination channel filter 200 is the type (a, b, b, a) shown in FIG. 8B and is a code (1,7), the destination channel filter 200 has P1 = 2a + 2b and P2 = 2b. 7 levels of P3 = -2a + 2b, P4 = 0, P5 = 2a-2b, P6 = -2b and P7 = -2a-2b are outputted.

When the type of the destination channel filter 200 is the type (a, b, b, a) shown in FIG. 8C and the code is (2,10), the destination channel filter 200 has P1 = 2a + 2b and P2 = 2b. Output five levels of values, P3 = 0, P4 = -2b and P5 = -2a-2b.

If the type of the destination channel filter 200 is the type (a, b, c, b, a) shown in FIG. 8C and is a (1,7) code, the destination channel filter 200 may have P1 = 2a + 2b + c. , P2 = 2b + c, P3 = -2a + 2b + c, P4 = c, P5 = -2a + c, P6 = 2a-c, P7 = -c, P8 = 2a-2b-c, P9 = -2b Outputs the 10 level values of -c and P10 = -2a-2b-c.

Finally, if the type of the destination channel filter 200 is of the type (a, b, c, b, a) shown in FIG. 8C and the code is (2,10), the destination channel filter 200 has P1 = 2a +. 2b + c, P2 = 2b + c, P3 = -2a + 2b + c, P4 = c, P5 = -c, P6 = 2a-2b-c, P7 = -2b-c, P8 = -2a-2b- Print eight levels of c.

In the above-described example, a case in which the values of the input signals input to the destination channel filter 200 are -1 and 1 is taken as an example, but the value of the input signal may be defined as 1 or 0. When the value of the input signal input to the destination channel filter 200 is defined as 1 or 0, the total number of levels does not change but the level value is incorrect.

Referring back to FIG. 9, if "signal valid" is not "0", the selection signal generator 201 determines which level the output of the target channel filter 200 corresponds to (S73, S75, S77). Selection signals corresponding to the level are generated (S74, S76, S78, and S79). The switch 202 transfers the signal input to the switch 202 according to the selection signal input from the selection signal generator 201 to one of the plurality of average filters 204 to 207.

FIG. 10A illustrates an RF signal input to the binary data detecting apparatus according to the present invention shown in FIG. 1, and FIG. 10B is a DC offset removed by the DC offset removing unit 12 after being sampled by the ADC 11. It is a figure which shows a signal. The signal from which the DC offset is removed is input to the first binarization unit 13, the FIR filter 14, and the PLL 17.

Sampling can sample the zero crossing of an RF signal or a point 180 degrees out of phase with the zero crossing. The signal shown in FIG. 10B corresponds to a case where a portion having a 180 degree phase difference is sampled.

10C is a diagram illustrating an output signal of the FIR filter 14. When the signal shown in FIG. 10B passes through the FIR filter 14, the high frequency component is amplified. The output signal of the FIR filter 14 becomes the input signal of the Viterbi decoder 16. As the input signal of the Viterbi decoder 16 passes through the FIR filter 14, a time delay of several system clocks may occur.

The output signal of the FIR filter 14 is input to the Viterbi decoder 16 or the second binarization unit 15 to output binary data, respectively. In this embodiment, binary data is also output from the first binarization unit 13. However, for convenience of explanation, it is assumed that only the output of the Viterbi decoder 16 is input to the level detector 18. FIG. 10D is a diagram showing binary data that is an output of the Viterbi decoder 16 when the signal shown in FIG. 10C is input to the Viterbi decoder 16. FIG.

FIG. 10E illustrates levels that are outputs of the destination channel filter 200. When the binary data shown in FIG. 10D is input to the destination channel filter 200 of the type (a, b, a), the destination channel filter ( 200). For example, when the first binary data "-1, 1, 1" is input to the destination channel filter 200, the destination channel filter 200 outputs the level value "b". The next level value "b" is an output when the binary data input to the destination channel filter 200 is "1, 1, -1".

Levels that are outputs of the destination channel filter 200 shown in FIG. 10E are input to the selection signal generator 201. The selection signal generator 201 sequentially receives "b, b, -b, -b, b, 2a + b, b, -b, -2a-b, -b" from the target channel filter 200, The select signals P2, P2, P3, P3, P2, P1, P2, P3, P4, and P3 are generated and output to the switch 202, respectively.

10F is a diagram showing an input signal to the switch 202, in which the signal shown in FIG. 10C is a signal delayed by a predetermined time. The switch 202 transfers the signal shown in FIG. 10F to one average filter among the plurality of average filters 204 to 207 according to the selection signal that is the output of the selection signal generator 201. That is, a signal having a magnitude of 4.1 is input to the average value filter # 1 204, and four signals having a magnitude of 2.1, 1.9, 2.2, and 1.9 are input to the average value filter # 2 205.

Four signals having the magnitudes of -2.0, -2.3, -2.0, and -1.8 are input to the average filter # 3 206, and signals having the magnitude of -4.3 are input to the average filter # 4 (not shown). . The average value filters 204 to 207 receive a signal for a number of times defined by a microcomputer (not shown) and output the average value.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disks, optical data storage devices, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). It includes being. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

As described above, according to the present invention, binary data can be detected more accurately from an analog signal. In particular, binary data can be detected more accurately from an optical disk on which data is recorded at a higher density.

Claims (21)

An apparatus for detecting binary data from an input analog signal, An AD converter for converting the input analog signal into a digital signal; At least one binarizer for converting the digital signal into binary data; A Viterbi decoder for performing binary Viterbi decoding to detect binary data from the digital signal; And The at least two binary data values corresponding to each other on the time axis are received by receiving at least two or more binary data of the digital signal and the output binary data of the Viterbi decoder or the output binary data of the at least one binarization unit. And a level detector for detecting and outputting a level value for the Viterbi decoding from the digital signal if the number is equal to each other. According to claim 1, The level detector, And at least one delayer for synchronizing the at least two binary data. According to claim 1, The level detector, A switch which receives the digital signal and switches the digital signal according to a level to which each digital value of the digital signal belongs; A destination channel filter configured to receive one of the at least two binary data and output a level value of a predetermined type; And And a selection signal generator for controlling the switch based on the level value of the predetermined type received from the target channel filter. The method of claim 3, wherein The level detector, At least one NXOR operator for performing NXOR (Not eXclusive OR) operations on respective corresponding values of the at least two or more binary data to determine whether the at least two or more synchronized binary data values coincide with each other by a predetermined number or more. Apparatus comprising a. The method of claim 4, wherein The level detector, And an OR operation unit which receives an output value of the at least one NXOR operation unit and performs an OR operation. And the selection signal generator performs the switching control operation according to the output signal of the OR operator. The method of claim 3, wherein Wherein the destination channel filter is a filter of the same type as the Viterbi decoder. According to claim 1, And the Viterbi decoder is a Viterbi decoder of type (a, b, a). According to claim 1, And the Viterbi decoder is a Viterbi decoder of the type (a, b, b, a). According to claim 1, The Viterbi decoder is a Viterbi decoder of the type (a, b, c, b, a). In the method for detecting binary data from an input analog signal, Converting the input analog signal into a digital signal; Binarizing the digital signal into first binary data; A Viterbi decoding step of performing Viterbi decoding to detect second binary data from the digital signal; When the digital signal, the first binary data and the second binary data are input, and the first binary data and the second binary data values corresponding to each other on the time axis coincide with each other for a predetermined number or more, from the digital signal. Detecting a level value for the Viterbi decoding. The method of claim 10, Synchronizing the first binary data and the second binary data. The method of claim 10, The level value detection step for decoding Viterbi, Outputting a level value of a predetermined type from one of said first binary data and said second binary data; And Switching the digital signal according to a level to which each digital value of the digital signal belongs based on the predetermined type of level value. The method of claim 12, The level value detection step for decoding Viterbi, Performing a Not eXclusive OR (NXOR) operation on corresponding respective values of the at least two or more binary data to determine whether the at least two or more synchronized binary data values coincide with each other by a predetermined number or more. How to. The method of claim 13, The level value detection step for decoding Viterbi, Performing an OR operation by receiving an output value of the at least one NXOR operator; The switching of the digital signal may include performing the switching control operation according to the OR operation result signal. In the method for detecting binary data from an input analog signal, Converting the input analog signal into a digital signal; Binarizing the digital signal into first binary data; Binarizing the digital signal into second binary data; If the first binary data and the second binary data values corresponding to each other on the time axis correspond to each other by a predetermined number or more, the digital signal, the first binary data and the second binary data may be inputted. Detecting from said digital signal a level value to be used for Viterbi decoding; And And a Viterbi decoding step of detecting output binary data from the digital signal using the detected level value. The method of claim 15, Synchronizing the first binary data and the second binary data. The method of claim 15, The level value detection step for decoding Viterbi, Outputting a level value of a predetermined type from one of said first binary data and said second binary data; And Switching the digital signal according to a level to which each digital value of the digital signal belongs based on the predetermined type of level value. The method of claim 17, The level value detection step for decoding Viterbi, Performing a Not eXclusive OR (NXOR) operation on corresponding respective values of the at least two or more binary data to determine whether the at least two or more synchronized binary data values coincide with each other by a predetermined number or more. How to. The method of claim 18, The level value detection step for decoding Viterbi, Performing an OR operation by receiving an output value of the at least one NXOR operator; The switching of the digital signal may include performing the switching control operation according to the OR operation result signal. In the method for detecting binary data from an input analog signal, Converting the input analog signal into a digital signal; Binarizing the digital signal into first binary data; A Viterbi decoding step of performing Viterbi decoding to detect second binary data from the digital signal; When the digital signal, the first binary data and the second binary data are input, and the first binary data and the second binary data values corresponding to each other on the time axis coincide with each other for a predetermined number or more, from the digital signal. And detecting a level value for the Viterbi decoding. 15. A computer readable recording medium having recorded thereon a program for realizing a method for realizing a method for viterbi decoding. In the method for detecting binary data from an input analog signal, Converting the input analog signal into a digital signal; Binarizing the digital signal into first binary data; Binarizing the digital signal into second binary data; If the first binary data and the second binary data values corresponding to each other on the time axis correspond to each other by a predetermined number or more, the digital signal, the first binary data and the second binary data may be inputted. Detecting from said digital signal a level value to be used for Viterbi decoding; And And a Viterbi decoding step of detecting output binary data from the digital signal using the detected level value. 15. A computer readable recording medium having recorded thereon a program for realizing a method.

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