KR100537625B1 - Discharge display apparatus wherein electric potentials are effectively disconnected - Google Patents

Abstract

In the discharge display apparatus according to the present invention, a discharge display panel, driving units for applying driving signals to respective electrode lines of the discharge display panel, a control unit for generating driving control signals for operating the driving unit, and an image signal to the control unit An image processing unit and a power supply unit supplying driving potentials to the driving units and supplying operating potentials to the driving units and the control unit are provided. The power supply unit includes an AC / DC converter and a plurality of DC / DC converters. The AC / DC converter includes a rectifier circuit and a power factor correction unit. The DC / DC converters convert the DC potential from the AC / DC converter into the driving potentials and the operating potentials, respectively. When the output potential of the rectifier circuit of the AC / DC converter falls below the set potential, the output potential from at least one of the DC / DC converters is forcibly cut off.

Description

Discharge display apparatus wherein electric potentials are effectively disconnected}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discharge display apparatus, and more particularly, to a discharge display panel, drivers for applying driving signals to respective electrode lines of the discharge display panel, and generating driving control signals for allowing the driving units to operate. A discharge display apparatus including a control unit and a power supply unit supplying driving potentials to the driving units and supplying operating potentials to the driving units and the control unit.

FIG. 1 shows the structure of a three-electrode surface discharge plasma display panel as a conventional discharge display panel. FIG. 2 shows an example of one display cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of a conventional surface discharge plasma display panel 1, address electrode lines A _R1 ,..., A _Bm , a dielectric layer. (11, 15), Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), phosphor 16, partition 17 and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _R1 ,..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., And A _Bm . These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) intersect the address electrode lines (A _R1 , ..., A _Bm ). It is formed in a constant pattern on the back of the front glass substrate 10. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (see FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method (see US Pat. No. 5,541,618) basically applied to such a plasma display panel, the resetting, addressing, and sustaining-discharge steps are sequentially performed in the unit subfield. Is performed. In the resetting phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the sustain-discharge step, a predetermined alternating voltage is applied to all the XY electrode line pairs so that the display cells in which the wall voltage is formed in the addressing step cause sustain-discharge. In this sustain-discharge step, a plasma is formed in the discharge space 14 of the selected display cells causing the sustain-discharge, that is, the gas layer, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

The driving device of the discharge display panel as described above includes driving units, a control unit, and a power supply unit. The drivers apply driving signals to respective electrode lines of the discharge display panel. The controller generates driving control signals through which the driving units can operate. The power supply unit supplies driving potentials to the driving units, and supplies operating potentials to the driving units and the control unit. Here, the driving potentials and the operating potentials are always controlled to be constant.

The power supply unit includes an AC / DC converter and a plurality of DC / DC converters. The AC / DC converter converts the input AC potential into a DC potential. The DC / DC converters convert the DC potential from the AC / DC converter into the driving potentials and the operating potentials, respectively. Here, the driving potentials and the operating potentials are always controlled to be constant.

According to the conventional discharge display device as described above, when the power supply is momentarily interrupted and then again performed, the image is not displayed on the display panel and the user has to turn it on after turning off the power switch again. There is this. The reason is that the image processing unit does not detect that the power supply is momentarily interrupted and maintains the states of the distorted internal devices.

It is an object of the present invention to provide a discharge display apparatus in which a normal display can be continued even if the power supply is momentarily interrupted and then again performed.

In the discharge display apparatus of the present invention for achieving the above object, the discharge display panel, the control unit for applying the driving signals to the respective electrode lines of the discharge display panel, the control unit for generating the drive control signals to enable the driving unit And an image processor for providing an image signal to the controller, and a power supply unit for supplying driving potentials to the drivers and supplying operation potentials to the drivers and the controller. The power supply unit includes an AC / DC converter and a plurality of DC / DC converters. The AC / DC converter includes a rectifier circuit and a power factor correction unit. The DC / DC converters convert the DC potential from the AC / DC converter into the driving potentials and the operating potentials, respectively. When the output potential of the rectifier circuit of the AC / DC converter falls below a set potential, the output potential of at least one of the DC / DC converters is forcibly cut off.

According to the discharge display device of the present invention, when the output potential from the at least one DC / DC converter is used as the operating potential of the image processor, the output potential of the rectifier circuit of the AC / DC converter is set. If the voltage falls below the potential, the operation potential of the image processor may be forcibly cut off. Accordingly, even if the power supply is momentarily interrupted and then again performed, the image processing unit may quickly perform a reset operation, and thus the normal display may continue.

Hereinafter, preferred embodiments according to the present invention will be described in detail. Here, the plasma display panel as the discharge display panel included in the discharge display device of the present invention has been described with reference to FIGS. 1 and 2.

3 shows a driving method in the plasma display device as the discharge display device according to the present invention. Referring to FIG. 3, each unit frame is divided into _eight subfields SF ₁ ,..., SF ₈ to realize time division gray scale display. In addition, each subfield SF ₁ , ..., SF ₈ has a reset time R ₁ , ..., R ₈ , an addressing time A ₁ , ..., A ₈ , and sustain-discharge It is divided by time S ₁ , ..., S ₈ .

The discharge conditions of all the display cells become uniform at each reset time R ₁ ,..., R ₈ , while being adapted to the addressing to be performed in the next step.

Each addressing time _{(A 1, ..., A 8} ), the address electrode lines (Fig. 1 A _R1, ..., A _Bm) display data signals are applied at the same time as soon each Y electrode lines in the (Y _1, ..., Y _n ), the scanning pulses are sequentially applied. Accordingly, when high level display data signals are applied while the scan pulse is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

At each sustain-discharge time (S ₁ , ..., S ₈ ), all Y electrode lines (Y ₁ , ..., Y _n ) and all X electrode lines (X ₁ , ..., X _n) Sustain-discharge pulses are alternately applied, causing display discharge in discharge cells in which wall charges are formed at corresponding addressing times A ₁ ,..., A ₈ . Therefore, the luminance of the plasma display panel is proportional to the length of the sustain-discharge time S ₁ ,..., S ₈ occupied in the unit frame. The length of the sustain-discharge time S ₁ , ..., S ₈ occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray levels, including the case where it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ is the sustain-discharge time S ₁ of the first subfield SF ₁ , and the time 1T corresponding to the sustain-discharge time S ₂ of the second subfield SF ₂ is 2. ^The time 2T corresponding to ¹ is maintained in the third subfield SF ₃ -In the discharge time S ₃ , the time 4T corresponding to 2 ² is maintained in the fourth subfield SF ₄ . The discharge time S ₄ has a time 8T corresponding to 2 ³ , and the sustaining-discharge time S ₅ of the fifth subfield SF ₅ has a time 16T corresponding to 2 ⁴ , and the sixth sub field maintenance of the (SF ₆₎ - discharge time (S _6), this time (32T) corresponding to 2 ^5, 7 keep the sub-fields (SF ₇₎ - discharge time period that is equivalent to 2 ⁶ (S ₇₎ 64T and time 128T corresponding to 2 ⁷ are set in the sustain-discharge time S ₈ of the eighth subfield SF ₈ , respectively.

Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, the display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

4 illustrates signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in the unit sub-field SF of FIG. 3. In FIG. 4, reference numeral S _{AR1 ..ABm} denotes a drive signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to.

Referring to FIG. 4, in the first times t1 to t2 of the resetting time R of the unit sub-field SF, first, the first electrode is applied to the X electrode lines X ₁ ,..., X _n . The voltage is continuously raised from the ground voltage V _G to the second voltage V _S. Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

A second voltage from the second time as a wall charge storage time (t2 ~ t3), Y electrode lines of the second voltage (V _S) the voltage applied to the _{(Y 1, ..., Y n} ) (V S) The voltage is continuously raised to the first voltage V _SET + V _{S which} is higher than the fourth voltage V _SET . Here, the ground voltage V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm .

In the third time t3 to t4 as the wall charge distribution time, the Y electrode while the voltage applied to the X electrode lines X ₁ ,..., X _n is maintained at the second voltage V _S. The voltage applied to the lines Y ₁ ,..., Y _n is continuously lowered from the second voltage V _S to the ground voltage V _G as the third voltage. Here, the ground voltage V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around .., Y _n ) move around the X electrode lines X ₁ ,..., X _n . Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG. Meanwhile, since the ground voltage V _G is applied to all the address electrode lines A _R1 ,..., And A _Bm , the address electrode lines A _R1 ,..., A _Bm are X electrode lines ( Discharge is performed on X ₁ , ..., X _n ) and Y electrode lines (Y ₁ , ..., Y _n ), and due to the discharge, the address electrode lines (A _R1 , ..., A) _Bm ) the positive wall charges around it disappear.

At the subsequent addressing time A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ ,... _{Biased to} the fifth voltage V _SCAN lower than the second voltage V _S. , Y _n ), as the scan signal of the ground voltage V _G is sequentially applied, smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive addressing voltage V _A when the display cell is selected and the ground voltage V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive addressing voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the second voltage V _S is maintained at the X electrode lines X ₁ ,... X _n .

In the following display-hold time _S , the display of the second voltage V _{S at} all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . -Hold pulses are alternately applied, causing a discharge for display-holding in the display cells in which wall charges are formed at the corresponding addressing time (A).

4 and 5, a plasma display device as a discharge display device according to the present invention includes a plasma display panel 1, an image processor 56, a logic controller 62, an address driver 53, and an X-driver 54. ), A Y-drive unit 65, and a power supply unit 61.

The plasma display panel 1 has been described with reference to FIGS. 1 and 2. The image processing unit 56 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 56.

The address driver 53 processes the address signal S _A among the driving control signals S _A , S _Y , and S _X from the logic controller 62 to generate display data signals, and generates the generated display data signals. Are applied to the address electrode lines (A _R1 , A _G1 ,..., A _Gm , A _Bm in FIG. 1). The X-drive unit 54 processes the X drive control signal S _X among the drive control signals S _A , S _Y , and S _X from the logic controller 62 to form X electrode lines (X _{1 in} FIG. 1). , ... X _n ). The Y-drive unit 55 processes the Y drive control signal S _Y among the drive control signals S _A , S _Y , and S _X from the logic controller 62 to Y electrode lines (Y _{1 in} FIG. 1). , ... Y _n ).

The power supply unit 61 supplies driving potentials V _A , V _SCAN , V _S , V _SET to the respective driving units 53, 54, 55, the image processing unit 56, and the logic controller 62. 3.3 V, 5 V, V _GT ). More specifically, the operating potential of 5 V is supplied to the image processor 56 and the operating potentials of 3.3 V and 5 V are supplied to the logic controller 62. Further, the sustain-discharge potential V _S , the additional potential V _SET , and the scan-bias potential V _SCAN as the driving potentials are supplied to the Y-drive part 55, and the gate operating potentials as the operating potentials ( v _GT ) and 5 V (volts) are supplied. In addition, the addressing driver 53 is supplied with an addressing potential V _A as a driving potential, and a gate operating potential v _GT and 5 V (volts) as an operating potential. The sustain-discharge potential V _S as the driving potential is supplied to the X-drive section 54, and the gate operating potential v _GT and 5 V (volts) as the operating potential are supplied.

4 and 6, the power supply 61 of FIG. 5 includes a relay 6101, an AC / DC converter 6102, first to fifth DC / DC converters 6101 to 6107, and a connection diode ( D _CON ), the auxiliary rising part 6108, the auxiliary lowering part 6109, the first to seventh sensing-potential generating parts 6110 to 6116, the microcomputer 6171, and the blocking timing controller 6120. .

The relay 6101 passes or blocks the input AC power supply 6161 under the control of the microcomputer 6171. The AC / DC converter 6102 including a rectifier circuit and a power factor _corrector includes a second DC potential having an input AC potential from the relay 6101 lower than the first DC potential V _DCIN1 and the first DC potential V _DCIN1 . V _DCIN2 ).

The first DC / DC converter 6103 _raises the first DC potential V _DCIN1 from the AC / DC converter 6102 and converts it into the sustain-discharge potential V _S as a driving potential. Here, the sustain-discharge potential V _S is frequently used in the X-drive part (54 in FIG. 5) and the Y-drive part (55 in FIG. 5) and thus corresponds to the main potential. Of course, the addressing potential V _A is also frequently used in the address driver 53 (Fig. 5) and thus corresponds to the main potential. However, the additional potential V _SET and the scan-bias potential V _SCAN correspond to auxiliary potentials because they are not frequently used in the Y-drive part 55 (see FIG. 4). Therefore, the auxiliary rising part 6108 generates the additional potential V _SET as the auxiliary potential by raising the sustain-discharge potential V _S as the main potential. In addition, the auxiliary lowering portion 6109 generates the scan-bias potential V _SCAN as the auxiliary potential by lowering the sustain-discharge potential V _S as the main potential. Accordingly, the manufacturing cost of the power supply unit 61 can be reduced.

The second DC / DC converter 6104 _lowers the first DC potential V _DCIN1 from the AC / DC converter 6102 and converts it into an addressing potential V _A as a driving potential.

The third DC / DC converter 6105 _lowers the second DC potential V _DCIN2 from the AC / DC converter 6102 and converts it to the gate operation potential v _GT as an operation potential. The fourth DC / DC converter 6106 _lowers the second DC potential V _DCIN2 from the AC / DC converter 6102 to convert it to 5 V (volts) as an operating potential.

The fifth DC / DC converter 6107 _lowers the second DC potential V _DCIN2 from the AC / DC converter 6102 to convert it to 3.3 V (volts) as an operating potential.

Each of the first to seventh sense-potential generators 6110 to 6116 respectively outputs driving potentials V _A , V _SCAN , V _S , and V _SET and operating potentials 3.3 V, 5 V, and V _GT . Is converted into sense-potentials and input to the microcomputer 6171. The microcomputer 6171 monitors the sensing-potentials from the first to seventh sensing-potential generators 6110 to 6116 to block the relay 6161 when an abnormal potential is generated.

The interruption timing controller 6120 may be configured to generate the fourth and fifth DC / DC converters 6106 and 6107 when the output potential V _REC of the rectifier circuit in the AC / DC converter 6102 falls below a set potential. Output potentials are forced off. Here, since the output potential from the fifth DC / DC converter 6107 is used as the operation potential of the image processing unit (56 in FIG. 5), the image processing unit 56 is performed even if the power supply is momentarily interrupted and then performed again. Since the reset operation can be performed quickly, normal display can be continued.

6 and 7, the AC / DC converter 6102 includes an input filter 71, a rectifier circuit 72, and a power factor compensator 73.

The input AC potential V _ACIN is input to the rectifier circuit 72 through the input filter 71. The input filter 71 filters the noise of the input AC potential V _ACIN . The rectifier circuit 72 converts the input AC potential V _ACIN into a DC potential V _REC . The output potential V _REC of the rectifier circuit 72 is provided to the power factor correction unit 73 and the cutoff timing controller 6120.

The power factor correction unit 73 includes a switching unit TR11 + TR12 + C11, an AC potential conversion unit 151 and 152, diodes D11 and D12, capacitors C12 and C22, and a controller 17. do.

The switching unit TR11 + TR12 + C11 including the AC generating capacitor C11 and the switching elements TR11 and TR12 switches the output potential V _REC from the rectifier circuit 72 to convert to the first AC potential. Let's do it. In the AC potential converting units 151 and 15, the first transformer 151 converts the first AC potential generated by the operation of the switching unit TR11 + TR12 + C11 into a second corresponding to the first DC potential V _DCIN1 . Convert to AC potential. In addition, the second transformer 152 converts the third AC potential generated by the operation of the switching unit TR11 + TR12 + C11 into a fourth AC potential corresponding to the second DC potential V _DCIN2 .

The first diode D11 half-wave rectifies the second alternating current potential from the first transformer 151. The second diode D12 half-wave rectifies the fourth alternating current potential from the second transformer 152.

The first capacitor C12 smoothes the half-wave rectified potential from the first diode D11 to generate the first DC potential V _DCIN1 . The second capacitor C22 smoothes the half-wave rectified potential from the second diode D12 to generate the second DC potential V _DCIN2 . Here, the first and second capacitors C12 and C22 also perform a function of power factor correction for bringing the phase of the current closer to the phase of the voltage.

The controller 17 controls the switching elements TR11 and TR12 of the switching unit TR11 + TR12 + C11 according to the half-wave rectified potential from the first diode D11 to compensate for the power factor, while the half wave is compensated. The rectified potential causes the first DC potential V _DCIN1 to be maintained. More specifically, the composite controller 17 periodically turns on and off the switching elements TR11 and TR12, so that the power factor compensation and potential holding are performed. Controls the On time of. Here, the power factor correction is performed by adjusting the amount of current according to the first DC potential V _DCIN1 .

8 illustrates an internal configuration of the first DC / DC converter 6103 of FIG. 6. The internal configuration of this first DC / DC converter 6103 is also applied to the auxiliary lift 6108.

Referring to FIG. 8, the first DC / DC converter 6103 of FIG. 6 includes switching elements TR81 and TR82, an AC generator capacitor C81, a transformer 85, a diode D81, and a smoothing capacitor. (C82), and the controller 87.

The AC generating capacitor C81 and the switching elements TR81 and TR82 switch and convert the first DC potential V _DCIN1 from the AC / DC converter 6102 of FIG. 6 to an AC potential. Accordingly, the transformer 85 raises the AC potential generated by the operation of the switching elements TR11 and TR12.

The diode D81 half-wave rectifies the alternating potential raised by the transformer 15. Smoothing capacitor C82 smoothes the half-wave rectified potential from diode D81 to generate the sustain-discharge potential V _S.

The controller 87 periodically turns on and off the switching elements TR11 and TR12, but turns on the switching elements TR11 and TR12 to be inversely proportional to the half-wave rectified potential from the diode D81. (On) Controls the time. Accordingly, the additional potential V _SET from the smoothing capacitor C82 can be constantly output. Here, since the ground potential is always applied to the output disable terminal DIS of the controller 87, the output of the controller 87 is always enabled.

9 illustrates an internal configuration of the third DC / DC converter 6105 of FIG. 6. The internal configuration of the third DC / DC converter 6105 for lowering the DC potential is also applied to the auxiliary lower part 6109, the second DC / DC converter 6104, and the fourth DC / DC converter 6106. Apply.

Referring to FIG. 9, the third DC / DC converter 6105 of FIG. 6 includes a controller 97, a flyback diode D91, a power accumulation coil L91, voltage distribution resistors R1 to R3, and A smoothing capacitor C91 is included.

The controller 97 periodically disconnects and connects the second DC potential V _DCIN2 according to the output sense potential from the voltage distribution resistors R1 to R3. Here, the connection time of the second DC potential V _DCIN2 is inversely proportional to the output potential V _GT . That is, when the output potential V _GT rises above the set potential, the connection time of the second direct current potential V _DCIN2 becomes long, and the output potential V _GT falls and becomes equal to the set potential. On the contrary, when the output potential V _GT falls below the set potential, the connection time of the second DC potential V _DCIN2 is shortened and the output potential V _GT rises to be equal to the set potential. Here, since the ground potential is always applied to the output disable terminal DIS of the controller 97, the output of the controller 87 is always enabled.

While the second DC potential V _DCIN2 is periodically interrupted and connected, the second DC potential V _DCIN2 is periodically supplied to the smoothing capacitor C91 through the controller 97 and the power accumulation coil _L91 . do. In addition, the smoothing capacitor C91 generates the output potential V _GT set lower than the second DC potential V _DCIN2 by smoothing the potential input periodically.

On the other hand, while the second DC potential V _DCIN2 is periodically interrupted, the second DC potential V _DCIN2 is not applied to the input terminal of the power accumulation coil _L91 . At this time, a current flows from the power accumulation coil L ₁ to the ground side through the flyback diode D91.

FIG. 10 illustrates an internal configuration of the fourth or fifth DC / DC converters 6106 and 6107 of FIG. 6. In FIG. 10, the same reference numerals as used in FIG. 9 denote the same target objects.

6, 7, 9, and 10, the difference in the configuration of FIG. 10 from the configuration of FIG. 9 is that the disable signal S _DIS from the interruption timing control unit S _DIS is outputted from the controller 97. It is applied to the disable terminal DIS. That is, the blocking timing controller 6120 may include the fourth and fifth DC / DC converters when the output potential V _REC of the rectifier circuit 72 in the AC / DC converter 6102 falls below the set potential. The output potentials of 6106 and 6107 are forcibly cut off. Here, since the output potential from the fourth DC / DC converter 6106 is used as the operating potential of the image processor (56 in FIG. 5), the image processor 56 is performed even if the power supply is momentarily interrupted and then again performed. Since the reset operation can be performed quickly, normal display can be continued.

6, 7, 10, and 11, the blocking timing controller 6120 may include a potential sensing circuit 111 and a signal generation circuit 112. The potential sensing circuit 111 senses the output potential V _REC of the rectifier circuit 72 in the AC / DC converter 6162 and sets an operating condition of the signal generation circuit 112. Accordingly, the signal generation circuit unit 112 generates a high logic disable signal S _DIS when the output potential V _REC of the rectifier circuit 72 falls below the set potential, thereby disabling the controller 97. Disable, otherwise generate a low logic disable signal S _DIS to enable controller 97.

As described above, according to the discharge display apparatus according to the present invention, when the output potential of the rectifier circuit of the AC / DC converter is lower than the set potential, the operation potential of the image processor may be forcibly cut off. Accordingly, even if the power supply is momentarily interrupted and then again performed, the image processor may quickly perform the reset operation, and thus the normal display may continue.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

1 is an internal perspective view showing the structure of a plasma display panel of a three-electrode surface discharge method as a conventional discharge display panel.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the panel of FIG. 1.

3 is a timing diagram showing a driving method in the discharge display device according to the present invention.

4 is a waveform diagram of signals applied to electrode lines of the plasma display panel of FIG. 1 in a unit sub-field of FIG. 3.

5 is a block diagram showing a plasma display device as a discharge display device according to the present invention.

FIG. 6 is a block diagram illustrating an internal configuration of the power supply unit of FIG. 5.

FIG. 7 is a circuit diagram illustrating an internal configuration of the AC / DC converter of FIG. 6.

FIG. 8 is a circuit diagram illustrating an internal configuration of a first DC / DC converter of FIG. 6.

9 is a circuit diagram illustrating an internal configuration of a third DC / DC converter of FIG. 6.

FIG. 10 is a circuit diagram illustrating an internal configuration of a fourth or fifth DC / DC converter of FIG. 6.

FIG. 11 is a block diagram illustrating an internal configuration of a blocking timing controller of FIG. 6.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line, Y ₁ , ..., Yn ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... subfield,

S _Y ... Y drive control signal, S _X ... X drive control signal,

S _A ... address drive control signal, 61 ... power supply,

62 logic controller, 53 address drive,

54 ... X-Drive, 55 ... Y-Drive,

56 ... image processing unit, 6120 ... blocking timing control unit.

Claims (5)

A discharge display panel, drivers for applying driving signals to respective electrode lines of the discharge display panel, a controller for generating drive control signals for allowing the drivers to operate, an image processor for providing an image signal to the controller, and A discharge display apparatus including a power supply unit supplying driving potentials to the driving units and supplying operating potentials to the driving units and the control unit, The power supply unit, AC / DC converter including rectifier circuit and power factor correction unit, and A plurality of DC / DC converters for converting the DC potential from the AC / DC converter into the driving potentials and the operating potentials, respectively; And an output potential from at least one of the DC / DC converters is forcibly cut off when the output potential of the rectifier circuit of the AC / DC converter falls below a set potential. The method of claim 1, wherein the at least one DC / DC converter 6107, Discharge display device for lowering the output potential (V _DCIN2 ) of the AC / DC converter. The method of claim 1, wherein the at least one DC / DC converter 6107, And a controller (97) for outputting a signal obtained by periodically blocking and connecting the output potential (V _DCIN2 ) of the AC / DC converter. The method of claim 3, When the output potential V _REC of the rectifier circuit 72 of the AC / DC converter 6102 falls below a set potential, the controller 97 of the at least one DC / DC converter 6107. Discharging display device of which output signals are disabled. The method of claim 3, And a connection time of the output potential (V _DCIN2 ) of the AC / DC converter (6102) is inversely proportional to the output potential of the at least one DC / DC converter (6107).