KR100537185B1 - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can improve the process margin in the manufacturing process of the semiconductor device to which the SAC process is applied, and can prevent the deterioration of characteristics of the semiconductor device, the present invention, on the substrate Forming first and second conductive patterns having a predetermined interval; Forming an insulating film for an interlayer insulating film on the entire surface including the first and second conductive patterns; Forming a capping insulating film on the insulating film; Forming a photoresist pattern for a self-aligned contact process; Etching the capping insulating layer using the photoresist pattern as an etch mask, and subsequently etching the insulating layer to near the upper portions of the first and second conductive patterns to form a first open portion; Removing the photoresist pattern; Selectively etching the remaining portion of the insulating layer exposed through the first open portion to form a second open portion exposing the substrate between the first conductive pattern and the second conductive pattern; And removing the capping insulating layer.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an ultra-high density integrated circuit MOSFET (Metal Oxide Semiconductor Feild Effect Transitor) semiconductor device having a minimum line width of 100 nm or less as a design rule.

In manufacturing an integrated semiconductor device, after forming a transistor on a substrate, an insulating film forming process and a wiring process for interlayer insulation and planarization are performed. In the highly integrated device having a design rule of 200 nm or less and requiring an ultra fine wiring pattern, a Self Align Contact (hereinafter referred to as SAC) process is generally used in the insulating film etching process for forming the wiring. As an example, a SOD (Spin-On Dielectric) film having excellent gap-fill characteristics is used.

1A and 1B are cross-sectional views illustrating a wire forming process of a MOSFET device according to the prior art, and looks at the problems of the prior art with reference to this.

Referring to FIG. 1A, a field insulating film for separating an active region and a field region is locally formed on a substrate 10, and the field insulating layer includes a liner 11 and a field oxide film 12 using a nitride film or the like. And formed in the lower portion of the substrate in the form of a trench. Here, an example in which the field insulating film is formed by using a shallow trench isolation (STI) method is illustrated. In addition, a LOCOS (LOCal Oxidation Silicon) method may be used.

Wells 13 and wells are formed under the substrate 10 adjacent to the field insulating layer, and a plurality of gate electrode patterns are formed on the substrate 10. The gate electrode pattern has a structure in which the gate insulating film 14, the conductive film 15, and the hard mask 16 are stacked.

The gate insulating film 14 mainly uses an oxide film series, and the conductive film 15 uses a single or combined structure of polysilicon, tungsten, tungsten silicide, tungsten nitride, or the like. The hard mask 16 prevents the conductive film 15 from being attacked in a subsequent process such as SAC etching and also prevents an electrical short between the conductive film 15 and the subsequent connection part. For this purpose, a silicon oxynitride film, a silicon oxide film, or a silicon nitride film is mainly used as the hard mask 16 material.

On the side of the gate electrode pattern, a source / drain of LDD (Lightly Doped Drain) structure is formed on the substrate on the side of the gate electrode pattern during ion implantation, and a process of deposition and front etching to prevent attack on the side of the gate electrode pattern during SAC process The spacer 17 is formed by this. To this end, a silicon oxynitride film, a silicon oxide film, or a silicon nitride film is mainly used as a spacer 17 material.

A source / drain region 18 extending from the surface of the substrate 10 to a predetermined depth by ion implantation and thermal diffusion is formed in the well 13 on the side of the gate electrode pattern, and a hot carrier effect is generated by a short channel. In order to prevent hot carrier effect, a low-level impurity doping and a spacer 17 are formed, followed by high-level impurity doping to form a conventional structure. It was.

An insulating film 19 for interlayer insulation is formed over the entire structure on which the gate electrode pattern is formed, and is formed by a densification process by application and heat treatment using an SOD film having excellent gap-fill characteristics.

A photoresist pattern 20 is formed on the insulating film 19, and the photoresist pattern 20 is opened to expose the source / drain regions 18 by a SAC etching process in which the insulating film 19 is etched using the photoresist pattern 20 as an etch mask. The part 21 is formed.

One of the problems to be solved in the SAC process is to secure a sufficient area at the bottom of the open part 21, while the area (that is, the critical dimension) at the upper part of the open part 21 to secure a margin for a subsequent process or the like. (Critical Dimension (hereinafter referred to as CD)) should not be enlarged but should be minimized.

After the process of FIG. 1A is completed, the photoresist pattern 20 is removed, and then a conductive material such as polysilicon or tungsten is deposited to electrically connect the source / drain region 18 through the open portion 21. Next, a plurality of conductive connections 22 isolated from each other are formed by chemical mechanical polishing (hereinafter referred to as CMP) or local etching. Here, the connection portion 22 includes a plug or a contact pad or the like.

A planarization film 23 is formed of a PMD (Pre-Metal Dielectric) film for insulation and planarization before the wiring process on the front surface where the plurality of planarized connection parts 22 are separated from each other, and then a damascene or a conventional An open part (not shown) for exposing the connection part 22 is formed through a contact forming process, and then a conductive pattern 24 such as a metal wire electrically connected to the exposed connection part 22 is formed.

As the integration degree of the semiconductor device increases, the process margin for keeping the CD of the upper part of the SAC small during the SAC process is further reduced, which causes the following problems.

One). As shown in 'A', the thickness of the photoresist pattern 20 is rapidly increased, a decrease in overlay margin, a decrease in development inspection critical dimension (DICD) margin and a photoresist pattern during the exposure process for SAC formation. Problems such as collapse occur, which causes a bridge between photoresist patterns and an electrical short between wirings or an increase in leakage current in a subsequent process such as a polysilicon wiring process.

2). This is a problem that occurs in the SAC etching process as in 'B'. Reduces Final Inspection Critical Dimension (FICD) margin (i.e. increases CD bias) during the etching process for SAC formation, resulting in increased electrical short-circuit or leakage current between wiring during subsequent processes such as polysilicon wiring .

3). In the etching process for forming the SAC, excessive loss of the hard mask 16 is induced, such as 'C', and as a result, the insulating property between the conductive layer 15 and the connection part 22 is degraded, thereby increasing leakage current. . To prevent this, the thickness of the hard mask 16 should be further increased.

4). Increasing the thickness of the hard mask increases the aspect ratio between the gate electrode patterns, thereby causing voids, thereby degrading the gap-fill characteristics of the insulating film 19. This makes the subsequent ultra fine wiring formation process difficult, and since the operation reliability of the semiconductor device can be reduced by increasing the leakage current, it is difficult to manufacture a semiconductor device in which the integration degree is further improved and the minimum line width is reduced.

The present invention has been proposed to solve the above problems of the prior art, a semiconductor device manufacturing method that can improve the process margin in the manufacturing process of the semiconductor device to which the SAC process is applied, and can prevent the deterioration of characteristics of the semiconductor device Its purpose is to provide.

In order to achieve the above object, the present invention comprises the steps of forming a first and a second conductive pattern having a predetermined interval on the substrate; Forming an insulating film for an interlayer insulating film on the entire surface including the first and second conductive patterns; Forming a capping insulating film on the insulating film; Forming a photoresist pattern for a self-aligned contact process; Etching the capping insulating layer using the photoresist pattern as an etch mask, and subsequently etching the insulating layer to near the upper portions of the first and second conductive patterns to form a first open portion; Removing the photoresist pattern; Selectively etching the remaining portion of the insulating layer exposed through the first open portion to form a second open portion exposing the substrate between the first conductive pattern and the second conductive pattern; And removing the capping insulating layer.

According to the present invention, an organic SOD film is coated and planarized as the first insulating film for interlayer insulation, and then, when the open portion is formed by the SAC process, the CD at the top of the open portion is narrower than before, thereby spacing between SAC and SAC ( Spacing can be increased. Thus, the step and thickness of the photoresist pattern can be reduced during the photolithography process for forming the SAC pattern, thereby preventing the bridge of the photoresist pattern or the collapse of the pattern, and securing DICD and overlay margin. have. In addition, by increasing the FICD margin during the etching process for forming the SAC pattern, it facilitates the ultra-fine wiring process.

To this end, the CD is minimized when the open portion is formed by the SAC etching process, and the open portion is formed by selectively removing the organic SOD film inside the SAC hole in a plasma atmosphere such as O ₂ or O ₃ .

The organic SOD film has a hydrocarbon component such as CH ₃ and C ₂ H ₅ inside the film. When such an organic SOD film is exposed to O ₂ or O ₃ plasma, the hydrocarbon inside the organic SOD film The component reacts with oxygen and is discharged to carbon dioxide (CO ₂ ) to be etched and shrunk. However, the O ₂ plasma and the O ₃ plasma react only with the hydrocarbon component and do not react with the silicon oxide film (SiO ₂ ), the silicon nitride film (Si ₃ N ₄ ), or the like which does not contain the hydro-carbon component. Therefore, the selective removal of only the organic SOD film in the SAC hole is possible, and thus does not cause the loss of the hard mask of the gay electrode pattern.

Therefore, the spacing between the conductive material embedded in the open portion and the gate conductive film can be increased by a subsequent process, thereby increasing the process margin for preventing an electrical short circuit and leakage current between the connection portion and the gate conductive film. Can be.

Increasing the process margin makes it possible to secure a margin for reducing the thickness of the hard mask, and reducing the thickness of the hard mask reduces the aspect ratio between the gate electrode patterns, thereby smoothing the gap-fill characteristics and planarization of the SOD film used for interlayer insulation. Can improve the characteristics.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, and the semiconductor device manufacturing process of the present invention will be described in detail with reference to the drawing.

In addition, the wiring formation process of MOSFET element was taken as the example here.

2A illustrates a process cross section in which a plurality of transistors including a gate electrode pattern and a source / drain region 108 are formed on a substrate 100.

Looking at the manufacturing process in more detail, a field insulating film for separating the active region and the field region is locally formed on the substrate 100. The field insulating film is composed of a liner 101 and a field oxide film 102 using a nitride film or the like, and is formed under the substrate in the form of a trench. Here, an example in which the field insulating film is formed by using the STI method is shown. In addition, the LOCOS method may be applied.

Subsequently, a well 103 such as an N-well or a P-well is formed under the substrate 100 adjacent to the field insulating layer. In addition, the well 103 formation process is well-known and the description of the specific process is abbreviate | omitted.

Subsequently, a plurality of gate electrode patterns forming a structure in which the gate insulating film 104, the conductive film 105, and the hard mask 106 are stacked on the substrate 100 are formed.

When the gate electrode pattern is formed, the gate insulating film 104, the conductive film 105, and the hard mask 106 are sequentially deposited and then formed through a selective etching process using one to three masks, or for each layer. Deposition and patterning processes may also be performed.

Here, the gate insulating film 104 is used to control the threshold voltage of the transistor, and mainly uses an oxide film series, and the conductive film 105 is used alone or in combination of polysilicon, tungsten, tungsten silicide, tungsten nitride, or the like. Use structure.

The hard mask 106 prevents the conductive film 105 from being attacked in a subsequent process such as SAC etching and also prevents an electrical short between the conductive film 105 and the subsequent connection portion. For this purpose, a nitride film series or a silicon oxide film such as a silicon oxynitride film or a silicon nitride film is mainly used as the hard mask 106 material.

Subsequently, a silicon oxynitride film, a silicon oxide film, or a silicon nitride film is deposited along the profile on which the gate electrode pattern is formed, and then a spacer 107 is formed on the side of the gate electrode pattern through front etching.

The spacer 107 is to form a source / drain of an LDD structure in the substrate 100 on the side of the gate electrode pattern during ion implantation and to prevent attack on the side of the gate electrode pattern during the SAC process.

An ion implantation and a thermal diffusion process are performed in the well 103 region on the side of the gate electrode pattern to form a source / drain region 108 extending from the surface of the substrate 100 to a predetermined depth.

Forming the source / drain region 108 in the LDD structure is to prevent the hot carrier effect due to the short channel, and is formed at a low level on the substrate 100 on the side of the gate electrode pattern through ion implantation before forming the spacer 107. After the doping of the impurities, the spacer 107 is formed, followed by ion implantation to perform high-level impurity doping again to form a conventional structure.

As shown in FIG. 2B, an insulating film 109 for interlayer insulation is formed on the entire structure where the gate electrode pattern is formed, and then coated using an SOD film having excellent gap-fill characteristics, and the like, for densification of the film. A heat treatment step is carried out.

Meanwhile, in the present invention, an organic-based SOD film that can be selectively removed by a subsequent O ₂ or O ₃ plasma among the SOD films is used, and it does not matter whether the material of the SOD film includes a material other than hydro-carbon. none. However, it is preferable to use the one containing 5w% or more of the hydrocarbon component in the film after the heat treatment.

Here, it is preferable to perform heat processing for film densification within the temperature range of 400 degreeC-1000 degreeC.

Subsequently, a capping insulating layer 110 is deposited on the insulating layer 109. The capping insulating layer 110 may be selectively etched when the insulating layer 109 including the hydrocarbon structure is removed using a subsequent oxygen plasma. Therefore, it is preferable to use an oxide-based or nitride-based insulating material film having an etching resistance to oxygen plasma.

As shown in FIG. 2C, after forming the photoresist pattern 111 for the SAC process on the capping insulating layer 110, the capping insulating layer 110 and the insulating layer 109 are formed using the photoresist pattern 111 as an etch mask. A portion of the portion is etched to form the first open portion 112. By forming the first open portion 112, the pattern formation region for SAC formation is defined.

In this case, it is preferable to use a dry etching method by etching the insulating film 109 to the upper portion near the gate electrode pattern. Accordingly, since the target to be etched by the SAC process decreases the thickness of the insulating layer 109, that is, the etching target, the CD of the photoresist pattern 111 and the first open part 112 is not required to be larger than in the prior art. do.

Therefore, since the spacing between the SAC and the SAC, that is, the first opening 112 is wider and the layer to be etched is thin, the thickness of the photoresist pattern 111 may also be lowered. This reduces the step of the photoresist pattern 111 for forming the SAC, reduces the collapse of the photoresist pattern and the occurrence of bridges during etching, and increases the overlay and DICD margins to form a more reliable SAC pattern. It becomes easy to do it.

Next, a photoresist strip process is performed to remove the photoresist pattern 111. Meanwhile, the photoresist pattern 111 may be removed after the completion of the subsequent SAC process.

Subsequently, as shown in FIG. 2D, the second insulating layer 109 exposes the source / drain region 108 between the gate electrode patterns by selectively removing the remaining insulating layer 109 using the plasma 113 including oxygen. Open section 115 is formed.

The organic SOD film used as the insulating film 109 has a hydrocarbon component such as CH ₃ or C ₂ H ₅ inside the film. When the organic SOD film is exposed to an oxygen plasma, the hydrocarbon component inside the organic SOD film becomes oxygen. Reacts with carbon dioxide (CO ₂ , 114) and the like is etched and contracted. However, an oxygen plasma such as O ₂ or O ₃ reacts only with a hydrocarbon component, and a capping insulating layer 110 such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ) that does not contain a hydrocarbon component. ) Does not respond. Therefore, the selective removal of only the organic SOD film in the SAC hole is possible, and thus does not cause the loss of the hard mask of the gay electrode pattern.

In the oxygen plasma, a down stream method using a gas containing oxygen such as O ₂ , O ₃ , CO ₂ , or N ₂ O is used.In this case, in order to activate selective removal of only the organic SOD film, It is preferable to keep temperature in the range of 30 degreeC-400 degreeC.

Here, it is preferable to use a downstream method instead of a bias electric field application method. When using an oxygen plasma using the bias electric field application method, the insulating film 109 is induced by inducing unwanted physical etching such as sputtering. This is because the selectivity with and other films can be reduced.

As shown in FIG. 2E, the capping insulation layer 110 is removed through a polishing process such as a front etch (or a blanket etch back) or a CMP. At this time, a portion of the upper layer of the insulating layer 109 is removed to sufficiently secure the upper width of the second open part 115, and then a cleaning process is performed to remove residues on the bottom surface of the second open part 115.

When etching the entire surface, a gas containing florin (Fluorine) is used, and a diluted buffered oxide etchant (Dilute Buffered Oxide Etchant) is used.

Meanwhile, a heat treatment process such as baking or annealing or a cleaning process by wet chemical may be further performed before the capping insulating layer 110 is removed.

Subsequently, as shown in FIG. 2F, a conductive material such as polysilicon or tungsten is deposited to electrically connect with the source / drain region 108 through the second open portion 115, and then CMP or local front etching. A plurality of conductive connecting portions 116 are isolated from each other through. Herein, the connection part 116 includes a plug or a contact pad.

As shown in FIG. 2G, the planarization film 117 is formed on the entire surface on which the connection part 116 is formed by a PMD film used for insulation and planarization before the wiring process, and then the connection part is formed by damascene or a conventional contact forming process. An open portion (not shown) that exposes 116 is formed, and then a conductive pattern 118 such as a metal wire electrically connected to the exposed connection portion 116 is formed.

As the planarization film 117, an oxide film-based material such as BPSG (Boro Phospho Silicate Glass) is used. The conductive pattern 118 includes a structure in which Cu, Al, Ti, TiN, Ta, TaN, polysilicon, or the like is singly or combined.

According to the present invention made as described above, the organic-based SOD film is applied and planarized, and when the open portion is formed by the SAC process, the CD at the top of the open portion is narrower than before, thereby increasing the spacing between the SAC and the SAC. As a result, the step and thickness of the photoresist pattern may be reduced during the photolithography process for forming the SAC pattern, thereby preventing the bridge of the photoresist pattern or the collapse of the pattern, and securing DICD and overlay margin. Can be. In addition, the present invention has been found to increase the FICD margin during the etching process for forming the SAC pattern, thereby facilitating the ultra fine wiring process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, the metal wiring forming process is taken as an example, but it is applicable to various conductive patterns having the structure shown in the embodiment.

The present invention as described above has the following effects in the manufacture of an ultra-high density semiconductor device having a minimum line width of 100 nm or less.

end). Since the thickness of the hard mask is reduced when the pattern of the gate electrode is formed, the aspect ratio is reduced between the gate electrodes, thereby suppressing the generation of voids during the deposition of the insulating layer, and improving the gap-fill characteristics.

I). In the photolithography process for the SAC etching process, the width of the photoresist pattern can be increased and the thickness can be decreased, so that the step difference of the photoresist pattern can be reduced, which greatly reduces the bridge bridge or collapse phenomenon, and the DICD margin and over The lay margin can be secured to form a reliable SAC pattern.

All). All). By etching only a portion of the organic SOD film and selectively removing only the organic SOD film by oxygen plasma during the etching process for forming the SAC pattern, the attack of the gate hard mask can be prevented and the CD bias can be reduced. This can reduce the occurrence of short-circuit or leakage current between the connecting portion and the gate conductive film during the subsequent connecting portion forming process, thereby improving the yield.

As a result, in the planarization of the insulating film for interlayer insulation and the SAC formation scheme, the reliability is improved, and the yield of the semiconductor device is improved and the degree of integration can be improved.

1A and 1B are cross-sectional views showing a wiring forming process of a MOSFET device according to the prior art.

2A to 2G are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on main parts of drawing

100: substrate 101: liner

102: field oxide film 103: well

104: gate insulating film 105: conductive film

106: hard mask 107: spacer

108: source / drain region 109: insulating film

110: capping insulating film 114: CO ₂

115: second open portion

Claims (13)

Forming first and second conductive patterns having a predetermined distance on the substrate; Forming an insulating film for an interlayer insulating film on the entire surface including the first and second conductive patterns; Forming a capping insulating film on the insulating film; Forming a photoresist pattern for a self-aligned contact process; Etching the capping insulating layer using the photoresist pattern as an etch mask, and subsequently etching the insulating layer to near the upper portions of the first and second conductive patterns to form a first open portion; Removing the photoresist pattern; Selectively etching the remaining portion of the insulating layer exposed through the first open portion to form a second open portion exposing the substrate between the first conductive pattern and the second conductive pattern; And Removing the capping insulating layer Semiconductor device manufacturing method comprising a. The method of claim 1, The insulating film is a semiconductor device manufacturing method characterized in that it comprises an organic SOD (Spin On Dielectric) film containing a hydro-carbon component. The method of claim 2, And the insulating film includes at least 5w% of the hydro-carbon component. The method of claim 2, The forming of the second open portion, the semiconductor device manufacturing method comprising using an oxygen plasma. The method of claim 4, wherein In the forming of the second open portion, a semiconductor device manufacturing method using a downstream method using a gas containing any one of O ₂ , O ₃ , CO ₂ or N ₂ O. The method of claim 5, Forming the second open portion, the semiconductor device manufacturing method, characterized in that carried out in a temperature range of 30 ℃ to 400 ℃. The method of claim 1, After the step of forming the insulating film, the semiconductor device manufacturing method characterized in that it further comprises a heat treatment step performed at a temperature range of 400 ℃ to 1000 ℃ for the film densification of the insulating film. The method of claim 1, The capping insulating film is a semiconductor device manufacturing method characterized in that it comprises an oxide film series or a nitride film series. delete delete The method of claim 1, The first and second conductive patterns are semiconductor device manufacturing method, characterized in that the gate electrode pattern. The method of claim 1, After removing the capping insulating layer, forming a connection part electrically connected to the substrate through the second opening part. The method of claim 1, And removing a portion of the insulating film to secure a width of an upper portion of the second opening part.