KR100534205B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a semiconductor device and a method of manufacturing the same. According to this, an etch groove is formed in a portion of the surface of the semiconductor substrate, a gate oxide film and a gate electrode are formed on the bottom surface of the etch groove, a spacer is formed in the empty space of the etch groove, and a low concentration source / drain is formed in the semiconductor substrate under the spacer. A region is formed and integrally connected thereto, and a high concentration source / drain region is formed on the semiconductor substrate outside the spacer.

Therefore, even though the gate electrode length is reduced by increasing the junction level of the high concentration source / drain regions of the source / drain regions of the LDD structure with respect to the bottom of the gate oxide layer, punchthrough occurs due to the depletion layer expansion of the high concentration source / drain regions. In this way, the punch-through margin can be increased, and the ion implantation process for forming low concentration and high concentration source / drain regions can be easily controlled.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same by increasing the junction level of a high concentration source / drain region of the source / drain region of the LDD structure to increase the punch-through margin will be.

In general, in order to improve the high speed of the CPU, the gate electrode length of the MOS transistor constituting the CPU has been reduced. As the gate electrode length is reduced, the effective channel length has also been shortened, and the manufacturing process of the MOS transistors is becoming more difficult. Currently, the key to improving the speed of various semiconductor devices, including a central processing unit, depends on how much the gate electrode of the MOS transistor can be shortened without the manufacturing process.

In the conventional MOS transistor, as shown in FIG. 1, an isolation layer 11 is known in the field region of the semiconductor substrate 10 to limit the active region of the p-type semiconductor substrate 10. Formed by a process, a lamination structure of the gate oxide film 13 and the gate electrode 15 and a sidewall spacer 17 are formed on the central portion of the surface of the semiconductor substrate 10 in the active region, and the gate electrode 15 is formed. Source / drain regions 19 of the LDD structure are spaced apart from each other on the active substrate semiconductor substrate 10, and are exposed on the exposed surfaces of the source / drain regions 19 and the exposed surfaces of the gate electrodes 15. The salicide layer 20 is formed.

Here, the salicide layer 20 is made of a silicon compound such as Ti and Co to reduce the metal contact resistance of the gate electrode 15 and the source / drain region 19.

In the conventional MOS transistor configured as described above, an n + type source / drain region 19 is typically located below the surface of the semiconductor substrate 10 and the bottom surface of the gate oxide film 13 is positioned on the surface of the semiconductor substrate 10. do. That is, the junction of the high concentration source / drain regions is located considerably lower than the bottom of the gate oxide film 13.

However, in the conventional MOS transistor, since the junction of the high concentration source / drain region is located substantially lower than the bottom surface of the gate oxide film 13, a high concentration of impurities are ionized to form an n + type source / drain region in the source / drain region 19. In the heat treatment after implantation, the junction of the n + type source / drain regions tend to extend laterally and be connected to each other. In addition, when an electric field is applied to the source / drain 19 after the MOS transistor is normally completed, a depletion layer is formed around the n + type source / drain region. In severe cases, a depletion layer is formed around the n + type source / drain region. Depletion layers are likely to be connected to each other.

As a result, in the related art, as the gate electrode of the MOS transistor is reduced in length, punch through easily occurs due to the expansion of the depletion layer of the source / drain regions, thereby reducing the punch through margin for preventing punch through. And making it difficult to control the conditions of the ion implantation process for forming a high concentration source / drain region.

Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which reduce the length of the gate electrode and increase the punch-through margin of the source / drain regions.

The semiconductor device according to the present invention for achieving the above object is

First conductive semiconductor substrate:

An isolation layer formed in the field region of the semiconductor substrate to isolate the active region of the semiconductor substrate;

A gate oxide layer selectively formed on a bottom surface of an etch groove in which a portion of a surface of the semiconductor substrate of the active region is etched;

A gate electrode formed on the gate oxide film;

A spacer formed in the sidewall of the gate electrode while being filled in the etching groove; And

And a second conductivity type source / drain region having an LDD structure formed on the semiconductor substrate of the active region, spaced apart from each other with the gate electrode interposed therebetween.

Preferably, the source / drain region may include a low concentration source / drain region formed in an active region below the bottom of the etch groove, and a high concentration source / drain region integrally connected to the source / drain region formed on a semiconductor substrate outside the side surface of the etch groove. Include. In addition, the spacer may be formed of a nitride film.

In addition, the method for manufacturing a semiconductor device according to the present invention for achieving the above object is

Forming an isolation layer in the field region of the semiconductor substrate to isolate the active region of the first conductivity type semiconductor substrate;

Selectively forming an etching groove in the semiconductor substrate of the active region;

Forming a gate oxide layer only on a bottom surface and a side surface of the etch groove, and filling a polysilicon layer only on the etch groove to planarize to the same level as the surface of the semiconductor substrate;

Forming the polysilicon layer in a pattern of a gate electrode;

Low concentration ion implantation of a second conductivity type impurity on the entire surface of the semiconductor substrate using a pattern of a photoresist film having an opening exposing the active region and a pattern of the gate electrode as a mask layer;

Forming a spacer on the pattern sidewall of the gate electrode and leaving only the etching groove;

Implanting a high concentration of ion-implanted impurities into the semiconductor substrate by using a pattern of a photosensitive film having an opening exposing the active region, a pattern of the gate electrode, and the spacer as a mask layer; And

And heat-treating the high concentration and low concentration ion implanted impurities to form source / drain regions of the LDD structure.

Preferably, the source / drain regions are integrally connected to the low concentration source / drain regions on the semiconductor substrate under the bottom of the etch groove, and the low concentration source / drain regions are integrally connected to the semiconductor substrate on the outer side of the etch groove. It is formed as a drain region.

In addition, the forming of the polysilicon layer in the pattern of the gate electrode

Forming a pattern of an etch stop layer on the isolation layer to prevent etching of the isolation layer;

Forming an etch mask layer of the polysilicon layer on the polysilicon layer in the same pattern as the pattern of the gate electrode, and forming a spacer of the etch mask layer on a pattern sidewall of the etch stop layer; And

Forming the polysilicon layer as a pattern of a gate electrode by etching back the polysilicon layer using the pattern of the etch stop layer, the pattern of the etch mask layer, and the spacer as a mask layer.

Forming the etching mask layer in the same pattern as the pattern of the gate electrode and forming a spacer of the etching mask layer is

Stacking an etch mask layer on the semiconductor substrate including the pattern of the etch stop layer;

Forming a pattern of a photoresist layer corresponding to the pattern of the gate electrode on a predetermined region of the etch mask layer; And

Anisotropically etching the etch mask layer using the pattern of the photoresist layer to form the etch mask layer in the same pattern as the pattern of the gate electrode, and forming a spacer of the etch mask layer.

The etch stop layer and the etch mask layer are formed of an insulating film of the same material. In addition, the etch stop layer and the etch mask layer is formed of a nitride film. Further, the etch stop layer and the etch mask layer are formed of a nitride film made of SiON. In addition, the etch stop layer may be formed of a nitride film of any one of SiON and SiN material.

Preferably, the spacer is formed of a nitride film. The method may further include ion implanting a second conductivity type impurity between forming the gate oxide layer and forming the etch groove to form a channel in the semiconductor substrate under the bottom of the etch groove. Forming a salicide layer on surfaces of the gate electrode and the source / drain regions.

Therefore, according to the present invention, the punch-through margin is increased by increasing the junction level of the high concentration source / drain regions of the MOS transistor of the LDD structure.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part same as a conventional part.

2 is a cross-sectional structural view showing a semiconductor device according to the present invention.

As shown in FIG. 2, the isolation layer 11 is formed in the field region of the semiconductor substrate 10 by an STI process to define the active region of the p-type semiconductor substrate 10, and the semiconductor substrate of the active region is formed. An etching groove 26 is formed in the center of the surface of the etching area 10, and a lamination structure of the gate oxide film 25 and the gate electrode 27 is formed in the center of the bottom surface of the etching groove 26, and the bin in the etching groove 26 is formed. The spacer 33 is filled in the space, and the n + type source / drain region 37a is formed on the semiconductor substrate 10 of the active region, spaced apart with the etching groove 26 therebetween, and the gate oxide layer 25 is interposed therebetween. An n-type source / drain region 37b is formed on the semiconductor substrate 10 below the bottom of the etch groove 26 and spaced apart from each other, and is integrally connected to the n + type source / drain region 37a. The salicide layer 40 is formed on the exposed surfaces of the gate electrode 25 and the source / drain regions 37a, respectively.

Here, the spacer 33 is made of an insulating film such as a nitride film. P type may be used as the first conductivity type and n type may be used as the second conductivity type.

In the semiconductor device of the present invention configured as described above, the source / drain region 37b is disposed below the surface of the semiconductor substrate 10 and the gate oxide film 25 is located on the bottom surface of the etch groove. Unlike this conventional art, it is formed relatively much higher than the junction of the source / drain 19 of FIG.

Therefore, in the present invention, even though the gate electrode length of the MOS transistor having the LDD structure is reduced, the punch-through phenomenon due to the expansion of the depletion layer of the high concentration source / drain region is unlikely to occur, so that the punch-through margin is increased and further, the low concentration and high concentration source / It is easy to control the conditions of the ion implantation process for forming the drain region.

A method of manufacturing a semiconductor device according to the present invention configured as described above will be described in detail with reference to FIGS. 3 to 12.

3 to 12 are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device according to the present invention.

As shown in FIG. 3, first, the isolation layer 11 is formed by an STI process known in the field region of the semiconductor substrate 10 in order to limit the active region of the semiconductor substrate 10 of the first conductivity type such as the p-type. ).

Then, a pattern of the photoresist film 22 is formed on the semiconductor substrate 10 so that the opening is located on the active region where the etching groove 21 is to be formed, and the exposed active region in the opening is desired by using the pattern as a mask layer. Anisotropically etch by depth. Of course, the depth of the etching groove 21 is preferably formed to be shallower than the depth of the etching groove for the isolation layer (11).

As shown in FIG. 4, after the pattern of the photoresist layer 22 is removed, the pattern of the photoresist layer 24 is positioned so that an opening is located on the semiconductor substrate 10 region of the entire active region including the etch groove 21. Is formed on the semiconductor substrate 10. Next, in order to form a channel in the semiconductor substrate 10 under the bottom of the etch groove 21, a second conductivity such as n-type is formed on the entire surface of the semiconductor substrate 10 using the pattern of the photosensitive film 24 as a mask layer. Ion implantation of the type impurity.

As shown in FIG. 5, after the pattern of the photoresist layer 24 is removed, a gate insulating film, for example, a gate oxide film 25 is formed on the entire surface of the semiconductor substrate 10, and a high concentration for the gate electrode is formed thereon. The polysilicon layer 27 is laminated to a thickness thick enough to completely fill the etching groove 21.

As illustrated in FIG. 6, the semiconductor substrate 10 outside the etch groove 21 may be formed by using the chemical mechanical polishing process, for example, to form the polysilicon layer 27 and the gate oxide layer 25. The polysilicon layer 27 is left in the etch groove 21 only by polishing until the surface of the etch surface is exposed, leaving no polysilicon layer 27 and the gate oxide film 21 on the active region outside the etch groove 21. .

At this time, the surface of the polysilicon layer 27 remaining in the etching groove 21 is planarized to the same level as the surface of the semiconductor substrate 10 outside the etching groove 21.

As shown in FIG. 7, next, in order to prevent the etching of the isolation layer 11 from occurring when the pattern of the polysilicon layer for the gate electrode is formed, an anti-etching film 29, for example, a SiON material After the nitride film is laminated, a pattern of the etch stop layer 29 is formed on the isolation layer 11 using a photolithography process. Here, a nitride film made of SiN material may be used as the etch stop layer 29 instead of a nitride film made of SiON material.

Subsequently, an etching mask layer 31 of the polysilicon layer 27, for example, a nitride film made of SiON material is stacked on the resulting structure, and a gate electrode is formed on the etching mask layer 31 in the region where the pattern of the gate electrode is to be formed. The pattern of the photosensitive film 32 corresponding to the pattern of is formed.

On the other hand, the thickness of the etch stop layer 29 and the etching mask layer 31 is only the polysilicon layer 27 having the pattern of the gate electrode in the etch back process of the step shown in FIG. It is preferable that both the polysilicon layer 27 and the gate oxide film 25 in the remaining region be removed.

As shown in FIG. 8, the polycrystalline silicon layer under the pattern of the photosensitive film 32 is then anisotropically etched using the pattern of the photosensitive film 32 as a mask layer until the surface of the polycrystalline silicon layer 27 is exposed. The etching mask layer 31 is formed on the sidewalls of the etching prevention layer 29 and the etching mask layer 31 is formed on the pattern 27. Then, the pattern of the photosensitive film 32 is removed.

As shown in FIG. 9, the polysilicon layer 27 in the exposed region is then used under the etch mask layer 31 by using the remaining etch mask layer 31 and the etch stop layer 29 as the etch mask layer. The polysilicon layer 27 having the pattern of the gate electrode is formed by etching by the etch back process until the polysilicon layer 27 is exposed.

At this time, the etching selectivity of the polysilicon layer 27, the semiconductor substrate 10, and the gate oxide film 25 is appropriately selected, except for the gate oxide film 25 under the polysilicon layer 27 having the pattern of the gate electrode. The gate oxide layer is etched completely, and the semiconductor substrate 10 in the exposed region is also etched together to form an etching groove 26.

As shown in FIG. 10, a pattern of the photosensitive film 24 is formed on the semiconductor substrate 10 so that the opening is located on the entire area of the active region. Next, the pattern of the photoresist layer 24 and the gate electrode are formed to form a low concentration source / drain region of the LDD structure on the semiconductor substrate 10 under the bottom surface of the etching groove 26 with the gate oxide layer 25 interposed therebetween. By using the pattern (27) as a mask layer, ion-implanted second conductivity type impurities such as n-type are implanted into the entire surface of the semiconductor substrate 10 in the active region.

As shown in FIG. 11, an insulating film, for example, a nitride film 33, is then etched to remove the pattern of the photoresist film 32 and then form a spacer on the sidewall of the gate electrode 27 on the resulting structure. Laminate to thick enough to completely fill (26). Thereafter, the nitride film 33 is etched using the etch back process until the upper surface of the polysilicon layer 27 is exposed, so that the nitride film 33 for the sidewall spacer of the gate electrode 27 is formed only in the etching groove 26. Leave

As shown in FIG. 12, after the pattern of the photosensitive film 34 is formed on the semiconductor substrate 10 such that the opening is positioned in the active region of the resultant structure, the pattern of the photosensitive film 34 and the nitride film 33 and the polycrystal are formed. Using the silicon layer 27 as a mask layer, ion implantation with high concentration of n-type impurities for a high concentration source / drain region is performed.

Subsequently, after removing the pattern of the photoresist layer 34, the impurities ion-implanted are diffused using a heat treatment process to form the source / drain region 37 of the LDD structure. Accordingly, in the present invention, the junction of the source drain region 37b can be formed relatively high, unlike the conventional art, when the gate oxide film 25 is referenced.

Finally, the salicide layer 40 is formed on the exposed surfaces of the gate electrode 27 and the source / drain regions 37 to complete the semiconductor device as shown in FIG. 2.

As described above, the semiconductor device and the method of manufacturing the same according to the present invention form an etch groove on a portion of the surface of the semiconductor substrate, form a stacked structure of a gate oxide film and a gate electrode on the bottom surface of the etch groove, A spacer is formed, a low concentration source / drain region is formed in the semiconductor substrate under the spacer, and is integrally connected thereto, and a high concentration source / drain region is formed in the semiconductor substrate outside the spacer.

Therefore, the present invention suppresses the punch-through generation caused by the depletion layer expansion of the high concentration source / drain region by reducing the gate electrode length by increasing the junction level of the high concentration source / drain region of the LDD structure relatively. It is possible to easily control the ion implantation process to increase the margin and to form low concentration and high concentration source / drain regions.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

1 is a vertical cross-sectional view showing a semiconductor device according to the prior art.

2 is a vertical cross-sectional view showing a semiconductor device according to the present invention.

3 to 12 are vertical cross-sectional view showing a method of manufacturing a semiconductor device according to the present invention.

Claims (15)

First conductive semiconductor substrate: An isolation layer formed in the field region of the semiconductor substrate to isolate the active region of the semiconductor substrate; A gate oxide layer selectively formed on a bottom surface of an etch groove in which a portion of a surface of the semiconductor substrate of the active region is etched; A gate electrode formed on the gate oxide film; A spacer formed in the sidewall of the gate electrode while being filled in the etching groove; And And a second conductivity type source / drain region having an LDD structure formed on the semiconductor substrate of the active region, spaced apart from the gate electrode. The semiconductor device of claim 1, wherein the source / drain region comprises a low concentration source / drain region formed in an active region below the bottom of the etch groove, and a high concentration source / drain formed integrally with the semiconductor substrate outside the side surface of the etch groove. A semiconductor device comprising a drain region. The semiconductor device according to claim 1, wherein said spacer is made of a nitride film. The semiconductor device of claim 1, further comprising a salicide layer formed on an exposed surface of the gate electrode and the source / drain region. Forming an isolation layer in the field region of the semiconductor substrate to isolate the active region of the first conductivity type semiconductor substrate; Selectively forming an etching groove in the semiconductor substrate of the active region; Forming a gate oxide layer only on a bottom surface and a side surface of the etch groove, and filling a polysilicon layer only on the etch groove to planarize to the same level as the surface of the semiconductor substrate; Forming the polysilicon layer in a pattern of a gate electrode; Low concentration ion implantation of a second conductivity type impurity on the entire surface of the semiconductor substrate using a pattern of a photoresist film having an opening exposing the active region and a pattern of the gate electrode as a mask layer; Forming a spacer on the pattern sidewall of the gate electrode and leaving only the etching groove; Implanting a high concentration of ion-implanted impurities into the semiconductor substrate by using a pattern of a photosensitive film having an opening exposing the active region, a pattern of the gate electrode, and the spacer as a mask layer; And And heat-treating the high concentration and low concentration ion implanted impurities to form a source / drain region of an LDD structure. The semiconductor device of claim 5, wherein the source / drain regions are formed on the semiconductor substrate under the bottom of the etch groove, and the source / drain regions are formed on the semiconductor substrate, and the semiconductors are integrally connected to the low concentration source / drain regions. A method for manufacturing a semiconductor device, comprising forming a high concentration source / drain region on a substrate. The method of claim 5, wherein the polysilicon layer is formed in a pattern of a gate electrode. Forming a pattern of an etch stop layer on the isolation layer to prevent etching of the isolation layer; Forming an etch mask layer of the polysilicon layer on the polysilicon layer in the same pattern as the pattern of the gate electrode, and forming a spacer of the etch mask layer on a pattern sidewall of the etch stop layer; And Forming the polysilicon layer in a pattern of a gate electrode by etching back the polysilicon layer using the pattern of the etch stop layer, the pattern of the etch mask layer, and the spacer as a mask layer; Manufacturing method. The method of claim 7, wherein the etching mask layer is formed in the same pattern as the pattern of the gate electrode and the spacer of the etching mask layer is formed. Stacking an etch mask layer on the semiconductor substrate including the pattern of the etch stop layer; Forming a pattern of a photoresist layer corresponding to the pattern of the gate electrode on a predetermined region of the etch mask layer; And Anisotropically etching the etch mask layer by using the pattern of the photoresist layer as a mask to form the etch mask layer in the same pattern as the pattern of the gate electrode and to form a spacer of the etch mask layer. A method of manufacturing a semiconductor device. The method of claim 7 or 8, wherein the etch stop layer and the etch mask layer are formed of an insulating film of the same material. 10. The method of claim 9, wherein the etch stop layer and the etch mask layer are formed of a nitride film. The method of claim 9, wherein the etch stop layer and the etch mask layer are formed of a nitride film made of SiON. 10. The method of claim 8, wherein the etch stop layer is formed of a nitride film of any one of SiON and SiN. The method of manufacturing a semiconductor device according to claim 5, wherein the spacer is formed of a nitride film. 6. The method of claim 5, further comprising ion implanting a second conductivity type impurity between forming the gate oxide layer and forming the etch groove to form a channel in the semiconductor substrate under the bottom of the etch groove. Method for manufacturing a semiconductor device, characterized in that. The method of claim 5, further comprising forming a salicide layer on surfaces of the gate electrode and the source / drain regions.