KR100533721B1 - Plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel which can improve the image quality while preventing erroneous discharge of adjacent adjacent cells in driving the plasma display panel.

The present invention provides a plasma display panel having a partition wall for partitioning discharge cells, wherein an edge of the partition wall is lower than a center portion of the partition wall.

By such a configuration, the present invention can prevent erroneous discharge between adjacent cells by forming the upper end of the horizontal partition wall by rounding or chamfering. In addition, according to the present invention, the lower end portion of the horizontal barrier rib near the address electrode is made of a material having a low dielectric constant, thereby preventing cross talk between adjacent cells and improving image quality.

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of preventing erroneous discharge of adjacent adjacent cells and improving image quality in driving a plasma display panel.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs"), and electroluminescence (Electro). -Luminescence (EL) display.

Among them, PDP is a display device using gas discharge, which has the advantage of easy manufacturing of large panels. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP is formed on a first electrode 12Y and a second electrode 12Z formed on an upper substrate 10, and on a lower substrate 18. The address electrode 20X is provided.

The first and second electrodes 12Y and 12Z are made of a transparent material to transmit light supplied from the discharge cells. Bus electrodes 13Y and 13Z formed of a metal material are formed on the rear surfaces of the first electrode 12Y and the second electrode 12Z to be parallel to the first and second electrodes 12Y and 12Z. The bus electrodes 13Y and 13Z are used to supply driving signals to the first and second electrodes 12Y and 12Z having high resistance values.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the first electrode 12Y and the second electrode 12Z side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the first electrode 12Y and the second electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells.

The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert gas such as He + Ne, He + Xe or He + Ne + Xe is injected into the discharge space provided between the upper and lower plates and the partition wall.

In the conventional PDP, the first electrode 12Y and the second electrode 12Z are formed to face each other in each of the discharge cells 1 as shown in FIG. 2. The reset pulse, the scan pulse and the first sustain pulse are supplied to the first electrode 12Y. The second sustain pulse is supplied to the second electrode 12Y.

The discharge cells are initialized when the reset pulse is supplied to the first electrode 12Y. When scan pulses are supplied to the first electrode 12Y, data pulses synchronized with the scan pulses are supplied to the address electrode 20X. At this time, address discharge occurs in the discharge cells supplied with the scan pulse and the data pulse.

After the address discharge is generated in the discharge cells, the first and second sustain pulses are alternately supplied to the first electrode 12Y and the second electrode 12Z. When the first and second sustain pulses are supplied to the first electrode 12Y and the second electrode 12Z, the sustain discharge occurs in the discharge cells in which the address discharge has occurred. In this sustain discharge, the discharge time is determined according to the gray scale value, so that an image corresponding to the gray scale value is displayed.

Meanwhile, in the conventional PDP, the first electrode 12Y and the second electrode 12Z are formed to face each other with a large area in the discharge cells. As described above, when the first electrode 12Y and the second electrode 12Z have a large area, a large amount of power is consumed, thereby lowering the discharge efficiency of the PDP. In order to overcome this disadvantage, the PDP as shown in FIG. 3 has been proposed.

Referring to FIG. 3, the PDP according to another exemplary embodiment has a delta structure in which discharge cells positioned adjacent to each other up and down form one pixel. In other words, according to another exemplary embodiment of the present invention, the PDP includes an R subpixel and a B subpixel positioned in an nth line (n is a natural number of 1 or more), and a G subpixel positioned in an n + 1 or n-1 line. Form one pixel.

The PDP according to another exemplary embodiment of the present invention has the address electrode 40X, the first and second electrodes 32Y and 32Z formed in a direction crossing the address electrode 40X, and the first and second electrodes ( And first and second bus electrodes 33Y and 33Z formed on 32Y and 32Z.

The first and second electrodes 32Y and 32Z are formed from the first and second main electrodes 32a and 32c formed orthogonal to the address electrode 40X, and from the first and second main electrodes 32a and 32c. The first and second auxiliary electrodes 32b and 32d extend in the same direction as the address electrode 40X.

The first auxiliary electrode 32b is formed on both sides of the first main electrode 32a, and the second auxiliary electrode 32d is formed on both sides of the second main electrode 32c similarly to the first auxiliary electrode 32b. .

The address electrode 40X includes an address main electrode 40a having a line shape in a direction orthogonal to the first and second main electrodes 32a and 32b, and the address main electrode in a discharge cell forming one pixel. The address auxiliary electrode 40b extends by a predetermined width in a direction orthogonal to 40a.

In addition, as shown in FIG. 4, the second auxiliary electrodes 32b and the second auxiliary electrodes 32b alternately extended to the first main electrode 32a are disposed on the upper surface of the PDP according to another exemplary embodiment. The first dielectric layer 44b in which the upper dielectric layer and the passivation layer are sequentially stacked on the front surface of the upper plate to cover the upper and lower surfaces thereof is provided.

In the first dielectric layer 44b, wall charges generated during plasma discharge through the upper dielectric layer accumulate, and damage of the first dielectric layer due to sputtering generated during plasma discharge through the protective film is prevented and the emission efficiency of secondary electrons is improved. Raised.

The lower surface of the PDP covers the first to third address electrodes 42a, 42b and 42c formed to be orthogonal to the first and second electrodes 32Y and 32Z, and the lower plate front to cover the address electrodes 42a, 42b and 42c. A second dielectric layer 44a formed on the second dielectric layer 44a and a horizontal partition wall 46b formed on the bottom surface in the same direction as the first to third address electrodes 42a, 42b, and 42c. Phosphors (not shown) are formed on the surfaces of the second dielectric layer 44a and the horizontal partition wall 46b. The first and second address electrodes 42a and 42c formed at both sides of the first to third address electrodes 42a, 42b, and 42c are formed from the first and second main electrodes 32Y and 32Z from the address main electrode 40a. The address auxiliary electrode 40b extending in the direction is shown, and the third address electrode 42b represents the address electrode main electrode 40a. The horizontal partition wall 46b is formed in parallel with the first to third address electrodes 42a, 42b, and 42c to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells.

The horizontal partition wall 46b of the PDP according to another conventional embodiment has a rectangular shape on the upper part of the partition wall 46.

5 to 12 are diagrams showing an equipotential surface when a specific voltage is applied to a discharge cell according to the PDP shown in FIG. 4.

5 through 12, the width of the second auxiliary electrodes 32b formed on the upper plate of the PDP is 185 μm, and the widths of the first and third address electrodes 42a and 42c formed on both sides of the PDP are 150 μm. . The width of the second address electrode 42b formed between the first and third address electrodes 42a and 42c and not including the address auxiliary electrode 40b is 70 μm. The height of the horizontal partition wall 46b formed in the closed form in the lower board is 120 micrometers, and the dielectric constant of the horizontal partition wall 46b is 12. The dielectric layer formed on each of the upper and lower electrodes was 30 탆. In this case, the second auxiliary electrodes 32b include a second auxiliary first electrode 32b1 formed on the left side and a second auxiliary second electrode 32b2 formed on the right side of the horizontal partition wall 46b.

5 to 12, when 0 V is applied, no voltage is applied, and 1 V means applying a predetermined voltage, and -1.2 V indicates an opposite polarity, and the absolute magnitude of the voltage is also larger than 1 V. Means that.

5 to 7, 0V, that is, no voltage is applied to the second auxiliary first electrode 32b1, the first and third address electrodes 42a and 42c of the PDP, and only to the second address electrode 42b. A voltage of 1V is applied. At this time, the discharge cells including the first and third address electrodes 42a and 42c are non-illuminated cells, and if such non-illuminated cells are turned on, it is considered that erroneous discharge has occurred.

5 and 6, when a data voltage is applied to the second address electrode 42b, the maximum electric field of the non-lighting cell including the first and third address electrodes 42a and 42c (the maximum electric field is the partition wall 66). Is formed between the top of the first dielectric layer and the first dielectric layer) in the case of FIG. 6 (Emax = 1.55E-2) where an air gap exists between the horizontal partition wall 46b and the first dielectric layer 44b. It has a larger value than that of FIG. 5 (Emax = 8.85E-3). As a result, when there is an air gap between the horizontal partition wall 46b and the first dielectric layer 44b, there is a high probability of false discharge.

FIG. 7 illustrates a case in which an air gap is larger between the horizontal partition wall 46b and the first dielectric layer 44b than in FIG. 6. At this time, the maximum electric field (Emax = 1.48E-2) of the non-illuminated cell in FIG. 7 does not change significantly compared to the case of FIG. 6 (Emax = 1.55E-2). In FIG. 7, the vertical direction of the equipotential surface formed between the horizontal partition wall 46b and the first dielectric layer 44a is the direction of the electric field. In this case, the electric field in the air gap I moves the charged particles upward or downward depending on the polarity of the charged particles.

6 and 7, 0V, that is, no voltage is applied to the second auxiliary first electrode 32b1, the second auxiliary second electrode 32b2, and the third address electrode 42c of the PDP. A data voltage of 1V is applied to the two address electrodes 42a and 42b. 6 illustrates a case where there is no air gap between the horizontal partition wall 46b and the first dielectric layer 44b, and FIG. 7 illustrates a case where there is an air gap between the horizontal partition wall 46b and the first dielectric layer 44b. .

When comparing the intensity of the maximum electric field induced in the non-lighting cell including the third address electrode 42c in FIGS. 6 and 7, as shown in FIGS. 3 and 4, that is, in FIG. It can be seen that the intensity of the electric field is greater than that of 1.48E-2) without the air gap (Emax = 8.85E-3).

8 and 9 show that no voltage is applied to the second auxiliary first electrode 32b1, the second auxiliary second electrode 32b2, and the third address electrodes 42b and 42c of the PDP. A data voltage of 1V is applied to the address electrode 42a. FIG. 8 shows an equipotential surface when there is no air gap between the horizontal partition wall 46b and the first dielectric layer 44b, and the intensity of the maximum electric field induced by the non-lighting cell including the third address electrode 42c (Emax). ) Is around 9.02E-3. FIG. 9 shows an equipotential surface when the air gap is 25 μm between the horizontal partition wall 46b and the first dielectric layer 44b, and the intensity of the maximum electric field induced in the non-lighting cell including the third address electrode 42c. (Emax) is about 1.52E-2.

FIG. 10 illustrates that 0V, that is, no voltage is applied to the second auxiliary first electrode 32b1, the second auxiliary second electrode 32b2, and the second and third address electrodes 42b and 42c of the PDP. Only a data voltage of 1V is applied to 42a). In this case, FIG. 10 shows an equipotential surface when there is no air gap between the horizontal partition wall 46b and the first dielectric layer 44b, and the intensity of the maximum electric field induced in the non-lighting cell including the third address electrode 42c. (Emax) is about 9.4E-3.

5 to 9, the presence or absence of an air gap between the horizontal partition wall 46b and the first dielectric layer 44b becomes an important factor in relation to misdischarge. That is, it can be seen that the maximum electric field strength is large when there is an air gap. 6 and 7, it can be seen that the intensity of the maximum electric field near the air gap does not change greatly depending on the size of the air gap.

Referring to FIGS. 6, 7, and 9, the cross talk is performed by applying the voltage applied to the second address electrode 42b positioned at the lower half of the horizontal partition wall 46b to between the horizontal partition wall 46b and the first dielectric layer 44b. If there is an air gap, it is generated by forming a strong electric field near the air gap inside the discharge cell. 8 and 10, crosstalk is not generated when a voltage of 0 V is applied to the second address electrode 42b formed under the horizontal partition wall 46b.

11 is a view showing an equipotential surface when a specific voltage is applied to a discharge cell according to the prior art.

Referring to FIG. 11, a voltage of −1.2 V is applied to the second auxiliary first electrode 32 b1 and the second auxiliary second electrode 32 b2 of the PDP, and a voltage of 0 V is applied to the third address electrode 42 c. A data voltage of 1V is applied to the first and second address electrodes 42a and 42b. In this case, the discharge cell including the first address electrode 42a is a lit cell, and the cell including the third address electrode 42c is a cell that is not lit because no data voltage is applied. FIG. 11 also shows an equipotential surface when the air gap is 5 占 퐉 between the horizontal partition wall 46b and the first dielectric layer 44a.

FIG. 12 is a diagram illustrating a relative intensity of an electric field formed in the left and right discharge cells in FIG. 11.

Referring to FIG. 12, the intensity of the maximum electric field in the non-illuminated cell including the third address electrode 42c in the PDP is defined between the horizontal partition wall 46b and the first dielectric layer 44b as shown in FIG. 11. When the air gap is present and the upper portion of the horizontal partition wall 46b has a rectangular shape, the air gap is almost similar to the intensity of the maximum electric field of the lighting cell to which the data voltage is applied to the first address electrode 42a. In this case, the probability that the non-illuminated cell is turned on is increased, that is, a pulse applied to the column electrodes of the non-illuminated cells around the air gap forms a strong electric field around the air gap, causing unwanted discharge to deteriorate image quality. Will be.

Accordingly, an object of the present invention is to provide a plasma display panel which prevents erroneous discharge of neighboring adjacent cells in driving the plasma display panel.

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Another object of the present invention is to provide a plasma display panel capable of reducing crosstalk.

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In order to achieve the above object, the plasma display panel of the present invention is characterized in that the plasma display panel having a partition wall for partitioning the discharge cells, the edge of the partition wall is lower than the central portion of the partition wall.

The discharge cells of the plasma display panel are characterized in that the red, green and blue discharge cells are arranged in a delta type.

The partition wall may include a first partition wall in the plasma display panel; And a second partition vertically connected to the first partition.

At least a portion of the barrier rib in the plasma display panel is rounded at an upper end thereof.

At least a portion of the partition wall in the plasma display panel is characterized in that the upper edge is stepped.

At least a portion of the partition wall in the plasma display panel is characterized in that the upper edge is concave.

The plasma display panel includes first electrodes formed on a first substrate; Second electrodes formed on a second substrate facing the first substrate with a discharge space therebetween and intersecting the first electrodes; A first dielectric layer formed on the first substrate to cover the first electrodes; A protective film formed on the first dielectric layer; A second dielectric layer formed on the second substrate to cover the second electrodes; And a phosphor formed in the second dielectric layer and the partition wall.

In the plasma display panel, the first electrode may include a metal bus electrode; And a transparent electrode connected to the metal bus electrode and having a width greater than that of the metal bus electrode.

The transparent electrode in the plasma display panel and the main electrode portion; An auxiliary electrode extending from the main electrode portion toward the discharge cell; The auxiliary electrode is characterized in that it extends zigzag on both sides of the main electrode.

In the plasma display panel, the second electrode may include a main electrode; And an auxiliary electrode extending from both sides of the main electrode and at least partially overlapping the first electrode.

In the plasma display panel, the partition wall has a stripe shape, and an upper center portion thereof is convex.

In the plasma display panel, the partition wall has a stripe shape, and an upper edge thereof is stepped.

A plasma display panel according to an embodiment of the present invention is a plasma display panel having partition walls for partitioning discharge cells, wherein the partition walls are characterized in that the dielectric constant value is different.

In the plasma display panel, an edge of the barrier rib is lower than a central portion of the barrier rib.

The partition wall may include a first partition wall in the plasma display panel; And a second partition vertically connected to the first partition.

In the plasma display panel, any one of the first and second partitions has a lower dielectric constant value at a lower end thereof than the upper end thereof.

One of the first and second barrier ribs of the plasma display panel has a dielectric constant value lower than 12 at its lower end; The partition dielectric constant value of the other part except for the lower end is characterized in that 12 or more.

A plasma display panel according to an embodiment of the present invention has a plasma display panel having partition walls for partitioning discharge cells, the upper end of the partition wall facing the first substrate with an air gap therebetween; The air gap between the top edge of the partition and the first substrate is different from the air gap between the top center of the partition and the first substrate.

In the plasma display panel, the barrier rib is partially different in the dielectric constant value.

In the plasma display panel, an edge of the barrier rib is lower than a central portion of the barrier rib.

A plasma display panel according to an embodiment of the present invention has a plasma display panel having partition walls for partitioning discharge cells, wherein an upper end of the partition wall faces the first substrate with an air gap therebetween, and the partition wall is partially dielectric. The constant value is different, and the edge of the partition is lower than the center portion of the partition.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 13 to 19C.

Referring to FIG. 13, a plasma display panel (called a “PDP”) according to an exemplary embodiment of the present invention has a delta structure in which discharge cells positioned adjacent to each other up and down form one pixel. Has In other words, according to an embodiment of the present invention, the PDP may include an R subpixel and a B subpixel located in an nth line (n is a natural number of 1 or more), and a G subpixel located in an n + 1 or n-1th line. This forms one pixel.

As such, the PDP according to the embodiment of the present invention may include the first and second electrodes 52Y and 52Z formed in the direction intersecting the address electrode 60X on the lower plate, the address electrode 60X on the upper plate, First and second bus electrodes 53Y and 53Z are formed on the first and second electrodes 52Y and 52Z.

The first and second electrodes 52Y and 52Z are formed from the first and second main electrodes 52a and 52c formed orthogonal to the address electrode 60X, and from the first and second main electrodes 52a and 52c. First and second auxiliary electrodes 52b and 52d extending toward the discharge cell are provided.

The first auxiliary electrode 52b extends alternately or zigzag on both sides of the first main electrode 52a. In other words, if the first auxiliary electrode 62b intersecting with the n-th address electrode 60X is extended from the first side of the first main electrode 62a, the first intersecting electrode with the n + 1th address electrode 60X is intersected. The first auxiliary electrode 52b extends on the second side of the first main electrode 52a.

Like the first auxiliary electrode 52b, the second auxiliary electrode 52d is alternately extended on the first and second sides of the second main electrode 52c. In this case, the second main electrode 52c is formed to face the first main electrode 52a. In other words, if the first auxiliary electrode 52b crossing the nth address electrode 60X is extended from the first side of the first main electrode 52a, the second auxiliary electrode crossing the nth address electrode 60X is crossed. The electrode 52d extends on the second side of the second main electrode 52c.

The address electrode 60X includes an address main electrode 60a having a line shape in a direction orthogonal to the first and second main electrodes 52a and 52b, and the address main electrode 60 in a discharge cell forming one pixel. And an address auxiliary electrode 60b extending by a predetermined width in a direction orthogonal to 60a.

In addition, as shown in FIG. 14, the upper surface of the PDP according to the first embodiment of the present invention includes second auxiliary electrodes 52b and second auxiliary electrodes 52b alternately extended to the first main electrode 52a. The first dielectric layer 64b having the upper dielectric layer and the passivation layer sequentially stacked on the front surface of the upper plate to cover 52b).

In the first dielectric layer 64b, wall charges generated during plasma discharge through the upper dielectric layer accumulate, and damage to the upper dielectric layer due to sputtering generated during plasma discharge through the passivation layer, while increasing emission efficiency of secondary electrons. do.

The lower surface of the PDP covers the first to third address electrodes 62a, 62b, 62c and the address electrodes 62a, 62b, 62c formed to be orthogonal to the first and second electrodes 52Y, 52Z. And a second dielectric layer 64a formed in the barrier rib and partition walls 66 for partitioning the discharge cells.

 Phosphors (not shown) are formed on the surfaces of the second dielectric layer 64a and the horizontal partition wall 66b. The first and second address electrodes 62a and 62c formed at both sides of the first to third address electrodes 62a, 62b, and 62c are formed from the first and second main electrodes 52Y and 52Z from the address main electrode 60a. The address auxiliary electrode 60b extending in the direction, and the third address electrode 62b represents the address electrode main electrode 60a.

The partition 66 has a vertical partition 66a and a horizontal partition 66b vertically connected to the vertical partition 66a. The vertical partitions 66a are formed in a direction crossing the first to third address electrodes 62a, 62b and 62c, and the horizontal partitions 66b are formed on the first to third address electrodes 62a, 62b and 62c. In addition to being formed side by side, the upper portion of the horizontal partition wall 66b is formed to have a round shape. At this time, the horizontal partition 66b is formed in a round shape so that its upper center portion is convex. For this reason, the edge of the horizontal partition 66b becomes lower than the center part of the horizontal partition 66b.

The upper end of the partition 66 faces the upper plate with the air gap therebetween. Accordingly, the air gap between the upper edge of the horizontal partition 66b and the upper plate is different from the air gap between the upper center portion and the upper plate of the horizontal partition 66b.

Meanwhile, as shown in FIG. 15, the second auxiliary electrodes 52b and the second auxiliary electrodes 52b that are alternately extended to the first main electrode 52a are disposed on the upper surface of the PDP according to the second embodiment of the present invention. The first dielectric layer 64b having the upper dielectric layer and the passivation layer sequentially stacked on the front surface of the upper plate to cover 52b). In the first dielectric layer 64b, wall charges generated during plasma discharge through the upper dielectric layer accumulate, and damage to the upper dielectric layer due to sputtering generated during plasma discharge through the passivation layer, while increasing emission efficiency of secondary electrons. do.

The lower surface of the PDP covers the first to third address electrodes 62a, 62b, 62c and the address electrodes 62a, 62b, 62c formed to be orthogonal to the first and second electrodes 52Y, 52Z. And a second dielectric layer 64a formed in the barrier rib and partition walls 66 for partitioning the discharge cells.

 Phosphors (not shown) are formed on the surfaces of the second dielectric layer 64a and the horizontal partition wall 66b. The first and second address electrodes 62a and 62c formed at both sides of the first to third address electrodes 62a, 62b, and 62c are formed from the first and second main electrodes 52Y and 52Z from the address main electrode 60a. The address auxiliary electrode 60b extending in the direction, and the third address electrode 62b represents the address electrode main electrode 60a.

The partition 66 has a vertical partition 66a and a horizontal partition 66b vertically connected to the vertical partition 66a. The vertical partitions 66a are formed in a direction crossing the first to third address electrodes 62a, 62b and 62c, and the horizontal partitions 66b are formed on the first to third address electrodes 62a, 62b and 62c. In addition to being formed side by side and around the corner of the upper end of the horizontal partition wall (66b) is formed to be stepped or chamfered in about 20㎛. At this time, the upper edge of the horizontal partition wall 66b is stepped. The partition wall 66 prevents the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. At this time, the portion requiring stepping or chamfering is the partition portion in the direction perpendicular to the address electrode. For this reason, the edge of the horizontal partition 66b becomes lower than the center part of the horizontal partition 66b.

The upper end of the partition 66 faces the upper plate with the air gap therebetween. Accordingly, the air gap between the upper edge of the horizontal partition 66b and the upper plate is different from the air gap between the upper center portion and the upper plate of the horizontal partition 66b.

FIG. 16 is a diagram illustrating relative strengths of electric fields formed in left and right discharge cells when a data voltage is applied to an address electrode when the barrier rib structure is illustrated in FIGS. 14 and 15.

First, the widths of the second auxiliary electrodes 52b formed on the upper plate of the PDP shown in FIGS. 14 and 15 are 185 μm, and the widths of the first and third address electrodes 62a and 62c formed on both lower plates are 150. [Mu] m. The width of the second address electrode 62b formed between the first and third address electrodes 62a and 62c and not including the address auxiliary electrode 60b is 70 μm. The height of the partition wall 66 formed in a closed form on the lower plate is 120 µm, and the dielectric constant of the partition wall 66 is 12. Further, the first and second dielectric layers 64 formed on the electrodes of the upper and lower plates are 30 탆. In this case, the second auxiliary electrodes 52b may include a second auxiliary first electrode 52b1 formed on the left side and the second auxiliary second electrode 52b2 formed on the right side of the partition wall 66. The air gap between the transverse partition 66b and the first dielectric layer 64b is about 5 μm.

In addition, a voltage of −1.2 V is applied to the second auxiliary first electrode 52 b1 and the second auxiliary second electrode 52 b 2 of the PDP, and a voltage of 0 V is applied to the third address electrode 62 c. A data voltage of 1V is applied to the address electrodes 62b and 62c. In this case, the discharge cell including the first address electrode 62b is a lit cell, and the cell including the third address electrode 62c is a non-lighted cell because no data voltage is applied.

In this case, the intensity of the maximum electric field of the cell including the third address electrode 62c, that is, the non-lighting cell is the intensity of the maximum electric field of the cell including the first address electrode 62a to which the data voltage is applied, that is, the lit cell ( It can be seen that it is much smaller than (Emax) (reduced to about 1/2), thereby preventing the erroneous discharge with the neighboring adjacent cells. In other words, by forming the upper end portion of the horizontal partition wall 66b in a round shape or a step / chamfering shape, the intensity of the maximum electric field of the lit cell can be weakened to weaken the electric field concentration distribution.

Meanwhile, as illustrated in FIG. 17, second auxiliary electrodes 52b and second auxiliary electrodes 52b that are alternately extended to the first main electrode 52a are disposed on an upper surface of the PDP according to the third embodiment of the present invention. The first dielectric layer 64b having the upper dielectric layer and the passivation layer sequentially stacked on the front surface of the upper plate to cover 52b). In the first dielectric layer 64b, wall charges generated during plasma discharge through the upper dielectric layer accumulate, and damage to the upper dielectric layer due to sputtering generated during plasma discharge through the passivation layer, while increasing emission efficiency of secondary electrons. do.

The lower surface of the PDP covers the first to third address electrodes 62a, 62b, 62c and the address electrodes 62a, 62b, 62c formed to be orthogonal to the first and second electrodes 52Y, 52Z. And a second dielectric layer 64a formed in the barrier rib and partition walls 66 for partitioning the discharge cells.

Phosphors (not shown) are formed on the surfaces of the second dielectric layer 64a and the horizontal partition wall 66b. The first and second address electrodes 62a and 62c formed at both sides of the first to third address electrodes 62a, 62b, and 62c are formed from the first and second main electrodes 52Y and 52Z from the address main electrode 60a. The address auxiliary electrode 60b extending in the direction, and the third address electrode 62b represents the address electrode main electrode 60a.

The partition 66 has a vertical partition 66a and a horizontal partition 66b vertically connected to the vertical partition 66a. The vertical partitions 66a are formed in a direction crossing the first to third address electrodes 62a, 62b and 62c, and the horizontal partitions 66b are formed on the first to third address electrodes 62a, 62b and 62c. It is formed side by side.

In the present invention, the horizontal partition wall 66b is formed with different dielectric constants except for the lower end of the horizontal partition wall 66b and the lower end of the horizontal partition wall 66b adjacent to the second address electrode 62b. That is, the horizontal partition wall 66b is made of a material having a lower dielectric constant value than the upper end thereof. In FIG. 17, the dielectric constant value of the lower end of the horizontal partition wall 66b is 12 or less (for example, 1 (dielectric constant of air) = 1), and the dielectric constant value of the portion except the lower end of the horizontal partition wall, that is, the upper end part, is At this time, the dielectric constant value of the horizontal partition wall 66b becomes smaller than the dielectric constant value of the vertical partition wall 66a (that is, the dielectric constant value 12).

As a result, almost all voltages are applied to the voltage applied to the second address electrode 62b at a portion composed of a material having a small dielectric constant value. This may be seen as black in the vicinity of the second address electrode 62b in FIG. 17. That is, it shows that the equipotential surface is densely located near the second address electrode 62b and the strength of the electric field near the second address electrode 62b is strong. As a result, as shown in FIG. 17, the intensity of the maximum electric field (Emax = 8.85E-3) is smaller than in other cases, and the probability of erroneous discharge with neighboring adjacent cells becomes small.

In addition, even when an air gap is formed inside the lower end of the horizontal partition wall 66b on the second address electrode 62b, it may be generated due to the pulse applied to the column electrode to the peripheral non-lighting cell as described in FIG. 17. It is possible to improve the image quality by preventing the discharge.

Meanwhile, referring to FIG. 18, a PDP according to another embodiment of the present invention may include top electrodes formed on a top plate (not shown), an upper dielectric layer (not shown) formed on the top plate to cover the top electrodes, and an upper dielectric layer. The lower plate 150 formed on the protective film (not shown) and the lower electrode 150 facing the upper plate with the discharge space interposed therebetween to cover the address electrode 160X and the address electrode 160X. A lower dielectric layer 164 formed on the back panel; A partition wall 166 formed vertically on the lower dielectric layer 164 to partition discharge cells, and a phosphor 126 formed on the lower dielectric layer 164 and the partition wall 166.

The top electrodes include a pair of sustain electrodes (not shown) formed side by side on the top plate. The upper dielectric layer accumulates wall charges during plasma discharge, and the protective layer prevents damage to the sustain electrode pair and the upper dielectric layer from sputtering of gas ions during plasma discharge, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. Do it.

The address electrode 160X of the lower plate 150 is formed to cross the sustain electrode pair. The address electrode 160X is supplied with a data signal for selecting cells to be displayed.

The partition wall 166 is a stripe type and formed side by side with the address electrode 160X to prevent the ultraviolet rays generated by the discharge from leaking to the adjacent discharge cells, thereby preventing electrical and optical crosstalk between adjacent discharge cells. Serves to prevent.

The partition wall 166 is formed to have a rounded upper end as shown in FIG. 19A. That is, the partition wall 166 is formed in a round shape so that the upper center portion thereof is convex. As a result, the edge of the partition wall 166 is lower than the central portion of the partition wall 166. The upper end of the partition wall 166 faces the upper plate with an air gap therebetween. Accordingly, the air gap between the top edge of the partition wall 166 and the top plate is different from the air gap between the top center portion of the partition wall 166 and the top plate.

The phosphor 126 is applied to the surfaces of the lower dielectric layer 164 and the partition wall 166 to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne for discharging is injected into the gas discharge space provided between the upper plate, the lower plate 150, and the partition wall 166.

Meanwhile, in the PDP according to another embodiment of the present invention, the partition wall 166 is formed to be stepped or chamfered around about 20 μm around the edge of the upper end as shown in FIG. 19B. That is, the upper edge of the partition 166 is stepped. The barrier rib 166 prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells. At this time, the portion requiring stepping or chamfering is the partition portion in the direction perpendicular to the address electrode. As a result, the edge of the partition wall 166 is lower than the central portion of the partition wall 166. The upper end of the partition wall 166 faces the upper plate with an air gap therebetween. Accordingly, the air gap between the top edge of the partition wall 166 and the top plate is different from the air gap between the top center portion of the partition wall 166 and the top plate.

As such, the PDP according to another embodiment of the present invention forms the upper end of the partition 166 in a round shape or a step / chamfering shape so that the maximum electric field strength of the non-lighting cell is the maximum electric field of the lit cell to which the data voltage is applied. It can be seen that it is much smaller than the intensity (Emax) of (reduced to about 1/2), thereby preventing erroneous discharge with neighboring adjacent cells. In other words, by forming the upper end portion of the partition wall 166 in a round shape or a step / chamfering shape, the intensity of the maximum electric field of the lighting cell may be weakened to weaken the electric field concentration distribution.

On the other hand, in the PDP according to another embodiment of the present invention, the dielectric constant of the portion (upper portion) except for the lower portion of the barrier rib 166 and the lower portion of the barrier rib 166 is formed differently. That is, the partition wall 166 is formed of a material having a lower dielectric constant value than the upper end thereof. For this reason, the dielectric constant value of the lower end of the partition 166 is 12 or less (for example, 1 (dielectric constant of air = 1)), and the dielectric constant value of the portion except the horizontal partition lower end, i.e., 12, is 12. It becomes abnormal.

As a result, almost all voltages are applied to the voltage applied to the address electrode at a portion composed of a material having a low dielectric constant value. This indicates that the equipotential surfaces are densely located near the address electrode 166 and the strength of the electric field near the address electrode 166 is strong. Therefore, the probability of causing an erroneous discharge with a neighboring adjacent cell becomes small.

On the other hand, in the PDP according to another embodiment of the present invention, the partition wall 166 is formed with a concave groove in the upper end as shown in Figure 19c. The barrier rib 166 prevents the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells and increases the exhaust performance. As a result, the edge of the partition wall 166 is lower than the central portion of the partition wall 166. The upper end of the partition wall 166 faces the upper plate with an air gap therebetween. Accordingly, the air gap between the top edge of the partition wall 166 and the top plate is different from the air gap between the top center portion of the partition wall 166 and the top plate.

As described above, the plasma display panel according to the present invention is formed by rounding or chamfering the upper end of the horizontal partition wall, thereby preventing mis-discharge between adjacent cells.

In addition, the plasma display panel according to the present invention may be formed of a material having a low dielectric constant at the lower end of the horizontal partition wall near the address electrode, thereby preventing cross talk between adjacent cells and improving image quality.

In addition, the plasma display panel according to the present invention forms an air gap in the lower portion of the horizontal partition wall, thereby preventing erroneous discharge caused by pulses applied to the electrodes of the peripheral non-lighting cells and improving image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a view showing an electrode structure of the plasma display panel shown in FIG.

3 is a plan view illustrating an electrode structure of another plasma display panel according to another exemplary embodiment of the prior art.

4 is a cross-sectional view of the plasma display panel taken along the line "A-A '" in FIG.

5 to 11 are diagrams showing an equipotential surface when a specific voltage is applied to a discharge cell according to the prior art.

FIG. 12 is a diagram illustrating a relative intensity of an electric field formed in left and right discharge cells when a data voltage is applied to an address electrode in FIG. 11.

13 is a plan view showing the electrode structure of the plasma display panel according to the present invention.

14 is a cross-sectional view of the plasma display panel according to the first embodiment of the present invention taken along the line "B-B '" in FIG.

15 is a cross-sectional view of the plasma display panel according to the second embodiment of the present invention taken along the line "B-B '" in FIG.

FIG. 16 is a diagram illustrating relative strengths of electric fields formed in left and right discharge cells when a data voltage is applied to an address electrode in FIG. 15; FIG.

FIG. 17 is a cross-sectional view of the plasma display panel according to the third embodiment of the present disclosure taken along the line “B-B ′” of FIG. 13.

18 is a perspective view illustrating a bottom plate structure of a plasma display panel having a stripe-shaped partition wall according to a fourth embodiment of the present invention.

FIG. 19A is a cross-sectional view of a sprip-shaped partition wall having a rounded upper end shown in FIG. 18. FIG.

FIG. 19B is a cross-sectional view of a sprip-shaped partition wall having an upper end portion of the step form shown in FIG. 18. FIG.

FIG. 19C is a cross-sectional view illustrating a sprip-shaped partition wall having a groove formed in an upper end portion shown in FIG. 18. FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 32Y, 52Y: first electrode

12Z, 32Z, 52Z: Second electrode 13Y, 13Z, 33Y, 33Z, 53Y, 53Z: Bus electrode

14,22,164: dielectric layer 16: protective film

18,150: Lower substrate 20X, 40X, 42,60X, 62,160X: Address electrode

24,46,66,166 Bulkhead 26,126 Phosphor

32a, 32c, 52a, 52c: main electrode 32b, 32d, 52b, 52d: auxiliary electrode

40a, 60a: address main electrode 40b, 60b: address auxiliary electrode

44,64: protective layer

Claims (21)

A plasma display panel in which red, green, and blue discharge cells for gradation are arranged in a delta shape and have partition walls for partitioning the discharge cells. At least a portion of the barrier rib is rounded at an upper end thereof. delete The method of claim 1, The partition wall, A first partition wall; And a second partition wall vertically connected to the first partition wall. delete The method of claim 1, And at least a portion of the partition wall is stepped at an upper edge thereof. The method of claim 1, And at least a portion of the partition wall has a concave or convex shape at an upper edge thereof. The method of claim 1, First electrodes formed on the first substrate; Second electrodes formed on a second substrate facing the first substrate with a discharge space therebetween and intersecting the first electrodes; A first dielectric layer formed on the first substrate to cover the first electrodes; A protective film formed on the first dielectric layer; A second dielectric layer formed on the second substrate to cover the second electrodes; And a phosphor formed in the second dielectric layer and the partition wall. The method of claim 7, wherein The first electrode, A metal bus electrode; And a transparent electrode connected to the metal bus electrode and having a width larger than that of the metal bus electrode. The method of claim 8, The transparent electrode, A main electrode portion; An auxiliary electrode extending from the main electrode portion toward the discharge cell; And the auxiliary electrode extends zigzag on both sides of the main electrode. The method of claim 7, wherein The second electrode, A main electrode; And an auxiliary electrode extending from both sides of the main electrode and at least partially overlapping with the first electrode. The method of claim 1, And the partition wall has a stripe shape, and a central portion of the partition wall is convex. The method of claim 1, And the barrier rib is stripe-shaped and has an upper edge stepped therein. A plasma display panel having partition walls for partitioning discharge cells, the plasma display panel comprising: And wherein the barrier rib partially differs in dielectric constant value. The method of claim 13, And an edge of the partition wall is lower than a central portion of the partition wall. The method of claim 13, The partition wall, A first partition wall; And a second partition wall vertically connected to the first partition wall. The method of claim 15, And one of the first and second barrier walls has a lower end portion with a lower dielectric constant than the upper end portion. The method of claim 16, Any one of the first and second barrier ribs has a dielectric constant lower than 12 at its lower end; Plasma display panel, characterized in that the dielectric constant value of the partition wall other than the lower end portion is 12 or more. A plasma display panel having partition walls for partitioning discharge cells, the plasma display panel comprising: An upper end of the partition wall faces the first substrate with an air gap therebetween; And an air gap between an upper edge of the partition and the first substrate is different from an air gap between an upper center portion of the partition and the first substrate. The method of claim 18, And wherein the barrier rib partially differs in dielectric constant value. The method of claim 18, And an edge of the partition wall is lower than a central portion of the partition wall. A plasma display panel having partition walls for partitioning discharge cells, the plasma display panel comprising: An upper end of the barrier rib faces the first substrate with an air gap therebetween; And wherein the barrier ribs have different dielectric constants, and the edges of the barrier ribs are lower than a central portion of the barrier ribs.