KR100532962B1 - Method for forming isolation layer in semiconductor - Google Patents
Method for forming isolation layer in semiconductor Download PDFInfo
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- KR100532962B1 KR100532962B1 KR10-2003-0091546A KR20030091546A KR100532962B1 KR 100532962 B1 KR100532962 B1 KR 100532962B1 KR 20030091546 A KR20030091546 A KR 20030091546A KR 100532962 B1 KR100532962 B1 KR 100532962B1
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- oxide film
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- 238000002955 isolation Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체소자의 소자분리막 형성방법에 관해 개시한 것으로서, 소자격리영역 및 소자형성영역이 정의된 반도체기판을 제공하는 단계와, 기판의 소자격리영역에 트렌치를 형성하는 단계와, 트렌치 내부에 월옥사이드막을 형성하는 단계와, 월옥사이드막을 포함한 기판 위에 불순물이 도핑된 다결정실리콘막을 증착하는 단계와, 결과물에 HDP 옥사이드막을 증착하여 상기 트렌치구조를 매립시키며, 상기 HDP옥사이드막을 증착하는 과정에 상기 다결정실리콘막이 산화되어 산화막으로 변화되는 단계와, HDP옥사이드막 및 산화막을 씨엠피하여 상기 트렌치를 매립시키는 소자분리막을 형성하는 단계를 포함한다.Disclosed is a method of forming a device isolation film of a semiconductor device, the method comprising: providing a semiconductor substrate having a device isolation region and a device formation region defined therein; forming a trench in the device isolation region of the substrate; Forming a wall oxide film, depositing a polycrystalline silicon film doped with an impurity on a substrate including a wall oxide film, depositing an HDP oxide film on the resultant, filling the trench structure, and depositing the polycrystalline HDP oxide film. And oxidizing the silicon film to an oxide film, and forming an isolation layer for filling the trench by CMP of the HDP oxide film and the oxide film.
Description
본 발명은 반도체 소자를 제조하는 기법에 관한 것으로, 더욱 상세하게는 트렌치 내부를 갭필시키는 HDP 옥사이드막을 증착 시, 터널산화막에 가해지는 플라즈마 데미지를 감소시키고 채널에 있는 불순물의 외부 확산을 보상해 줄 수 있는 반도체소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a technique for manufacturing a semiconductor device, and more particularly, to reduce the plasma damage to the tunnel oxide film and to compensate for the external diffusion of impurities in the channel when depositing the HDP oxide film gap gap fill the trench. A method of forming a device isolation film of a semiconductor device.
차세대 고집적 반도체소자에서 최소 선폭이 좁아지면서 트랜지스터의 쇼트채널효과(Short Channel Effect)와 채널 도판트(channel dopant)의 외부 확산(out-diffusion)이 심화된다. 플래쉬소자를 셀프어라인-STI(self aligned Shallow Trench Isolation)공정을 적용시켜 소자분리를 하는 경우, 게이트산화막이 형성된 후 HDP옥사이드막으로 갭필하기 때문에 터널 산화막에 플라즈마 데미지가 가해져서 트랜지스터 특성을 열화시키는 문제점이 있다.As the minimum line width becomes narrower in the next generation of highly integrated semiconductor devices, the short channel effect of the transistor and the out-diffusion of the channel dopant are intensified. When the device is separated by applying a self-aligned shallow trench isolation (STI) process, the flash device is gapfilled with an HDP oxide film after the gate oxide film is formed, thereby causing plasma damage to the tunnel oxide film, thereby degrading transistor characteristics. There is a problem.
따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 사이드 월 산화공정과 HDP산화막 증착 공정 사이에 불순물이 도핑된 다결정실리콘막을 증착시킴으로써, HDP옥사이드막을 증착하는 동안 상기 불순물이 도핑된 다결정실리콘막이 산화막으로 변화되어 터널 산화막에 가해지는 플라즈마 데미지를 감소시키고 채널에 있는 불순물의 외부 확산을 방지하는 반도체소자의 소자분리막 형성방법을 제공하려는 것이다.Therefore, in order to solve the above problems, an object of the present invention is to deposit a polysilicon film doped with an impurity between a sidewall oxidation process and an HDP oxide film deposition process, so that the impurity doped polysilicon film is deposited as an oxide film during the HDP oxide film deposition. The present invention provides a method for forming a device isolation film of a semiconductor device that is changed to reduce plasma damage to a tunnel oxide film and to prevent external diffusion of impurities in a channel.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성방법은 소자격리영역 및 소자형성영역이 정의된 반도체기판을 제공하는 단계와, 상기 기판의 소자격리영역에 트렌치를 형성하는 단계와, 상기 트렌치 내부에 월옥사이드막을 형성하는 단계와, 상기 월옥사이드막을 포함한 기판 위에 불순물이 도핑된 다결정실리콘막을 증착하는 단계와, 상기 결과물에 HDP 옥사이드막을 증착하여 상기 트렌치 구조를 매립시키면서 상기 다결정실리콘막을 산화시켜 산화막으로 변화시키는 단계와, 상기 HDP옥사이드막 및 산화막을 상기 트렌치 내에만 잔류하도록 씨엠피하여 소자분리막을 형성하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of forming a device isolation layer of a semiconductor device, the method including: providing a semiconductor substrate in which a device isolation region and a device formation region are defined, forming a trench in the device isolation region of the substrate; Forming a wall oxide film in the trench, depositing a doped polycrystalline silicon film on a substrate including the wall oxide film, depositing an HDP oxide film on the resultant, and burying the trench structure to oxidize the polycrystalline silicon film. And forming the device isolation layer by CMP so that the HDP oxide layer and the oxide layer remain only in the trench.
상기 월옥사이드막을 600∼700℃ 온도의 퍼니스 내에서 형성하는 것이 바람직하다.It is preferable to form the wall oxide film in a furnace at a temperature of 600 to 700 ° C.
상기 불순물이 도핑된 다결정실리콘막을 500∼600℃ 온도에서 증착하는 것이 바람직하다.It is preferable to deposit the polysilicon film doped with the impurity at a temperature of 500 to 600 ° C.
상기 불순물이 도핑된 다결정실리콘막을 20∼50Å두께로 형성하는 것이 바람직하다.It is preferable to form a polysilicon film doped with the impurity to a thickness of 20 to 50 GPa.
상기 불순물이 도핑된 다결정실리콘막에서, 상기 불순물로는 보론 및 인 중 어느 하나를 이용하는 것이 바람직하다.In the polysilicon film doped with the impurity, it is preferable to use any one of boron and phosphorus as the impurity.
(실시예)(Example)
이하, 첨부된 도면을 참고로하여 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기로 한다.Hereinafter, a method of forming an isolation layer of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 소자분리막 형성방법은, 도 1a에 도시된 바와 같이, 소자격리영역 및 소자형성영역이 정의된 반도체기판을 제공한다. 이어, 상기 기판 위에 패드산화막 및 패드질화막을 차례로 형성한 다음, 패드질화막 위에 감광막을 도포하고 노광 및 현상하여 소자격리영역을 노출시키는 감광막패턴을 형성한다.The method of forming a device isolation film of a semiconductor device according to the present invention provides a semiconductor substrate in which device isolation regions and device formation regions are defined, as shown in FIG. 1A. Subsequently, a pad oxide film and a pad nitride film are sequentially formed on the substrate, and then a photoresist film is coated on the pad nitride film, followed by exposure and development to form a photoresist pattern exposing the device isolation region.
그런다음, 상기 감광막패턴을 마스크로 이용해서 상기 패드질화막, 패드산화막 및 기판의 소정두께를 식각하여 상기 기판의 소자격리영역에 트렌치(5)를 형성한다. Then, using the photoresist pattern as a mask, a predetermined thickness of the pad nitride film, the pad oxide film, and the substrate is etched to form the trench 5 in the device isolation region of the substrate.
이후, 상기 감광막패턴을 제거한 다음, 도 1b에 도시된 바와 같이, 상기 트렌치(5)를 포함한 기판에 사이드 월 산화공정을 진행하여 트렌치(5) 내부를 덮는 월산화막(6)을 형성한다. 이때, 상기 사이드 월 산화공정은 600∼700℃온도의 퍼니스 내에서 진행한다.After removing the photoresist pattern, as shown in FIG. 1B, a sidewall oxidation process is performed on the substrate including the trench 5 to form a monthly oxide film 6 covering the inside of the trench 5. At this time, the side wall oxidation process is carried out in a furnace at 600 ~ 700 ℃ temperature.
이어, 도 1c에 도시된 바와 같이, 상기 월옥사이드막(6)을 포함한 기판 위에 불순물이 도핑된 다결정실리콘막(7)을 20∼50Å두께로 증착한다. 이때, 상기 불순물이 도핑된 다결정실리콘막(7) 증착공정은 500∼600℃온도에서 진행한다. 또한, 상기 불순물로는 보론 및 인 중 어느 하나를 이용한다.Subsequently, as illustrated in FIG. 1C, a polysilicon film 7 doped with impurities is deposited on the substrate including the wall oxide film 6 to a thickness of 20 to 50 μm. In this case, the deposition process of the polysilicon film 7 doped with the impurity is performed at a temperature of 500 to 600 ° C. In addition, any one of boron and phosphorus is used as the impurity.
그런다음, 도 1d에 도시된 바와 같이, 상기 결과물에 HDP 옥사이드막(9)을 증착하여 상기 트렌치 구조를 매립시킨다. 여기서, 상기 HDP 옥사이드막(9)은 600℃ 이상의 온도범위에서 증착하며, 이때, 상기 HDP 옥사이드막을 증착하는 동안에 증착열에 의해 상기 다결정실리콘막이 산화되어 산화막(8)으로 변화된다. 상기 다결정실리콘막이 산화되는 온도는 보통 200℃ 이상에서 가능하며, 온도가 높으면 높을수록 산화되는 다결정실리콘막의 산화가 빠르게 진행된다.Then, as shown in FIG. 1D, an HDP oxide film 9 is deposited on the resultant to fill the trench structure. Here, the HDP oxide film 9 is deposited at a temperature range of 600 ° C. or higher. In this case, the polysilicon film is oxidized and changed into an oxide film 8 by deposition heat during the deposition of the HDP oxide film. The temperature at which the polysilicon film is oxidized is usually possible at 200 ° C. or higher, and the higher the temperature, the faster the oxidation of the polycrystalline silicon film is oxidized.
이후, 도 1e에 도시된 바와 같이, 상기 패드질화막이 노출되는 시점까지 상기 HDP옥사이드막 및 산화막을 씨엠피(Chemical Mechnical Polishing)하고 나서, 패드질화막 및 패드산화막을 제거하여 트렌치(5)를 매립시키는 소자분리막(10)을 형성한다.Thereafter, as shown in FIG. 1E, the HDP oxide layer and the oxide layer are CMP (Physical Mechnical Polishing) until the pad nitride layer is exposed. Then, the pad nitride layer and the pad oxide layer are removed to fill the trench 5. The device isolation film 10 is formed.
본 발명에 따르면, 사이드 월 산화공정과 HDP산화막 증착 공정 사이에 불순물이 도핑된 다결정실리콘막을 증착시켜 주게되면 HDP산화막 증착 도중에 생기는 전자와 이온의 전하가 전기적으로 도전성이 있는 불순물이 도핑된 다결정실리콘막을 따라 기판쪽으로 흐르게 된다. 이로써 터널산화막으로 가해지는 플라즈마 데미지를 막아주게 된다.According to the present invention, when a polycrystalline silicon film doped with impurities is deposited between a sidewall oxidation process and an HDP oxide film deposition process, the charge of electrons and ions generated during the HDP oxide film deposition is doped with an impurity doped polycrystalline silicon film. Therefore, it flows toward the substrate. This prevents plasma damage to the tunnel oxide film.
전자가 터널산화막을 터널링하는 정도는 터널링산화막 두께에 반비례하므로, 불순물이 도핑된 다결정실리콘막을 통해서 전자가 흐르게 되면 초기의 전자 터널링에 의한 전자 데미지를 크게 줄여줄 수 있다. 또한, HDP산화막을 증착하는 동안 불순물이 도핑된 다결정실리콘막이 모두 산화되면 터널링 투과도가 현저히 줄어들게 된다. 그리고, 불순물이 도핑된 다결정실리콘막이 산화되면서 도핑된 산화막으로 변화되면 트렌치의 사이드월쪽으로 불순물이 공핍(depletion)되는 것을 보상해주어 소자 특성의 열화를 줄여준다.Since the degree of electron tunneling of the tunnel oxide film is inversely proportional to the thickness of the tunneling oxide film, when electrons flow through the polycrystalline silicon film doped with impurities, electron damage due to initial electron tunneling can be greatly reduced. In addition, if all of the polysilicon films doped with impurities during the deposition of the HDP oxide film are oxidized, the tunneling transmittance is significantly reduced. In addition, when the doped polysilicon film is oxidized and changed into the doped oxide film, depletion of impurities toward the sidewall of the trench is compensated to reduce deterioration of device characteristics.
이상에서와 같이, 본 발명은 사이드 월 산화공정과 HDP산화막 증착 공정 사이에 불순물이 도핑된 다결정실리콘막을 증착시켜 주게되면 HDP산화막 증착 도중에 생기는 전자와 이온의 전하가 전기적으로 도전성이 있는 불순물이 도핑된 다결정실리콘막을 따라 기판쪽으로 흐르게 된다. 이로써 터널산화막으로 가해지는 플라즈마 데미지를 막아주게 이점이 있다.As described above, in the present invention, when the polysilicon film doped with impurities is deposited between the sidewall oxidation process and the HDP oxide deposition process, the charges of electrons and ions generated during the HDP oxide deposition are doped with an electrically conductive impurity. It flows along the polysilicon film toward the substrate. This has the advantage of preventing the plasma damage to the tunnel oxide film.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1e는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도.1A to 1E are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
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| US11456171B2 (en) | 2020-11-20 | 2022-09-27 | Applied Materials, Inc. | Deep trench integration processes and devices |
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