KR100528380B1 - 클록신호디스큐시스템 - Google Patents

클록신호디스큐시스템 Download PDF

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Publication number
KR100528380B1
KR100528380B1 KR1019980705104A KR19980705104A KR100528380B1 KR 100528380 B1 KR100528380 B1 KR 100528380B1 KR 1019980705104 A KR1019980705104 A KR 1019980705104A KR 19980705104 A KR19980705104 A KR 19980705104A KR 100528380 B1 KR100528380 B1 KR 100528380B1
Authority
KR
South Korea
Prior art keywords
clock signal
site
signal
local
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980705104A
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English (en)
Korean (ko)
Other versions
KR19990076976A (ko
Inventor
다니엘 제이. 베델
찰스 에이. 밀러
Original Assignee
크레던스 시스템스 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of KR19990076976A publication Critical patent/KR19990076976A/ko
Application granted granted Critical
Publication of KR100528380B1 publication Critical patent/KR100528380B1/ko
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1019980705104A 1996-01-03 1996-12-10 클록신호디스큐시스템 Expired - Fee Related KR100528380B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/582,922 US5734685A (en) 1996-01-03 1996-01-03 Clock signal deskewing system
US8/582,922 1996-01-03
US08/582,922 1996-01-03

Publications (2)

Publication Number Publication Date
KR19990076976A KR19990076976A (ko) 1999-10-25
KR100528380B1 true KR100528380B1 (ko) 2006-02-09

Family

ID=24330982

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980705104A Expired - Fee Related KR100528380B1 (ko) 1996-01-03 1996-12-10 클록신호디스큐시스템

Country Status (5)

Country Link
US (1) US5734685A (enExample)
EP (1) EP0872069A4 (enExample)
JP (1) JP3739095B2 (enExample)
KR (1) KR100528380B1 (enExample)
WO (1) WO1997025796A1 (enExample)

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US6581126B1 (en) * 1996-12-20 2003-06-17 Plx Technology, Inc. Method, system and apparatus for a computer subsystem interconnection using a chain of bus repeaters
US5987576A (en) * 1997-02-27 1999-11-16 Hewlett-Packard Company Method and apparatus for generating and distributing clock signals with minimal skew
US6150866A (en) * 1997-04-01 2000-11-21 Fujitsu Limited Clock supplying circuit and integrated circuit device using it
US6031847A (en) * 1997-07-01 2000-02-29 Silicon Graphics, Inc Method and system for deskewing parallel bus channels
US5854797A (en) * 1997-08-05 1998-12-29 Teradyne, Inc. Tester with fast refire recovery time
US6105157A (en) * 1998-01-30 2000-08-15 Credence Systems Corporation Salphasic timing calibration system for an integrated circuit tester
US5974058A (en) * 1998-03-16 1999-10-26 Storage Technology Corporation System and method for multiplexing serial links
TW467373U (en) * 1998-04-01 2001-12-01 Asustek Comp Inc Input/output testing device of computer system
WO2000030308A2 (en) * 1998-11-13 2000-05-25 Broadcom Corporation Equalizer for multi-pair gigabit ethernet
US6201831B1 (en) 1998-11-13 2001-03-13 Broadcom Corporation Demodulator for a multi-pair gigabit transceiver
US6625206B1 (en) 1998-11-25 2003-09-23 Sun Microsystems, Inc. Simultaneous bidirectional data transmission system and method
US6449738B1 (en) * 1998-12-03 2002-09-10 International Business Machines Corporation Apparatus for bus frequency independent wrap I/O testing and method therefor
DE60035679T2 (de) * 1999-04-22 2008-06-05 Broadcom Corp., Irvine Gigabit-ethernt mit zeitverschiebungen zwischen verdrillten leitungspaaren
US6647506B1 (en) * 1999-11-30 2003-11-11 Integrated Memory Logic, Inc. Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle
US7035269B2 (en) * 2000-02-02 2006-04-25 Mcgill University Method and apparatus for distributed synchronous clocking
US7085237B1 (en) 2000-03-31 2006-08-01 Alcatel Method and apparatus for routing alarms in a signaling server
US6763016B1 (en) * 2000-03-31 2004-07-13 Alcatel Method and system for distributing a synchronization signal in a telecommunications network
US6977926B1 (en) * 2000-03-31 2005-12-20 Alcatel Method and system for providing a feedback signal in a telecommunications network
US6704881B1 (en) * 2000-08-31 2004-03-09 Micron Technology, Inc. Method and apparatus for providing symmetrical output data for a double data rate DRAM
US6788754B1 (en) 2000-10-10 2004-09-07 Hewlett-Packard Development Company, L.P. Method and apparatus for de-skewing clock edges for systems with distributed clocks
US7050512B1 (en) * 2001-01-08 2006-05-23 Pixelworks, Inc. Receiver architecture
US6920576B2 (en) * 2001-05-31 2005-07-19 Koninklijke Philips Electronics N.V. Parallel data communication having multiple sync codes
DE10148878B4 (de) * 2001-10-04 2006-03-02 Siemens Ag System und Verfahren zum Übertragen digitaler Daten
US7209492B2 (en) * 2002-04-15 2007-04-24 Alcatel DSO timing source transient compensation
US7720107B2 (en) * 2003-06-16 2010-05-18 Cisco Technology, Inc. Aligning data in a wide, high-speed, source synchronous parallel link
US20050063506A1 (en) * 2003-09-23 2005-03-24 Sony Corporation Method and system for jitter correction
KR100705502B1 (ko) * 2005-12-10 2007-04-09 한국전자통신연구원 클록 편차를 제거하는 클록 발생 장치 및 클록 수신 장치
TWI318834B (en) * 2006-06-02 2009-12-21 Hon Hai Prec Ind Co Ltd Network device and method for recovering clock signal thereof
EP2854326A1 (en) * 2007-07-20 2015-04-01 Blue Danube Labs Inc Method and system for multi-point signal generation with phase synchronized local carriers
JP4779063B2 (ja) 2008-04-07 2011-09-21 コス コーポレイション ワイヤレスネットワーク間で移行するワイヤレスイヤフォン
CA3087347C (en) 2011-08-08 2023-01-10 Larry D. Frederick Proximity detection system with concurrent rf and magnetic fields
US10838449B2 (en) * 2018-07-05 2020-11-17 International Business Machines Corporation Automatic detection of clock grid misalignments and automatic realignment
WO2020012550A1 (ja) * 2018-07-10 2020-01-16 株式会社ソシオネクスト 位相同期回路、送受信回路及び集積回路
EP4254804A3 (en) * 2019-05-05 2023-12-13 Yangtze Memory Technologies Co., Ltd. Double data rate circuit and data generation method implementing precise duty cycle control
CN113985959B (zh) * 2021-10-27 2024-03-26 中国科学院高能物理研究所 开关电容阵列芯片间时间差的校正方法、装置及存储介质

Citations (2)

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Publication number Priority date Publication date Assignee Title
US4998262A (en) * 1989-10-10 1991-03-05 Hewlett-Packard Company Generation of topology independent reference signals
US5432823A (en) * 1992-03-06 1995-07-11 Rambus, Inc. Method and circuitry for minimizing clock-data skew in a bus system

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US3496477A (en) * 1967-06-29 1970-02-17 Bell Telephone Labor Inc Clock pulse failure detector
US4447870A (en) * 1981-04-03 1984-05-08 Honeywell Information Systems Inc. Apparatus for setting the basic clock timing in a data processing system
US4411007A (en) * 1981-04-29 1983-10-18 The Manitoba Telephone System Distributed network synchronization system
CA1301261C (en) * 1988-04-27 1992-05-19 Wayne D. Grover Method and apparatus for clock distribution and for distributed clock synchronization
US5293626A (en) * 1990-06-08 1994-03-08 Cray Research, Inc. Clock distribution apparatus and processes particularly useful in multiprocessor systems
US5305451A (en) * 1990-09-05 1994-04-19 International Business Machines Corporation Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems
US5298866A (en) * 1992-06-04 1994-03-29 Kaplinsky Cecil H Clock distribution circuit with active de-skewing
US5369640A (en) * 1993-04-16 1994-11-29 Digital Equipment Corporation Method and apparatus for clock skew reduction through remote delay regulation
US5666079A (en) * 1994-05-06 1997-09-09 Plx Technology, Inc. Binary relative delay line
US5570054A (en) * 1994-09-26 1996-10-29 Hitachi Micro Systems, Inc. Method and apparatus for adaptive clock deskewing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998262A (en) * 1989-10-10 1991-03-05 Hewlett-Packard Company Generation of topology independent reference signals
US5432823A (en) * 1992-03-06 1995-07-11 Rambus, Inc. Method and circuitry for minimizing clock-data skew in a bus system

Also Published As

Publication number Publication date
EP0872069A1 (en) 1998-10-21
JP2000503191A (ja) 2000-03-14
KR19990076976A (ko) 1999-10-25
EP0872069A4 (en) 1999-12-01
WO1997025796A1 (en) 1997-07-17
JP3739095B2 (ja) 2006-01-25
US5734685A (en) 1998-03-31

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