KR100525397B1 - Systems Having Dual-Clock Distributer - Google Patents

Abstract

The present invention relates to a system having a redundant clock divider, comprising: first and second clock dividers for outputting a clock signal, operating exclusively with each other, and outputting an open signal in an active state; And a plurality of slave boards which select one of the clock signals received from the first and second clock dividers according to the open signal and supply the selected internal signal.

Therefore, there is an effect that can improve the problem that the clock supplied to the slave boards when the clock divider is mounted and mounted.

Description

Systems Having Dual-Clock Distributers

The present invention relates to a clock distribution structure, and more particularly, to a system having a redundant clock divider suitable for supplying a stable clock to slave boards when the clock divider is mounted and mounted.

Hereinafter, the prior art will be described with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a redundant clock divider and a slave board according to the prior art, and includes first and second clock dividers 11a and 11b which are exclusively in an active state to generate a clock. A plurality of slave boards (Slave Board # 1, # 2, ..., #n) (12-1 to 12) receiving a clock supplied from an active clock divider among the first and second clock dividers 11a and 11b. -n).

The first and second clock dividers 11a and 11b are each enabled by a clock module 1 generating a clock without skew and an output enable signal. It is composed of an ECL buffer 2 that is (Enable) to selectively output a clock (Clock) generated by the clock module (1).

While the ECL buffer 2 of the clock divider that is active among the first and second clock dividers 11a and 11b is enabled to output a clock generated by the clock module 1, The clock divider that is not active becomes a standby state and the ECL buffer 2 of the clock divider that is in the standby state is disabled and does not output a clock.

The outputs of the first and second clock dividers 11a and 11b are connected to each other to supply the clocks to the slave boards 12-1 to 12-n through one integrated line.

The slave boards 12-1 to 12-n receive an output supplied from the first and second clock dividers 11a and 11b using the ECL receiver 3.

In the system having the above-described configuration, when the active clock divider is dismounted, the standby clock divider recognizes that the active clock divider has been dismounted and is activated. It enters a state and supplies a clock.

Since the outputs of the two clock dividers are connected to each other, the clock is shaken when the clock divider period is changed when the clock divider is dismounted.

In addition, when a new clock divider is mounted when the clock divider operates in a single, a clock clock that is normally supplied is shaken.

In case of using general TTL signal, it is possible to prevent the clock from shaking by using HOT Swap Device. However, in case of using the differential ECL signal, it is difficult to apply HOT Swap, which prevents the clock shake. have.

An object of the present invention is to provide a system having a redundant clock divider for preventing the clock from shaking when mounting and mounting the clock divider.

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A system having a redundant clock divider according to the present invention for achieving the above object, the first and the second outputs a clock signal, and operates in an exclusively active state, and outputs an open signal in the active state 2 clock divider; And a plurality of slave boards which select one of the clock signals received from the first and second clock dividers, respectively, according to the open signal, and supply the internally selected slave signals. The first and second clock dividers include a clock. A clock module for generating a signal; And a buffer configured to output a clock signal received from the clock module. The slave board may further include: first and second receivers receiving clock signals from the first and second clock dividers, respectively; First and second delay units for delaying the output signals received from the first and second receivers, respectively; And a selector for selecting one of the output signals from the first and second delay units and outputting the selected signals according to the open signal received from the first or second clock divider. The clock signals output from the first and second clock dividers, respectively, are preferably input to the slave board through different lines. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. .

2 is a diagram illustrating the configuration of a clock divider and a slave board of a redundant structure according to the present invention, and FIG. 3 is an output waveform diagram of each part of FIG. 2.

As shown in FIG. 2, the system according to the present invention generates first and second clock dividers 21a and 21b which generate and output a clock signal and become exclusively active to output an open signal. Receives a clock signal and an open signal from the first and second clock dividers 21a and 21b and according to the open signal, a clock signal or a second clock from the first clock divider 21a. The slave boards 22-1 to 22-n select any one of the clock signals from the divider 21b.

The first and second clock dividers 21a and 21b respectively include a clock module 31 for generating a clock signal without skew and a clock signal generated by the clock module 31. It consists of an ECL buffer 32 which outputs (Clock). At this time, the ECL buffer 32 buffers a clock signal (Clock) regardless of whether the clock divider belongs to an active state or a standby state.

The first and second clock dividers 21a and 21b are exclusively in an active state, and when they become active, they output an open signal.

The clock signals Clock output from the first and second clock dividers 21a and 21b are input to the slave boards 22-1 to 22-n through different lines.

The slave board may include first and second ECL receivers 41a and 41b respectively configured to receive a clock signal (Clock) output from the first and second clock dividers 21a, and the first and second ECL receivers 41a. First and second delay units 42a and 42b for delaying the signals A and B received through 41b, respectively, and openings from the first and second clock dividers 21a and 21b. The selector 43 which selects any one of the outputs C and D of the first and second delay units 42a and 42b according to the open signal F to output the selected signal E therein. It consists of.

Next, the operation of the system according to the present invention will be described.

For convenience of explanation, it is assumed that the first clock divider 21a is an active state and the second clock divider 21b is a standby state.

The clock signal (Clock) output from the first clock divider 21a is received through the first receiver 41a of the slave board (A), and is then delayed by the first delay unit 42a for a predetermined time to be a C signal. Is output.

The clock signal Clock output from the second clock divider 21b is received through the second receiver 41b of the slave board (B), and is delayed by a second time through the second delay unit 42b. It is output as a signal.

The first clock divider 21a in the active state outputs an open signal of a "low" level. The selector 43 of the slave board receiving the open signal receives the C signal and the D signal. Selects a C signal, which is a signal derived from the first clock divider 21a, and outputs it as an E signal.

At this time, when the active first clock divider 21a is dismounted, as shown in FIG. 3, the open signal of the first clock divider 21a changes to “high” and the standby state of the first divider 21a is changed to “high”. The two clock dividers 21b become active.

As the open signal from the first clock divider 21a changes to “high”, the A signal, which is the clock signal currently being supplied, is shaken.

The selector 43 detects the open signal and selects the D signal, which is an input signal corresponding to the clock signal of the second clock divider 21b, and supplies the selected signal to a necessary place in the slave board.

In the present invention, even if the A signal is shaken, the output signal E of the selector 43 is not shaken because the first and second delay units 42a and 42b push the clock signal at the moment of hernia backward. .

This is because the clock supplied to the current selector 43 is not the clock supplied by the current clock divider, but the clock supplied previously is a delayed clock.

In the case where the standby clock divider is dismounted, the clock selected and supplied by the selector 43 is an active clock, which is supplied through a separate line from the standby clock. There is no shaking.

In addition, when only one clock divider is mounted and is supplying a clock, even if a new clock divider is mounted, the slave boards use the clock supplied by the existing clock divider, so that the clock that is shaken during the installation is not affected.

The system having the redundant clock divider of the present invention as described above has the following effects.

First, it is possible to improve a problem that the clock supplied to the slave boards is shaken when the clock divider is mounted and mounted.

Second, by adding an ECL receiver to the slave board and additionally implementing both the delay unit and the selector in the previously used FPGA, it is possible to implement a low price without adding an external device.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.

1 is a view showing the configuration of a clock divider and slave boards of a redundant structure according to the prior art,

2 is a diagram illustrating a configuration of a clock divider and slave boards of a redundant structure according to the present invention;

3 is a diagram illustrating output waveforms of each part of FIG. 2.

** Description of the symbols for the main parts of the drawings **

21a, 21b: first and second clock divider

22-1 to 22-n: slave boards

Claims (4)

First and second clock dividers for outputting a clock signal, operating exclusively with each other, and outputting an open signal in an active state; And A plurality of slave boards to select any one of the clock signal received from the first and second clock divider in accordance with the open signal and to supply therein A system having a redundant clock divider comprising. The method of claim 1, wherein the first and second clock divider, A clock module for generating a clock signal; And A buffer for outputting the clock signal received from the clock module A system having a redundant clock divider comprising. The method of claim 1, wherein the slave board, First and second receivers for receiving clock signals from the first and second clock dividers, respectively; First and second delay units for delaying the output signals received from the first and second receivers, respectively; And According to the open signal received from the first or second clock divider, the selector for selecting any one of the output signal from the first or second delay unit to output the internally A system having a redundant clock divider comprising. The clock signal of claim 1, wherein the clock signals output from the first and second clock dividers are respectively. And a redundant clock divider, which is input to the slave board through different lines.